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| 32 SH-2E SH7055S F-ZTAT TM TM Hardware Manual Renesas 32-bit RISC Microcomputer SuperH RISC engine Family/SH7000 Series The revision list can be viewed directly by clicking the title page.The revision list summarizes the locations of revisions and additions. Details should always be checked by referring to the relevant text. Rev. 2.00 2003.7.17 www.renesas.com Notes regarding these materials 1. This document is provided for reference purposes only so that Renesas customers may select the appropriate Renesas products for their use. Renesas neither makes warranties or representations with respect to the accuracy or completeness of the information contained in this document nor grants any license to any intellectual property rights or any other rights of Renesas or any third party with respect to the information in this document. 2. Renesas shall have no liability for damages or infringement of any intellectual property or other rights arising out of the use of any information in this document, including, but not limited to, product data, diagrams, charts, programs, algorithms, and application circuit examples. 3. You should not use the products or the technology described in this document for the purpose of military applications such as the development of weapons of mass destruction or for the purpose of any other military use. When exporting the products or technology described herein, you should follow the applicable export control laws and regulations, and procedures required by such laws and regulations. 4. All information included in this document such as product data, diagrams, charts, programs, algorithms, and application circuit examples, is current as of the date this document is issued. Such information, however, is subject to change without any prior notice. Before purchasing or using any Renesas products listed in this document, please confirm the latest product information with a Renesas sales office. Also, please pay regular and careful attention to additional and different information to be disclosed by Renesas such as that disclosed through our website. (http://www.renesas.com ) 5. Renesas has used reasonable care in compiling the information included in this document, but Renesas assumes no liability whatsoever for any damages incurred as a result of errors or omissions in the information included in this document. 6. When using or otherwise relying on the information in this document, you should evaluate the information in light of the total system before deciding about the applicability of such information to the intended application. Renesas makes no representations, warranties or guaranties regarding the suitability of its products for any particular application and specifically disclaims any liability arising out of the application and use of the information in this document or Renesas products. 7. With the exception of products specified by Renesas as suitable for automobile applications, Renesas products are not designed, manufactured or tested for applications or otherwise in systems the failure or malfunction of which may cause a direct threat to human life or create a risk of human injury or which require especially high quality and reliability such as safety systems, or equipment or systems for transportation and traffic, healthcare, combustion control, aerospace and aeronautics, nuclear power, or undersea communication transmission. If you are considering the use of our products for such purposes, please contact a Renesas sales office beforehand. Renesas shall have no liability for damages arising out of the uses set forth above. 8. Notwithstanding the preceding paragraph, you should not use Renesas products for the purposes listed below: (1) artificial life support devices or systems (2) surgical implantations (3) healthcare intervention (e.g., excision, administration of medication, etc.) (4) any other purposes that pose a direct threat to human life Renesas shall have no liability for damages arising out of the uses set forth in the above and purchasers who elect to use Renesas products in any of the foregoing applications shall indemnify and hold harmless Renesas Technology Corp., its affiliated companies and their officers, directors, and employees against any and all damages arising out of such applications. 9. You should use the products described herein within the range specified by Renesas, especially with respect to the maximum rating, operating supply voltage range, movement power voltage range, heat radiation characteristics, installation and other product characteristics. Renesas shall have no liability for malfunctions or damages arising out of the use of Renesas products beyond such specified ranges. 10. Although Renesas endeavors to improve the quality and reliability of its products, IC products have specific characteristics such as the occurrence of failure at a certain rate and malfunctions under certain use conditions. Please be sure to implement safety measures to guard against the possibility of physical injury, and injury or damage caused by fire in the event of the failure of a Renesas product, such as safety design for hardware and software including but not limited to redundancy, fire control and malfunction prevention, appropriate treatment for aging degradation or any other applicable measures. Among others, since the evaluation of microcomputer software alone is very difficult, please evaluate the safety of the final products or system manufactured by you. 11. In case Renesas products listed in this document are detached from the products to which the Renesas products are attached or affixed, the risk of accident such as swallowing by infants and small children is very high. You should implement safety measures so that Renesas products may not be easily detached from your products. Renesas shall have no liability for damages arising out of such detachment. 12. This document may not be reproduced or duplicated, in any form, in whole or in part, without prior written approval from Renesas. 13. Please contact a Renesas sales office if you have any questions regarding the information contained in this document, Renesas semiconductor products, or if you have any other inquiries. Rev.2.0, 07/03, page ii of xxxviii General Precautions in the Handling of MPU/MCU Products The following usage notes are applicable to all MPU/MCU products from Renesas. For detailed usage notes on the products covered by this manual, refer to the relevant sections of the manual. If the descriptions under General Precautions in the Handling of MPU/MCU Products and in the body of the manual differ from each other, the description in the body of the manual takes precedence. 1. Handling of Unused Pins Handle unused pins in accord with the directions given under Handling of Unused Pins in the manual. The input pins of CMOS products are generally in the high-impedance state. In operation with an unused pin in the open-circuit state, extra electromagnetic noise is induced in the vicinity of LSI, an associated shoot-through current flows internally, and malfunctions may occur due to the false recognition of the pin state as an input signal. Unused pins should be handled as described under Handling of Unused Pins in the manual. 2. Processing at Power-on The state of the product is undefined at the moment when power is supplied. The states of internal circuits in the LSI are indeterminate and the states of register settings and pins are undefined at the moment when power is supplied. In a finished product where the reset signal is applied to the external reset pin, the states of pins are not guaranteed from the moment when power is supplied until the reset process is completed. In a similar way, the states of pins in a product that is reset by an on-chip power-on reset function are not guaranteed from the moment when power is supplied until the power reaches the level at which resetting has been specified. 3. Prohibition of Access to Reserved Addresses Access to reserved addresses is prohibited. The reserved addresses are provided for the possible future expansion of functions. Do not access these addresses; the correct operation of LSI is not guaranteed if they are accessed. 4. Clock Signals After applying a reset, only release the reset line after the operating clock signal has become stable. When switching the clock signal during program execution, wait until the target clock signal has stabilized. When the clock signal is generated with an external resonator (or from an external oscillator) during a reset, ensure that the reset line is only released after full stabilization of the clock signal. Moreover, when switching to a clock signal produced with an external resonator (or by an external oscillator) while program execution is in progress, wait until the target clock signal is stable. 5. Differences between Products Before changing from one product to another, i.e. to one with a different type number, confirm that the change will not lead to problems. The characteristics of MPU/MCU in the same group but having different type numbers may differ because of the differences in internal memory capacity and layout pattern. When changing to products of different type numbers, implement a system-evaluation test for each of the products. Rev.2.0, 07/03, page iii of xxxviii Rev.2.0, 07/03, page iv of xxxviii Preface The SH7055SF is a single-chip RISC (reduced instruction set computer) microcomputer that has an original 32-bit RISC type CPU as its core, and also includes peripheral functions necessary for system configuration. The SH7055SF is equipped with on-chip peripheral functions necessary for system configuration, including a floating-point unit (FPU), large-capacity ROM and RAM, a direct memory access controller (DMAC), timers, a serial communication interface (SCI), Controller area network (HCAN), A/D converter, interrupt controller (INTC), and I/O ports, therefore, it can be used as a microprocessor built in a high-level control system. The SH7055SF is an F-ZTATTM* (Flexible Zero Turn-Around Time) version with flash memory as its on-chip ROM, and it can rapidly and flexibly deal with each situation on an application system with fluid specifications from an early stage of mass production to full-scale production. Note: F-ZTATTM is a trademark of Renesas Technology Corp. Target users: This manual was written for users who will be using the SH7055S F-ZTAT in the design of application systems. Users of this manual are expected to understand the fundamentals of electrical curcuits, logical circuits, and microcomputers. Objective: This manual was written to explain the hardware functions and electrical characteristics of the SH7055S F-ZTAT to the above users. Refer to the SH-2E Programming Manual for a detailed description of the instruction set. Notes on reading this manual: * In order to understand the overall functions of the chip Read the manual according to the contents. This manual can be roughly categorized into parts on the CPU, system control functions, peripheral functions and electrical characteristics. * In order to understand the details of the CPU's functions Read the SH-2E Programming Manual. Rule: Bit order: The MSB (most significant bit) is on the left and the LSB (least significant bit) is on the right. Releated Manuals: The latest versions of all related manuals are available from our web site. Please ensure you have the latest versions of all documents you require. http://www.renesas.com/ Rev.2.0, 07/03, page v of xxxviii SH7055S F-ZTAT manuals: Manual Title SH7055S F-ZTAT Hardware Manual SH-2E Programming Manual ADE No. This manual Users manuals for development tools: Manual Title SH Series C/C++ Compiler, Assembler, Optimizing Linkage Editor User's Manual SH Series Simulator/Debugger (for Windows) User's Manual SH Series Simulator/Debugger (for UNIX) User's Manual High-Performance Embedded Workshop User's Manual ADE No. ADE-702-246 ADE-702-186 ADE-702-203 ADE-702-201 Application note: Manual Title C/C++ Compiler ADE No. Rev.2.0, 07/03, page vi of xxxviii Revisions and Additions in This Editions Item 2.4.1 Instruction Set by Classification Table 2.16 Branch Instructions 3.6 Usage Notes 3. Restrictions of the FADD and FSUB instructions 5.3.1 Connecting a Crystal Oscillator Figure 5.3 Connecting of Crystal Oscillator(Example) Table 5.3 Damping Resistance Values(Recommended Values) 75, 76 Recommended value amended CL1=CL2=18-22 pF (recommended value) Table amended Frequency (MHz) Parameter Rd () 5 500 10 0 Page Revisions (See Manual for Details) 53 Table amended BF/S label 10001111dddddddd Delayed branch, if T = 0, disp x 2 + PC PC; if T = 1, nop 2/1* -- 69, 70 Newly added Rev.2.0, 07/03, page vii of xxxviii Item 5.4 Usage Notes PLL Oscillation Power Supply Figure 5.7 Points for Caution in PLL Power Supply Connection Figure 5.8 Actual Example of Board Design Page Revisions (See Manual for Details) 77, 78 Description deleted PLL Oscillation Power Supply: Separate PLLVCC and PLLVSS from the other VCC and VSS lines at the board power supply source, ... Figures amended PLLCAP Rp PLLVCC CPB PLLVSS VCC CB VSS Recommended values CPB, CB: 0.1F Rp: 200 PLLVSS PLLCAP PLLVCC XTAL VCC EXTAL VSS 6.7 Stack Status after Exception 92 Processing Ends Table 6.11 Stack Status After Exception Processing Ends Table amended General illegal instruction SP Address of general illegal instruction SR 32 bits 32 bits Rev.2.0, 07/03, page viii of xxxviii Item 11.1.1 Features Page Revisions (See Manual for Details) 191 to Description amended 193 Prescaler 1/1 to 1/32 clock scaling possible in initial stage for channels 0 to 8, 10, and 11 Channels 1 to 5 enable TI10 pin input, multiple the TI10 pin input (correction), and select AGCK and AGCKM. Channel 2 Provision for forcible cutoff of channel 8 downcounters(DCNT8I to P) Channel 8 Reload function can be set to eight 16-bit down counters (DCNT8I to DCNT8P) Channel 9 * Channel 9 has six event counters and six general registers, allowing the following operations: Channel 10 has a 32-bit output compare and input capture register, free-running counter, 16-bit freerunning counter, output compare/input capture register, reload register, 8-bit event counter, and output compare register, and one 16-bit reload counter, allowing the following operations: Reload count possible with 1/32, 1/64, 1/128, or 1/256 times the captured value Channel 11 Waveform output at compare match: 0 output, 1 output, and toggle output selectable Input capture function: Detection at rising edge, falling edge, and both edges Compare-match signal can be output at the APC by using a general register as a output compare register Channel 10 * Rev.2.0, 07/03, page ix of xxxviii Item 11.1.1 Features Table 11.1 ATU-II functions Page Revisions (See Manual for Details) 195, Table amended 196 Channel 1 (-/32) x (1/2n) (n = 0-5) TCLKA, TCLKB, AGCK, AGCKM Channel 2 (-/32) x (1/2n) (n = 0-5) TCLKA, TCLKB, AGCK, AGCKM Channels 3-5 (-/32) x (1/2n) (n = 0-5) TCLKA, TCLKB, AGCK, AGCKM GR10G OCR10AH, OCR10AL, OCR10B, NCR10, TCCLR10 11.1.3 Register Configuration Table 11.3 ATU-II Registers 201 Table amended TSTR1 TSTR2 TSTR3 PSCR1 PSCR2 PSCR3 PSCR4 R/W R/W R/W R/W R/W R/W R/W H'00 H'00 H'00 H'00 H'00 H'00 H'00 11.2.2 Prescaler Registers(PSCR) 227 Bit Table amended Bit: 7 -- Initial value: R/W: x = 1 to 4 0 R 6 -- 0 R 5 -- 0 R 4 PSCxE 0 R/W 3 PSCxD 0 R/W 2 PSCxC 0 R/W 1 PSCxB 0 R/W 0 PSCxA 0 R/W 11.2.4 Timer I/O Control Registers(TIOR) Timer I/O Control Registers 3A, 3B, 4A, 4B, 5A, 5B(TIOR3A, TIOR3B, TIOR4A, TIOR4B, TIOR5A, TIOR5B) 246, Table amended 247 Bits 6 to 4 1 0 0 1 1 0 GR is an input capture register (input capture by channel 3 and 9 compare-match enabled) Input capture disabled (In channel 3 only, GR cannot be written to) Input capture in GR on rising edge at TIOxx pin (GR cannot be written to) Input capture in GR on falling edge at TIOxx pin (GR cannot be written to) Bits 2 to 0 1 0 0 1 1 0 GR is an input capture register (input capture by channel 3 and 9 compare-match enabled) Input capture disabled (In channel 3 only, GR cannot be written to) Input capture in GR on rising edge at TIOxx pin (GR connot be written to) Input capture in GR on falling edge at TIOxx pin (GR connot be written to) Rev.2.0, 07/03, page x of xxxviii Item Page Revisions (See Manual for Details) Description amended At the same time, the buffer register (BFR) value is transferred to the duty register (DTR). Output pin (TO6A to TO6D, TO7A to TO7D) of corresponding channnel will be 0 when H'0000 of BFR is 0 output and otherwise will Description amended ...an input clock and is cleared to the initial value by input capture input (TI10)(AGCK). 11.2.22 Cycle Registers (CYLR) 335 Cycle Registers (CYLR6A to CYLR6D, CYLR7A to CYLR7D) 11.2.26 Channel 10 Registers Counters(TCNT) Free-Running Counter 10AH,AL (TCNT10AH, TCNT10AL) 11.2.26 Channel 10 Registers Registers (TCNT) Input Capture Register 10AH, AL (ICR10AH, ICR10AL) 11.3.1 Overview Channels 6 and 7 338 342 Description amended At the same time, ICF10A in timer status register 10 (TSR10) is set to 1. 355 Description amended Do not set a value in DTR that will result in the condition DTR > CYLR. When H'0000 is set to DTR, do not have DTR directly read H'0000. Set BFR to H'0000 and set H'0000 by forwarding from BFR to DTR. If H'0000 is directly set to DTR, duty may not be 0%. 11.3.8 Twin-Capture Function 365 Description amended Line 4 When TCNT0, TCNT1A, and TCNT2A in channel 0, channel 1, and channel 2 are started by a setting in the timer status register (TSR), and an edge detection is carried out by the ICR0A input as a trigger signal, the TCNT1A value is transferred to OSBR1, and the TCNT2A value to OSBR2. Edge detection is as described in section 11.3.4, Input Capture Function. Rev.2.0, 07/03, page xi of xxxviii Item 11.3.9 PWM Timer Function Figure 11.21 PWM Timer Operation Page Revisions (See Manual for Details) 366, Description amended 367 If the DTR value is H'0000, the output does not change (0% duty). However, when H'0000 is set to DTR, do not directly write H'0000 to DTR. Set H'0000 to BFR and forward it from BFR to DTR. If H'0000 is directly set to DTR, duty may not be 0%. A duty of 100% is specified by setting DTR = CYLR. Do not set a value in DTR that will result in the condition DTR > CYLR. Figure amended * TO6A amended PWM output does not change for one cycle after activation* Note added * PWM output is not guaranteed because retained value is output for one cycle after activation. Figure replaced 11.3.9 PWM Timer Function Figure 11.22 Complementary PWM Mode Operation 11.3.12 Channel 10 Functions Inter-Edge Measurement Function and Edge Input Cessation Detection Function: Figure 11.28 TCNT10A Capture Operation and Compare-Match Operation 11.7 Usage Notes Contention between DCNT Write and Counter Clearing by Underflow: Figure 11.72 Contention between DCNT Write and Underflow 11.7 Usage Notes ATU Pin Setting: 368 372 Figure amended 12345677 1234 5678 00000001 55555555 414 Note added Figure amended Underflow signal H'5555 is written to the DCNT because the write to the DCNT has priority 0001 0000 5555 DCNT 418 Description amended When a port is set to the ATU pin function, the following points must be noted because input capture or count operation may occur. 17.4.2 Scan Mode Figure 17.4 Example of A/D Converter Operation(Scan Mode(Single-Cycle Scan), Channels AN0 to AN11 Selected) 608 Figure amended Continuous A/D conversion Set* ADST Clear Rev.2.0, 07/03, page xii of xxxviii Item 22.1 Features * * Programming/erasing time Number of programming Page Revisions (See Manual for Details) 736 Description amended * Programming/erasing time The flash memory programming time is tP ms (typ) in 128-byte simultaneous programming and tP/128ms per byte. The erasing time is tE s (typ) per block. Number of programming The number of flash memory programming can be up to NWEC times. * 22.4.3 Programming/Erasing Interface Parameters (2) Programming/Erasing Initialization 22.5.3 User Boot Mode 758 Description added Line 13 The general registers R8 to R15 are stored. The general registers R0 to R7 can be used without being stored. 782 Description added Line 3 When the reset start is executed in user boot mode, the check routine for flash-memory related registers runs. While the check routine is running, the RAM area about 1.2 kbytes from H'FFFF6800 is used by the routine and 4 bytes from H'FFFFDFFC is used as a stack area. NMI and all other interrupts cannot be accepted. Neither can the AUD be used in this period. This period is approximately 100 s while operating at an internal frequency of 40 MHz. (1) User Boot Mode Initiation 22.7 Flash Memory Emulation 791 in RAM Note: Description added Note: Setting the RAMS bit to 1 puts all the blocks in flash memory in the programming/erasing-protected state regardless of the values of the RAM2 to RAM0 bits (emulation protection). Clear the RAMS bit to 0 before actual programming or erasure. RAM emulation can be performed when the user boot MAT is selected. However, programming/erasing user boot MAT can be performed only in boot mode or program mode. Rev.2.0, 07/03, page xiii of xxxviii Item 22.8.3 Other Notes 2. User branch processing intervals Table 22.11 Initiation Intervals of User Branch Processing Table 22.12 Required Period for Initiating User Branch Processing 4. State in which AUD operation is disabled and interrupts are ignored Page Revisions (See Manual for Details) 797 Table amended and added Minimum Interval Approximately 19 s Approximately 19 s Processing Programming Erasing Max. Approximately 113 s Approximately 85 s Min. Approximately 113 s Approximately 45 s Description added Checking the flash-memory related registers immediately after user boot mode is initiated (Approximately 100 s when operation with internal frequency of 40 MHz is carried out after the reset signal is released.) 827 Description added Command: Read start address (four bytes): Size of data to be read Error response: H'2A: Address error The start address for reading is not in the MAT. H'2B: Size error The read size exceeds the MAT, the last address for reading calculated from the start address for reading and the read size is not in the MAT, or read size is 0. 22.10.1 Serial Communication Interface Specification for Boot Mode (3) Memory read 24.3.1 Transition to Hardware Standby Mode 854 Description added The chip enters hardware standby mode when the HSTBY and RES pins go low. Set the pins following to mode setup pin shown in section 4, Operating modes. Operation with other pin set up are not guaranteed. Hardware standby mode reduces power consumption drastically by halting all SH7055SF functions Rev.2.0, 07/03, page xiv of xxxviii Item Page Revisions (See Manual for Details) 26.1 Absolute Maximum Ratings 861, Table amended Table 26.1 Absolute Maximum 862 Ratings Power supply voltage* PVCC1 and PVCC2 pins PVCC -0.3 to +6.5 Topr Operating temperature (except writing or erasing onchip flash memory) Operating temperature (writing or erasing on-chip flash memory) Storage temperature TWEopr -40 to +125 -40 to +85 Tstg -55 to +125 Note added Temperature Range for Operation 85 to 105 C Accumulated Time 3000 hours 26.2 DC Characteristics Table 26.2 Correspondence between Power Supply Names and Pins 869 Table amended 169 PC4 Rev.2.0, 07/03, page xv of xxxviii Item 26.2 DC Characteristics Table 26.4 DC Characteristics [Operating precautions] Page Revisions (See Manual for Details) 874 to Table amended 876 Conditions: V = PLLV = 3.3 V 0.3 V, PV 1 = 5.0 V CC CC CC 0.5 V/3.3 V 0.3 V, PVCC2 = 5.0 V 0.5 V, AVCC = 5.0 V 0.5 V, AVref = 4.5 V to AVCC, VSS = PLLVSS = AVSS = 0 V, Ta = -40C to 125C. When PVCC1 = 3.3 V 0.3 V, VCC = PVCC1. When writing or erasing on-chip flash memory, Ta = -40C to 85C. Input highlevel voltage (except Schmitt trigger input voltage) Input lowlevel voltage (except Schmitt trigger input voltage) , NMI, FWE, MD2-0, VIH VCC - 0.5 -- 5.8 V 2.7 V VCC 3.6V , NMI, FWE, , MD2-0, , , AUDMD PG0, PL11 Other input pins VIL -0.3 -- 0.5 V 2.7 V VCC 3.6V -0.3 -0.3 -- -- PVCC2 x V 0.3 0.8 V 1 2 Input leak current , NMI, FWE, MD2-0, , EXTAL (Standby) | lin | -- -- 3.0* 6.0* A A A A Vin = 0.5 V to 5.8 V Vin = 0.5 V to VCC - 0.5 V Vin = 0.5 V to VCC - 0.5 V Vin = 0.5 V to PVCC2 - 0.5 V -- -- 3.0* 6.0* 3.0* 6.0* 1 2 1 TMS, , TDI, TCK (Standby) AUDMD, AUDCK, , AUDATA3-0 (Standby) (Standby) -- -- 2 1 2 -- -- 3.0* 6.0* -- -- 3.0* 6.0 1 A A 2 1 Vin = 0.5 to AV PVCC2 - 0.5 V Vin = 0 to AVCC A/D port -- -- 0.2 0.4 2 Input leak current D15-D0, , | lin | -- -- 3.0* 6.0* 1 A 2 Vin = 0.5 V to PVCC1 - 0.5 V PVCC1 = 3.3 V 0.3 V Vin = 0.5 V to PVCC1 - 0.5 V PVCC1 = 3.3 V 0.3 V Vin = 0.5 V to PVCC2 - 0.5 V Vin = 0 V Vin = 0 V PE15-PE0, PF15- PF0, PH15-PH0 (When in MCU expansion mode) Other input pins -- -- 3.0* 6.0* 3.0* 6.0* 1 A 2 -- -- 1 A A A 2 Input pull-up TMS, , TDI, TCK -Ipu MOS current (pull-up characteristic) AUDMD, AUDCK, , AUDATA3-0 (pull-up characteristic) Input pulldown MOS current Three-state leak current (while OFF) (pull-down characteristic) A21-A0, D15-D0, - , , , , (When in MCU expansion mode) Ipd -- -- -- -- 350 800 -- -- 500 A Vin = PVCC2 l Its l -- -- 3.0* 6.0* 1 A 2 Vin = 0.5 to PVCC1 - 0.5 V PVCC1 = 3.3 V 0.3 V Rev.2.0, 07/03, page xvi of xxxviii Item 26.2 DC Characteristics Table 26.4 DC Characteristics [Operating precautions] Page Revisions (See Manual for Details) 877 to Current consumption 878 Normal operation Sleep Standby ICC -- -- -- -- -- Write operation Analog supply current During A/D conversion Awaiting A/D conversion AlCC -- -- -- 50 40 50 -- -- 60 1.2 1 80 60 200 500 1000 90 5 30 mA mA A A A mA mA A Ta 50C 50C < Ta105C Ta > 105C VCC = 3.3 V f = 40 MHz f = 40 MHz During A/D Reference power supply conversions current Awaiting A/D conversion RAM standby voltage Notes: *1 Ta 105C *2 Ta > 105C Alref -- -- 1.3 1.1 -- 5 10 -- mA A V AVref = 5 V VRAM 2.7 VCC Description added [Operating precautions] 2. The current consumption is measured when VIHmin = VCC - 0.3 V/PVCC - 0.3 V, VIL = 0.3 V, with all output pins unloaded. 26.2 DC Characteristics Table 26.5 Permitted Output Current Values 879 Table amended Conditions: VCC = PLLVCC = 3.3 V 0.3 V, PVCC1 = 5.0 V 0.5 V/3.3 V 0.3 V, PVCC2 = 5.0 V 0.5 V, AVCC = 5.0 V 0.5 V, AVref = 4.5 V to AVCC, VSS = PLLVSS = AVSS = 0 V, Ta = -40C to 125C. When PVCC1 = 3.3 V 0.3 V, VCC = PVCC1. When writing or erasing on-chip flash memory, Ta = -40C to 85C. Output low-level permissible current (per pin) Output low-level permissible current (total) Output high-level permissible current (per pin) Output high-level permissible current (total) IOL IOL IOH IOL -- -- -- -- -- -- -- -- 6 80 2 25 mA mA mA mA Rev.2.0, 07/03, page xvii of xxxviii Item 26.3.1 Timing for switching the power supply on/off Table 26.6 Timing for switching the power supply on/off Page Revisions (See Manual for Details) 880 Conditions amended Conditions: VCC = PLLVCC = 3.3 V 0.3 V, PVCC1 = 5.0 V 0.5 V/3.3 V 0.3 V, PVCC2 = 5.0 V 0.5 V, AVCC = 5.0 V 0.5 V, AVref = 4.5 V to AVCC, VSS = PLLVSS = AVSS = 0 V, Ta = -40C to 125C. When PVCC1 = 3.3 V 0.3 V, VCC = PVCC1. When writing or erasing on-chip flash memory, Ta = -40C to 85C. 881 Conditions amended Conditions: VCC = PLLVCC = 3.3 V 0.3 V, PVCC1 = 5.0 V 0.5 V/3.3 V 0.3 V, PVCC2 = 5.0 V 0.5 V, AVCC = 5.0 V 0.5 V, AVref = 4.5 V to AVCC, VSS = PLLVSS = AVSS = 0 V, Ta = -40C to 125C. When PVCC1 = 3.3 V 0.3 V, VCC = PVCC1. When writing or erasing on-chip flash memory, Ta = -40C to 85C. 883 Table amended Conditions: VCC = PLLVCC = 3.3 V 0.3 V, PVCC1 = 5.0 V 0.5 V/3.3 V 0.3 V, PVCC2 = 5.0 V 0.5 V, AVCC = 5.0 V 0.5 V, AVref = 4.5 V to AVCC, VSS = PLLVSS = AVSS = 0 V, Ta = -40C to 125C. When PVCC1 = 3.3 V 0.3 V, VCC = PVCC1. When writing or erasing on-chip flash memory, Ta = -40C to 85C. pulse width setup time MD2-MD0 setup time tRESW tRESS tMDS 20 40 20 -- -- -- tcyc ns tcyc Figure 26.5 26.3.2 Clock Timing Table 26.7 Clock Timing 26.3.3 Control Signal Timing Table 26.8 Control Signal Timing 26.3.4 Bus Timing Table 26.9 Bus Timing 886 Conditions amended Conditions: VCC = PLLVCC = 3.3 V 0.3 V, PVCC1 = 5.0 V 0.5 V/3.3 V 0.3 V, PVCC2 = 5.0 V 0.5 V, AVCC = 5.0 V 0.5 V, AVref = 4.5 V to AVCC, VSS = PLLVSS = AVSS = 0 V, Ta = -40C to 125C. When PVCC1 = 3.3 V 0.3 V, VCC = PVCC1. When writing or erasing on-chip flash memory, Ta = -40C to 85C. Rev.2.0, 07/03, page xviii of xxxviii Item 26.3.5 Advanced Timer Unit Timing and Advance Pulse Controller Timing Table 26.10 Advanced Timer Unit Timing and Advanced Pulse Controller Timing Page Revisions (See Manual for Details) 890 Conditions amended Conditions: VCC = PLLVCC = 3.3 V 0.3 V, PVCC1 = 5.0 V 0.5 V/3.3 V 0.3 V, PVCC2 = 5.0 V 0.5 V, AVCC = 5.0 V 0.5 V, AVref = 4.5 V to AVCC, VSS = PLLVSS = AVSS = 0 V, Ta = -40C to 125C. When PVCC1 = 3.3 V 0.3 V, VCC = PVCC1. When writing or erasing on-chip flash memory, Ta = -40C to 85C. 892 Conditions amended Conditions: VCC = PLLVCC = 3.3 V 0.3 V, PVCC1 = 5.0 V 0.5 V/3.3 V 0.3 V, PVCC2 = 5.0 V 0.5 V, AVCC = 5.0 V 0.5 V, AVref = 4.5 V to AVCC, VSS = PLLVSS = AVSS = 0 V, Ta = -40C to 125C. When PVCC1 = 3.3 V 0.3 V, VCC = PVCC1. When writing or erasing on-chip flash memory, Ta = -40C to 85C. 893 Conditions amended Conditions: VCC = PLLVCC = 3.3 V 0.3 V, PVCC1 = 5.0 V 0.5 V/3.3 V 0.3 V, PVCC2 = 5.0 V 0.5 V, AVCC = 5.0 V 0.5 V, AVref = 4.5 V to AVCC, VSS = PLLVSS = AVSS = 0 V, Ta = -40C to 125C. When PVCC1 = 3.3 V 0.3 V, VCC = PVCC1. When writing or erasing on-chip flash memory, Ta = -40C to 85C. 894 Conditions amended Conditions: VCC = PLLVCC = 3.3 V 0.3 V, PVCC1 = 5.0 V 0.5 V/3.3 V 0.3 V, PVCC2 = 5.0 V 0.5 V, AVCC = 5.0 V 0.5 V, AVref = 4.5 V to AVCC, VSS = PLLVSS = AVSS = 0 V, Ta = -40C to 125C. When PVCC1 = 3.3 V 0.3 V, VCC = PVCC1. When writing or erasing on-chip flash memory, Ta = -40C to 85C. 26.3.6 I/O Port Timing Table 26.11 I/O Port Timing 26.3.7 Watchdog Timer Timing Table 26.12 Watchdog Timer Timing 26.3.8 Serial Communication Interface Timing Table 26.13 Serial Communication Interface Timing Rev.2.0, 07/03, page xix of xxxviii Item 26.3.9 HCAN Timing Table 26.14 HCAN Timing Page Revisions (See Manual for Details) 896 Conditions amended Conditions: VCC = PLLVCC = 3.3 V 0.3 V, PVCC1 = 5.0 V 0.5 V/3.3 V 0.3 V, PVCC2 = 5.0 V 0.5 V, AVCC = 5.0 V 0.5 V, AVref = 4.5 V to AVCC, VSS = PLLVSS = AVSS = 0 V, Ta = -40C to 125C. When PVCC1 = 3.3 V 0.3 V, VCC = PVCC1. When writing or erasing on-chip flash memory, Ta = -40C to 85C. 897 Conditions amended Conditions: VCC = PLLVCC = 3.3 V 0.3 V, PVCC1 = 5.0 V 0.5 V/3.3 V 0.3 V, PVCC2 = 5.0 V 0.5 V, AVCC = 5.0 V 0.5 V, AVref = 4.5 V to AVCC, VSS = PLLVSS = AVSS = 0 V, Ta = -40C to 125C. When PVCC1 = 3.3 V 0.3 V, VCC = PVCC1. When writing or erasing on-chip flash memory, Ta = -40C to 85C. 899 Conditions amended Conditions: VCC = PLLVCC = 3.3 V 0.3 V, PVCC1 = 5.0 V 0.5 V/3.3 V 0.3 V, PVCC2 = 5.0 V 0.5 V, AVCC = 5.0 V 0.5 V, AVref = 4.5 V to AVCC, VSS = PLLVSS = AVSS = 0 V, Ta = -40C to 125C. When PVCC1 = 3.3 V 0.3 V, VCC = PVCC1. When writing or erasing on-chip flash memory, Ta = -40C to 85C. 901 Conditions amended Conditions: VCC = PLLVCC = 3.3 V 0.3 V, PVCC1 = 5.0 V 0.5 V/3.3 V 0.3 V, PVCC2 = 5.0 V 0.5 V, AVCC = 5.0 V 0.5 V, AVref = 4.5 V to AVCC, VSS = PLLVSS = AVSS = 0 V, Ta = -40C to 125C. When PVCC1 = 3.3 V 0.3 V, VCC = PVCC1. When writing or erasing on-chip flash memory, Ta = -40C to 85C. 26.3.10 A/D Converter Timing Table 26.15 A/D Converter Timing 26.3.11 H-UDI Timing Table 26.16 H-UDI Timing 26.3.12 AUD Timing Table 26.17 AUD Timing Rev.2.0, 07/03, page xx of xxxviii Item 26.3.13 UBC Trigger Timing Table 26.18 UBC Trigger Timing Page Revisions (See Manual for Details) 903 Conditions amended Conditions: VCC = PLLVCC = 3.3 V 0.3 V, PVCC1 = 5.0 V 0.5 V/3.3 V 0.3 V, PVCC2 = 5.0 V 0.5 V, AVCC = 5.0 V 0.5 V, AVref = 4.5 V to AVCC, VSS = PLLVSS = AVSS = 0 V, Ta = -40C to 125C. When PVCC1 = 3.3 V 0.3 V, VCC = PVCC1. When writing or erasing on-chip flash memory, Ta = -40C to 85C. 905 Conditions and table amended Conditions: VCC = PLLVCC = 3.3 V 0.3 V, PVCC1 = 5.0 V 0.5 V/3.3 V 0.3 V, PVCC2 = 5.0 V 0.5 V, AVCC = 5.0 V 0.5 V, AVref = 4.5 V to AVCC, VSS = PLLVSS = AVSS = 0 V, Ta = -40C to 125C. When PVCC1 = 3.3 V 0.3 V, VCC = PVCC1. When writing or erasing on-chip flash memory, Ta = -40C to 85C. CSK = 0: fop = 10-20 MHz Item Resolution A/D conversion time Analog input capacitance Permitted analog signal source impedance Non-linear error Min 10 -- -- -- -- Typ 10 -- -- -- -- Max 10 13.3 20 3 1.5* 2.5* Offset error -- -- 1.5* 2.5* Full-scale error -- -- 1.5* 2.5* Quantization error Absolute error Ta 105C Ta >105C -- -- -- -- 0.5 2.0* 2.5* Note: *1 *2 1 1 26.4 A/D Converter Characteristics Table 26.19 A/D Converter Characteristics CSK = 1: fop = 10 MHz Min 10 -- -- -- -- Typ 10 -- -- -- -- Max 10 13.4 20 3 1.5* 2.5* -- -- 1.5* 2.5* -- -- 1.5* 2.5* -- -- -- -- 0.5 2.0* 2.5* 1 1 Unit bit s pF k LSB 2 1 2 1 2 1 2 1 LSB LSB 2 2 LSB LSB 2 2 Rev.2.0, 07/03, page xxi of xxxviii Item 26.5 Flash Memory Characteristics Table 26.20 Flash Memory Characteristics Page Revisions (See Manual for Details) 906 Conditions and table amended Conditions: VCC = PLLVCC = 3.3 V 0.3 V, PVCC1 = 5.0 V 0.5 V/3.3 V 0.3 V, PVCC2 = 5.0 V 0.5 V, AVCC = 5.0 V 0.5 V, AVref = 4.5 V to AVCC, VSS = PLLVSS = AVSS = 0 V, Ta = -40C to 105C. When PVCC1 = 3.3 V 0.3 V, VCC = PVCC1. When writing or erasing on-chip flash memory, Ta = -40C to 85C. Item Programming time* * Erase time* * Note: 13 12 Symbol t P-- t E-- NWEC Min 20 1 -- Typ 200 10 -- Max ms/128 bytes s/block 100 Unit Reprogramming count Times *1 Use the on-chip programming/erasing routine for programming/erasure. *2 When all 0 are programmed. *3 64 kbytes of block 26.6.1 Notes on Connecting External Capacitor for Current Stabilization Figure 26.29 Connection of VCL Capacitor 907 26.6.1 Title added Description added ...power supply (VCL pin) and the Vss pin, an capacitor (0.33 to 0.47 F) for stabilizing the internal voltage.... Figure amended One 0.33 to 0.47 F capacitor VCL One 0.33 to 0.47 F capacitor VSS VCL VSS VCL One 0.33 to 0.47 F capacitor VSS Do not apply any power supply voltage to the VCL pin. Use multilayer ceramics capacitors (one 0.33 to 0.47 F capacitor for each VCL pin), which should be located near the pin. 26.6.2 Notes on Mode Pin Input 907 to Newly added 908 A.2 Register States in Reset and 953 to Table amended Power-Down States 954 Serial SMR0 to SMR4 Table A.2 Register States in Reset and Power-Down States communication interface (SCI) BRR0 to BRR4 SCR0 to SCR4 TDR0 to TDR4 SSR0 to SSR4 RDR0 to RDR4 SDCR0 to SDCR4 Held Intialized Initialized Initialized Held Held I/O ports PADR, PBDR, PCDR PDDR, PEDR, PFDR PGDE, PHDR, PJDR PKDR, PLDR PAPR, PBPR, PDPR, PJPR, PLPR Initialized Initialized Held Held Pin value Held Held Pin value Rev.2.0, 07/03, page xxii of xxxviii Contents Section 1 Overview............................................................................................1 1.1 1.2 1.3 Features ............................................................................................................................. 1 Block Diagram .................................................................................................................. 7 Pin Description.................................................................................................................. 8 1.3.1 Pin Arrangement .................................................................................................. 8 1.3.2 Pin Functions ....................................................................................................... 9 1.3.3 Pin Assignments................................................................................................... 17 Section 2 CPU....................................................................................................27 2.1 Register Configuration...................................................................................................... 27 2.1.1 General Registers (Rn)......................................................................................... 27 2.1.2 Control Registers ................................................................................................. 28 2.1.3 System Registers.................................................................................................. 29 2.1.4 Floating-Point Registers....................................................................................... 30 2.1.5 Floating-Point System Registers .......................................................................... 31 2.1.6 Initial Values of Registers.................................................................................... 31 Data Formats..................................................................................................................... 32 2.2.1 Data Format in Registers...................................................................................... 32 2.2.2 Data Formats in Memory ..................................................................................... 32 2.2.3 Immediate Data Format ....................................................................................... 32 Instruction Features........................................................................................................... 33 2.3.1 RISC-Type Instruction Set................................................................................... 33 2.3.2 Addressing Modes ............................................................................................... 36 2.3.3 Instruction Format................................................................................................ 40 Instruction Set by Classification ....................................................................................... 42 2.4.1 Instruction Set by Classification .......................................................................... 42 Processing States............................................................................................................... 57 2.5.1 State Transitions................................................................................................... 57 2.2 2.3 2.4 2.5 Section 3 Floating-Point Unit (FPU) .................................................................61 3.1 3.2 Overview........................................................................................................................... 61 Floating-Point Registers and Floating-Point System Registers......................................... 62 3.2.1 Floating-Point Register File ................................................................................. 62 3.2.2 Floating-Point Communication Register (FPUL) ................................................ 62 3.2.3 Floating-Point Status/Control Register (FPSCR)................................................. 62 Floating-Point Format ....................................................................................................... 65 3.3.1 Floating-Point Format.......................................................................................... 65 3.3.2 Non-Numbers (NaN) ........................................................................................... 66 3.3.3 Denormalized Number Values............................................................................. 66 Rev.2.0, 07/03, page xxiii of xxxviii 3.3 3.4 3.5 3.6 3.3.4 Other Special Values............................................................................................ 67 Floating-Point Exception Model....................................................................................... 68 3.4.1 Enable State Exceptions....................................................................................... 68 3.4.2 Disable State Exceptions...................................................................................... 68 3.4.3 FPU Exception Event and Code .......................................................................... 68 3.4.4 Floating-Point Data Arrangement in Memory ..................................................... 68 3.4.5 Arithmetic Operations Involving Special Operands ............................................ 68 Synchronization with CPU................................................................................................ 69 Usage Notes ...................................................................................................................... 69 Section 4 Operating Modes ...............................................................................71 4.1 Operating Mode Selection ................................................................................................ 71 Section 5 Clock Pulse Generator (CPG)............................................................73 5.1 Overview........................................................................................................................... 73 5.1.1 Block Diagram ..................................................................................................... 73 5.1.2 Pin Configuration................................................................................................. 74 Frequency Ranges............................................................................................................. 74 Clock Source..................................................................................................................... 75 5.3.1 Connecting a Crystal Oscillator ........................................................................... 75 5.3.2 External Clock Input Method............................................................................... 76 Usage Notes ...................................................................................................................... 77 5.2 5.3 5.4 Section 6 Exception Processing.........................................................................79 6.1 Overview........................................................................................................................... 79 6.1.1 Types of Exception Processing and Priority ........................................................ 79 6.1.2 Exception Processing Operations......................................................................... 80 6.1.3 Exception Processing Vector Table ..................................................................... 81 Resets ................................................................................................................................ 84 6.2.1 Types of Reset ..................................................................................................... 84 6.2.2 Power-On Reset ................................................................................................... 84 6.2.3 Manual Reset ....................................................................................................... 85 Address Errors .................................................................................................................. 86 6.3.1 Address Error Sources ......................................................................................... 86 6.3.2 Address Error Exception Processing.................................................................... 87 Interrupts........................................................................................................................... 87 6.4.1 Interrupt Sources.................................................................................................. 87 6.4.2 Interrupt Priority Level ........................................................................................ 88 6.4.3 Interrupt Exception Processing ............................................................................ 88 Exceptions Triggered by Instructions ............................................................................... 89 6.5.1 Types of Exceptions Triggered by Instructions ................................................... 89 6.5.2 Trap Instructions .................................................................................................. 89 6.5.3 Illegal Slot Instructions ........................................................................................ 90 6.2 6.3 6.4 6.5 Rev.2.0, 07/03, page xxiv of xxxviii 6.6 6.7 6.8 6.5.4 General Illegal Instructions.................................................................................. 90 6.5.5 Floating-Point Instructions................................................................................... 90 When Exception Sources Are Not Accepted .................................................................... 91 Stack Status after Exception Processing Ends .................................................................. 92 Usage Notes ...................................................................................................................... 93 6.8.1 Value of Stack Pointer (SP) ................................................................................. 93 6.8.2 Value of Vector Base Register (VBR) ................................................................. 93 6.8.3 Address Errors Caused by Stacking of Address Error Exception Processing...... 93 6.8.4 Interrupt Processing Timing Gap Caused in SCO Processing ............................. 93 Section 7 Interrupt Controller (INTC) ...............................................................95 7.1 Overview........................................................................................................................... 95 7.1.1 Features................................................................................................................ 95 7.1.2 Block Diagram ..................................................................................................... 96 7.1.3 Pin Configuration................................................................................................. 97 7.1.4 Register Configuration......................................................................................... 97 Interrupt Sources............................................................................................................... 98 7.2.1 NMI Interrupts ..................................................................................................... 98 7.2.2 User Break Interrupt ............................................................................................ 98 7.2.3 H-UDI Interrupt ................................................................................................... 98 7.2.4 IRQ Interrupts ...................................................................................................... 98 7.2.5 On-Chip Peripheral Module Interrupts ................................................................ 99 7.2.6 Interrupt Exception Vectors and Priority Rankings ............................................. 100 Description of Registers.................................................................................................... 109 7.3.1 Interrupt Priority Registers A-L (IPRA-IPRL) ................................................... 109 7.3.2 Interrupt Control Register (ICR).......................................................................... 110 7.3.3 IRQ Status Register (ISR).................................................................................... 111 Interrupt Operation............................................................................................................ 113 7.4.1 Interrupt Sequence ............................................................................................... 113 7.4.2 Stack after Interrupt Exception Processing .......................................................... 115 Interrupt Response Time................................................................................................... 116 Data Transfer with Interrupt Request Signals ................................................................... 118 7.6.1 Handling CPU Interrupt Sources, but Not DMAC Activating Sources ............... 118 7.6.2 Handling DMAC Activating Sources but Not CPU Interrupt Sources ................ 118 7.2 7.3 7.4 7.5 7.6 Section 8 User Break Controller (UBC) ............................................................119 8.1 Overview........................................................................................................................... 119 8.1.1 Features................................................................................................................ 119 8.1.2 Block Diagram ..................................................................................................... 120 8.1.3 Register Configuration......................................................................................... 121 Register Descriptions ........................................................................................................ 121 8.2.1 User Break Address Register (UBAR)................................................................. 121 8.2.2 User Break Address Mask Register (UBAMR) ................................................... 122 Rev.2.0, 07/03, page xxv of xxxviii 8.2 8.3 8.4 8.5 8.2.3 User Break Bus Cycle Register (UBBR) ............................................................. 124 8.2.4 User Break Control Register (UBCR).................................................................. 126 Operation .......................................................................................................................... 127 8.3.1 Flow of the User Break Operation ....................................................................... 127 8.3.2 Break on On-Chip Memory Instruction Fetch Cycle........................................... 129 8.3.3 Program Counter (PC) Values Saved................................................................... 129 Examples of Use ............................................................................................................... 129 8.4.1 Break on CPU Instruction Fetch Cycle................................................................ 129 8.4.2 Break on CPU Data Access Cycle ....................................................................... 130 8.4.3 Break on DMA Cycle .......................................................................................... 131 Usage Notes ...................................................................................................................... 131 8.5.1 Simultaneous Fetching of Two Instructions ........................................................ 131 8.5.2 Instruction Fetches at Branches ........................................................................... 131 8.5.3 Contention between User Break and Exception Processing ................................ 132 8.5.4 Break at Non-Delay Branch Instruction Jump Destination.................................. 132 8.5.5 User Break Trigger Output .................................................................................. 133 8.5.6 Module Standby................................................................................................... 133 Section 9 Bus State Controller (BSC) ...............................................................135 9.1 Overview........................................................................................................................... 135 9.1.1 Features................................................................................................................ 135 9.1.2 Block Diagram ..................................................................................................... 136 9.1.3 Pin Configuration................................................................................................. 137 9.1.4 Register Configuration......................................................................................... 137 9.1.5 Address Map ........................................................................................................ 138 Description of Registers.................................................................................................... 140 9.2.1 Bus Control Register 1 (BCR1) ........................................................................... 140 9.2.2 Bus Control Register 2 (BCR2) ........................................................................... 141 9.2.3 Wait Control Register (WCR).............................................................................. 145 9.2.4 RAM Emulation Register (RAMER)................................................................... 146 Accessing External Space ................................................................................................. 148 9.3.1 Basic Timing........................................................................................................ 148 9.3.2 Wait State Control................................................................................................ 149 9.3.3 CS Assert Period Extension ................................................................................. 151 Waits between Access Cycles ........................................................................................... 152 9.4.1 Prevention of Data Bus Conflicts......................................................................... 152 9.4.2 Simplification of Bus Cycle Start Detection ........................................................ 153 Bus Arbitration.................................................................................................................. 154 Memory Connection Examples......................................................................................... 155 9.2 9.3 9.4 9.5 9.6 Section 10 Direct Memory Access Controller (DMAC) ...................................157 10.1 Overview........................................................................................................................... 157 10.1.1 Features................................................................................................................ 157 Rev.2.0, 07/03, page xxvi of xxxviii 10.2 10.3 10.4 10.5 10.1.2 Block Diagram ..................................................................................................... 158 10.1.3 Register Configuration......................................................................................... 159 Register Descriptions ........................................................................................................ 160 10.2.1 DMA Source Address Registers 0-3 (SAR0-SAR3) .......................................... 160 10.2.2 DMA Destination Address Registers 0-3 (DAR0-DAR3).................................. 161 10.2.3 DMA Transfer Count Registers 0-3 (DMATCR0-DMATCR3)......................... 161 10.2.4 DMA Channel Control Registers 0-3 (CHCR0-CHCR3)................................... 162 10.2.5 DMAC Operation Register (DMAOR) ................................................................ 167 Operation .......................................................................................................................... 169 10.3.1 DMA Transfer Flow ............................................................................................ 169 10.3.2 DMA Transfer Requests ...................................................................................... 171 10.3.3 Channel Priority ................................................................................................... 174 10.3.4 DMA Transfer Types........................................................................................... 174 10.3.5 Dual Address Mode ............................................................................................. 174 10.3.6 Bus Modes ........................................................................................................... 180 10.3.7 Relationship between Request Modes and Bus Modes by DMA Transfer Category............................................................................................................... 181 10.3.8 Bus Mode and Channel Priorities ........................................................................ 182 10.3.9 Source Address Reload Function......................................................................... 182 10.3.10 DMA Transfer Ending Conditions....................................................................... 183 10.3.11 DMAC Access from CPU.................................................................................... 184 Examples of Use ............................................................................................................... 185 10.4.1 Example of DMA Transfer between On-Chip SCI and External Memory.......... 185 10.4.2 Example of DMA Transfer between A/D Converter and On-Chip Memory (Address Reload On)............................................................................................ 185 10.4.3 Example of DMA Transfer between External Memory and SCI1 Transmitting Side (Indirect Address on) ................................................................................... 187 Usage Notes ...................................................................................................................... 189 Section 11 Advanced Timer Unit-II (ATU-II)...................................................191 11.1 Overview........................................................................................................................... 191 11.1.1 Features................................................................................................................ 191 11.1.2 Pin Configuration................................................................................................. 197 11.1.3 Register Configuration......................................................................................... 201 11.1.4 Block Diagrams ................................................................................................... 211 11.1.5 Inter-Channel and Inter-Module Signal Communication Diagram...................... 221 11.1.6 Prescaler Diagram................................................................................................ 222 11.2 Register Descriptions ........................................................................................................ 223 11.2.1 Timer Start Registers (TSTR) .............................................................................. 223 11.2.2 Prescaler Registers (PSCR).................................................................................. 227 11.2.3 Timer Control Registers (TCR) ........................................................................... 228 11.2.4 Timer I/O Control Registers (TIOR).................................................................... 238 11.2.5 Timer Status Registers (TSR) .............................................................................. 249 Rev.2.0, 07/03, page xxvii of xxxviii 11.2.6 Timer Interrupt Enable Registers (TIER) ............................................................ 278 11.2.7 Interval Interrupt Request Registers (ITVRR) ..................................................... 300 11.2.8 Trigger Mode Register (TRGMDR) .................................................................... 305 11.2.9 Timer Mode Register (TMDR) ............................................................................ 305 11.2.10 PWM Mode Register (PMDR)............................................................................. 307 11.2.11 Down-Count Start Register (DSTR) .................................................................... 309 11.2.12 Timer Connection Register (TCNR).................................................................... 315 11.2.13 One-Shot Pulse Terminate Register (OTR) ......................................................... 320 11.2.14 Reload Enable Register (RLDENR) .................................................................... 324 11.2.15 Free-Running Counters (TCNT).......................................................................... 325 11.2.16 Down-Counters (DCNT) ..................................................................................... 327 11.2.17 Event Counters (ECNT)...................................................................................... 329 11.2.18 Output Compare Registers (OCR) ....................................................................... 329 11.2.19 Input Capture Registers (ICR) ............................................................................. 330 11.2.20 General Registers (GR)........................................................................................ 331 11.2.21 Offset Base Registers (OSBR) ............................................................................. 334 11.2.22 Cycle Registers (CYLR) ...................................................................................... 334 11.2.23 Buffer Registers (BFR) ........................................................................................ 335 11.2.24 Duty Registers (DTR) .......................................................................................... 336 11.2.25 Reload Register (RLDR)...................................................................................... 337 11.2.26 Channel 10 Registers ........................................................................................... 337 11.3 Operation .......................................................................................................................... 352 11.3.1 Overview.............................................................................................................. 352 11.3.2 Free-Running Counter Operation and Cyclic Counter Operation........................ 359 11.3.3 Compare-Match Function .................................................................................... 360 11.3.4 Input Capture Function ........................................................................................ 361 11.3.5 One-Shot Pulse Function ..................................................................................... 362 11.3.6 Offset One-Shot Pulse Function and Output Cutoff Function ............................. 363 11.3.7 Interval Timer Operation ..................................................................................... 364 11.3.8 Twin-Capture Function........................................................................................ 365 11.3.9 PWM Timer Function .......................................................................................... 366 11.3.10 Channel 3 to 5 PWM Function ............................................................................ 368 11.3.11 Event Count Function and Event Cycle Measurement ........................................ 369 11.3.12 Channel 10 Functions .......................................................................................... 371 11.4 Interrupts........................................................................................................................... 379 11.4.1 Status Flag Setting Timing................................................................................... 379 11.4.2 Status Flag Clearing ............................................................................................. 384 11.5 CPU Interface.................................................................................................................... 386 11.5.1 Registers Requiring 32-Bit Access ...................................................................... 386 11.5.2 Registers Permitting 8-Bit, 16-Bit, or 32-Bit Access........................................... 388 11.5.3 Registers Requiring 16-Bit Access ...................................................................... 389 11.5.4 8-Bit or 16-Bit Accessible Registers.................................................................... 390 11.5.5 Registers Requiring 8-Bit Access ........................................................................ 391 Rev.2.0, 07/03, page xxviii of xxxviii 11.6 Sample Setup Procedures.................................................................................................. 391 11.7 Usage Notes ...................................................................................................................... 406 11.8 ATU-II Registers and Pins ................................................................................................ 419 Section 12 Advanced Pulse Controller (APC)...................................................421 12.1 Overview........................................................................................................................... 421 12.1.1 Features................................................................................................................ 421 12.1.2 Block Diagram ..................................................................................................... 422 12.1.3 Pin Configuration................................................................................................. 423 12.1.4 Register Configuration......................................................................................... 423 12.2 Register Descriptions ........................................................................................................ 424 12.2.1 Pulse Output Port Control Register (POPCR)...................................................... 424 12.3 Operation .......................................................................................................................... 425 12.3.1 Overview.............................................................................................................. 425 12.3.2 Advanced Pulse Controller Output Operation ..................................................... 426 12.4 Usage Notes ...................................................................................................................... 429 Section 13 Watchdog Timer (WDT)..................................................................431 13.1 Overview........................................................................................................................... 431 13.1.1 Features................................................................................................................ 431 13.1.2 Block Diagram ..................................................................................................... 432 13.1.3 Pin Configuration................................................................................................. 432 13.1.4 Register Configuration......................................................................................... 433 13.2 Register Descriptions ........................................................................................................ 433 13.2.1 Timer Counter (TCNT)........................................................................................ 433 13.2.2 Timer Control/Status Register (TCSR) ................................................................ 434 13.2.3 Reset Control/Status Register (RSTCSR) ............................................................ 436 13.2.4 Register Access.................................................................................................... 437 13.3 Operation .......................................................................................................................... 438 13.3.1 Watchdog Timer Mode ........................................................................................ 438 13.3.2 Interval Timer Mode............................................................................................ 440 13.3.3 Timing of Setting the Overflow Flag (OVF) ....................................................... 440 13.3.4 Timing of Setting the Watchdog Timer Overflow Flag (WOVF)........................ 441 13.4 Usage Notes ...................................................................................................................... 442 13.4.1 TCNT Write and Increment Contention .............................................................. 442 13.4.2 Changing CKS2 to CKS0 Bit Values................................................................... 442 13.4.3 Changing between Watchdog Timer/Interval Timer Modes................................ 442 13.4.4 System Reset by WDTOVF Signal...................................................................... 443 13.4.5 Internal Reset in Watchdog Timer Mode............................................................. 443 13.4.6 Manual Reset in Watchdog Timer ....................................................................... 443 Section 14 Compare Match Timer (CMT).........................................................445 14.1 Overview........................................................................................................................... 445 Rev.2.0, 07/03, page xxix of xxxviii 14.2 14.3 14.4 14.5 14.1.1 Features................................................................................................................ 445 14.1.2 Block Diagram ..................................................................................................... 446 14.1.3 Register Configuration......................................................................................... 447 Register Descriptions ........................................................................................................ 448 14.2.1 Compare Match Timer Start Register (CMSTR) ................................................. 448 14.2.2 Compare Match Timer Control/Status Register (CMCSR).................................. 449 14.2.3 Compare Match Timer Counter (CMCNT) ......................................................... 450 14.2.4 Compare Match Timer Constant Register (CMCOR).......................................... 451 Operation .......................................................................................................................... 451 14.3.1 Cyclic Count Operation ....................................................................................... 451 14.3.2 CMCNT Count Timing........................................................................................ 452 Interrupts........................................................................................................................... 452 14.4.1 Interrupt Sources and DTC Activation ................................................................ 452 14.4.2 Compare Match Flag Set Timing......................................................................... 452 14.4.3 Compare Match Flag Clear Timing ..................................................................... 453 Usage Notes ...................................................................................................................... 454 14.5.1 Contention between CMCNT Write and Compare Match................................... 454 14.5.2 Contention between CMCNT Word Write and Incrementation .......................... 455 14.5.3 Contention between CMCNT Byte Write and Incrementation ............................ 456 Section 15 Serial Communication Interface (SCI) ............................................457 15.1 Overview........................................................................................................................... 457 15.1.1 Features................................................................................................................ 457 15.1.2 Block Diagram ..................................................................................................... 458 15.1.3 Pin Configuration................................................................................................. 459 15.1.4 Register Configuration......................................................................................... 460 15.2 Register Descriptions ........................................................................................................ 461 15.2.1 Receive Shift Register (RSR)............................................................................... 461 15.2.2 Receive Data Register (RDR) .............................................................................. 462 15.2.3 Transmit Shift Register (TSR) ............................................................................. 462 15.2.4 Transmit Data Register (TDR)............................................................................ 463 15.2.5 Serial Mode Register (SMR)................................................................................ 463 15.2.6 Serial Control Register (SCR).............................................................................. 466 15.2.7 Serial Status Register (SSR)................................................................................. 470 15.2.8 Bit Rate Register (BRR)....................................................................................... 474 15.2.9 Serial Direction Control Register (SDCR)........................................................... 481 15.2.10 Inversion of SCK Pin Signal................................................................................ 482 15.3 Operation .......................................................................................................................... 482 15.3.1 Overview.............................................................................................................. 482 15.3.2 Operation in Asynchronous Mode ....................................................................... 484 15.3.3 Multiprocessor Communication........................................................................... 494 15.3.4 Synchronous Operation........................................................................................ 502 15.4 SCI Interrupt Sources and the DMAC .............................................................................. 513 Rev.2.0, 07/03, page xxx of xxxviii 15.5 Usage Notes ...................................................................................................................... 514 15.5.1 TDR Write and TDRE Flag ................................................................................. 514 15.5.2 Simultaneous Multiple Receive Errors ................................................................ 514 15.5.3 Break Detection and Processing .......................................................................... 515 15.5.4 Sending a Break Signal........................................................................................ 515 15.5.5 Receive Error Flags and Transmitter Operation (Synchronous Mode Only)....... 515 15.5.6 Receive Data Sampling Timing and Receive Margin in Asynchronous Mode ... 515 15.5.7 Constraints on DMAC Use .................................................................................. 516 15.5.8 Cautions on Synchronous External Clock Mode ................................................. 517 15.5.9 Caution on Synchronous Internal Clock Mode.................................................... 517 Section 16 Controller Area Network (HCAN) ..................................................519 16.1 Overview........................................................................................................................... 519 16.1.1 Features................................................................................................................ 519 16.1.2 Block Diagram ..................................................................................................... 521 16.1.3 Pin Configuration................................................................................................. 522 16.1.4 Register Configuration......................................................................................... 523 16.2 Register Descriptions ........................................................................................................ 527 16.2.1 Master Control Register (MCR)........................................................................... 527 16.2.2 General Status Register (GSR)............................................................................. 528 16.2.3 Bit Configuration Register (BCR) ....................................................................... 529 16.2.4 Mailbox Configuration Register (MBCR) ........................................................... 533 16.2.5 Transmit Wait Register (TXPR) .......................................................................... 533 16.2.6 Transmit Wait Cancel Register (TXCR) .............................................................. 534 16.2.7 Transmit Acknowledge Register (TXACK) ........................................................ 535 16.2.8 Abort Acknowledge Register (ABACK) ............................................................. 536 16.2.9 Receive Complete Register (RXPR) .................................................................... 537 16.2.10 Remote Request Register (RFPR)........................................................................ 538 16.2.11 Interrupt Register (IRR) ....................................................................................... 538 16.2.12 Mailbox Interrupt Mask Register (MBIMR)........................................................ 542 16.2.13 Interrupt Mask Register (IMR) ............................................................................ 543 16.2.14 Receive Error Counter (REC) .............................................................................. 545 16.2.15 Transmit Error Counter (TEC)............................................................................. 546 16.2.16 Unread Message Status Register (UMSR) ........................................................... 546 16.2.17 Local Acceptance Filter Masks (LAFML, LAFMH)........................................... 547 16.2.18 Message Control (MC0 to MC15) ....................................................................... 549 16.2.19 Message Data (MD0 to MD15) ........................................................................... 552 16.3 Operation .......................................................................................................................... 554 16.3.1 Hardware Reset and Software Reset .................................................................... 554 16.3.2 Initialization after a Hardware Reset.................................................................... 557 16.3.3 Transmit Mode..................................................................................................... 561 16.3.4 Receive Mode ...................................................................................................... 567 16.3.5 HCAN Sleep Mode .............................................................................................. 573 Rev.2.0, 07/03, page xxxi of xxxviii 16.3.6 HCAN Halt Mode ................................................................................................ 575 16.3.7 Interrupt Interface ................................................................................................ 575 16.3.8 DMAC Interface .................................................................................................. 576 16.4 CAN Bus Interface............................................................................................................ 578 16.5 Usage Notes ...................................................................................................................... 579 Section 17 A/D Converter .................................................................................583 17.1 Overview........................................................................................................................... 583 17.1.1 Features................................................................................................................ 583 17.1.2 Block Diagram ..................................................................................................... 584 17.1.3 Pin Configuration................................................................................................. 586 17.1.4 Register Configuration......................................................................................... 589 17.2 Register Descriptions ........................................................................................................ 591 17.2.1 A/D Data Registers 0 to 31 (ADDR0 to ADDR31) ............................................. 591 17.2.2 A/D Control/Status Registers 0 and 1 (ADCSR0, ADCSR1) .............................. 592 17.2.3 A/D Control Registers 0 to 2 (ADCR0 to ADCR2)............................................. 597 17.2.4 A/D Control/Status Register 2 (ADCSR2)........................................................... 599 17.2.5 A/D Trigger Registers 0 to 2 (ADTRGR0 to ADTRGR2) .................................. 602 17.3 CPU Interface.................................................................................................................... 603 17.4 Operation .......................................................................................................................... 604 17.4.1 Single Mode......................................................................................................... 604 17.4.2 Scan Mode ........................................................................................................... 606 17.4.3 Analog Input Sampling and A/D Conversion Time............................................. 610 17.4.4 External Triggering of A/D Conversion .............................................................. 612 17.4.5 A/D Converter Activation by ATU-II.................................................................. 613 17.4.6 ADEND Output Pin ............................................................................................. 613 17.5 Interrupt Sources and DMA Transfer Requests ................................................................ 614 17.6 Usage Notes ...................................................................................................................... 614 17.6.1 A/D conversion accuracy definitions................................................................... 616 Section 18 High-Performance User Debug Interface (H-UDI) ........................617 18.1 Overview........................................................................................................................... 617 18.1.1 Features................................................................................................................ 617 18.1.2 Block Diagram ..................................................................................................... 618 18.1.3 Pin Configuration................................................................................................. 619 18.1.4 Register Configuration......................................................................................... 619 18.2 External Signals ................................................................................................................ 620 18.2.1 Test Clock (TCK) ................................................................................................ 620 18.2.2 Test Mode Select (TMS)...................................................................................... 620 18.2.3 Test Data Input (TDI) .......................................................................................... 620 18.2.4 Test Data Output (TDO) ...................................................................................... 620 18.2.5 Test Reset (TRST) ............................................................................................... 620 18.3 Register Descriptions ........................................................................................................ 621 Rev.2.0, 07/03, page xxxii of xxxviii 18.3.1 Instruction Register (SDIR) ................................................................................. 621 18.3.2 Status Register (SDSR) ........................................................................................ 623 18.3.3 Data Register (SDDR) ......................................................................................... 624 18.3.4 Bypass Register (SDBPR).................................................................................... 624 18.4 Operation .......................................................................................................................... 625 18.4.1 H-UDI Interrupt ................................................................................................... 625 18.4.2 Bypass Mode........................................................................................................ 628 18.4.3 H-UDI Reset ........................................................................................................ 628 18.5 Usage Notes ...................................................................................................................... 628 Section 19 Advanced User Debugger (AUD)....................................................631 19.1 Overview........................................................................................................................... 631 19.1.1 Features................................................................................................................ 631 19.1.2 Block Diagram ..................................................................................................... 632 19.2 Pin Configuration.............................................................................................................. 632 19.2.1 Pin Descriptions ................................................................................................... 633 19.3 Branch Trace Mode........................................................................................................... 635 19.3.1 Overview.............................................................................................................. 635 19.3.2 Operation ............................................................................................................. 635 19.4 RAM Monitor Mode ......................................................................................................... 637 19.4.1 Overview.............................................................................................................. 637 19.4.2 Communication Protocol ..................................................................................... 637 19.4.3 Operation ............................................................................................................. 638 19.5 Usage Notes ...................................................................................................................... 639 19.5.1 Initialization ......................................................................................................... 639 19.5.2 Operation in Software Standby Mode.................................................................. 639 19.5.3 Boot Mode Operation and User Boot Mode Initial State..................................... 640 19.5.4 AUD Input Signal in Software Standby/Hardware Standby Mode...................... 640 Section 20 Pin Function Controller (PFC).........................................................641 20.1 Overview........................................................................................................................... 641 20.2 Register Configuration...................................................................................................... 646 20.3 Register Descriptions ........................................................................................................ 647 20.3.1 Port A IO Register (PAIOR) ................................................................................ 647 20.3.2 Port A Control Registers H and L (PACRH, PACRL) ........................................ 648 20.3.3 Port B IO Register (PBIOR) ................................................................................ 652 20.3.4 Port B Control Registers H and L (PBCRH, PBCRL) ......................................... 653 20.3.5 Port B Invert Register (PBIR) .............................................................................. 658 20.3.6 Port C IO Register (PCIOR) ................................................................................ 659 20.3.7 Port C Control Register (PCCR) .......................................................................... 659 20.3.8 Port D IO Register (PDIOR) ................................................................................ 661 20.3.9 Port D Control Registers H and L (PDCRH, PDCRL) ........................................ 661 20.3.10 Port E IO Register (PEIOR)................................................................................. 665 Rev.2.0, 07/03, page xxxiii of xxxviii 20.3.11 Port E Control Register (PECR) .......................................................................... 666 20.3.12 Port F IO Register (PFIOR) ................................................................................. 671 20.3.13 Port F Control Registers H and L (PFCRH, PFCRL) .......................................... 672 20.3.14 Port G IO Register (PGIOR) ................................................................................ 677 20.3.15 Port G Control Register (PGCR).......................................................................... 678 20.3.16 Port H IO Register (PHIOR) ................................................................................ 679 20.3.17 Port H Control Register (PHCR).......................................................................... 680 20.3.18 Port J IO Register (PJIOR)................................................................................... 686 20.3.19 Port J Control Registers H and L (PJCRH, PJCRL) ............................................ 687 20.3.20 Port K IO Register (PKIOR) ................................................................................ 691 20.3.21 Port K Control Registers H and L (PKCRH, PKCRL) ........................................ 691 20.3.22 Port K Invert Register (PKIR) ............................................................................. 696 20.3.23 Port L IO Register (PLIOR)................................................................................. 697 20.3.24 Port L Control Registers H and L (PLCRH, PLCRL).......................................... 698 20.3.25 Port L Invert Register (PLIR) .............................................................................. 703 Section 21 I/O Ports (I/O)..................................................................................705 21.1 Overview........................................................................................................................... 705 21.2 Port A................................................................................................................................ 705 21.2.1 Register Configuration......................................................................................... 706 21.2.2 Port A Data Register (PADR) .............................................................................. 706 21.2.3 Port A Port Register (PAPR) ............................................................................... 707 21.3 Port B ................................................................................................................................ 708 21.3.1 Register Configuration......................................................................................... 708 21.3.2 Port B Data Register (PBDR) .............................................................................. 709 21.3.3 Port B Port Register (PBPR) ................................................................................ 710 21.4 Port C ................................................................................................................................ 710 21.4.1 Register Configuration......................................................................................... 710 21.4.2 Port C Data Register (PCDR) .............................................................................. 711 21.5 Port D................................................................................................................................ 712 21.5.1 Register Configuration......................................................................................... 712 21.5.2 Port D Data Register (PDDR) .............................................................................. 713 21.5.3 Port D Port Register (PDPR) ............................................................................... 714 21.6 Port E ................................................................................................................................ 715 21.6.1 Register Configuration......................................................................................... 715 21.6.2 Port E Data Register (PEDR)............................................................................... 716 21.7 Port F................................................................................................................................. 718 21.7.1 Register Configuration......................................................................................... 718 21.7.2 Port F Data Register (PFDR) ............................................................................... 719 21.8 Port G................................................................................................................................ 720 21.8.1 Register Configuration......................................................................................... 721 21.8.2 Port G Data Register (PGDR) .............................................................................. 721 21.9 Port H................................................................................................................................ 723 Rev.2.0, 07/03, page xxxiv of xxxviii 21.10 21.11 21.12 21.13 21.14 21.9.1 Register Configuration......................................................................................... 724 21.9.2 Port H Data Register (PHDR) .............................................................................. 724 Port J ................................................................................................................................. 725 21.10.1 Register Configuration......................................................................................... 726 21.10.2 Port J Data Register (PJDR)................................................................................. 726 21.10.3 Port J Port Register (PJPR) .................................................................................. 727 Port K................................................................................................................................ 728 21.11.1 Register Configuration......................................................................................... 728 21.11.2 Port K Data Register (PKDR) .............................................................................. 729 Port L ................................................................................................................................ 730 21.12.1 Register Configuration......................................................................................... 730 21.12.2 Port L Data Register (PLDR)............................................................................... 731 21.12.3 Port L Port Register (PLPR) ................................................................................ 732 POD (Port Output Disable) Control.................................................................................. 732 Usage Notes ...................................................................................................................... 733 Section 22 ROM ................................................................................................735 22.1 Features ............................................................................................................................. 735 22.2 Overview........................................................................................................................... 737 22.2.1 Block Diagram ..................................................................................................... 737 22.2.2 Operating Mode ................................................................................................... 738 22.2.3 Mode Comparison................................................................................................ 739 22.2.4 Flash Memory Configuration............................................................................... 741 22.2.5 Block Division ..................................................................................................... 742 22.2.6 Programming/Erasing Interface ........................................................................... 743 22.3 Pin Configuration.............................................................................................................. 745 22.4 Register Configuration...................................................................................................... 746 22.4.1 Registers............................................................................................................... 746 22.4.2 Programming/Erasing Interface Registers ........................................................... 748 22.4.3 Programming/Erasing Interface Parameters ........................................................ 754 22.4.4 RAM Emulation Register (RAMER)................................................................... 766 22.5 On-Board Programming Mode ......................................................................................... 768 22.5.1 Boot Mode ........................................................................................................... 768 22.5.2 User Program Mode............................................................................................. 771 22.5.3 User Boot Mode................................................................................................... 782 22.6 Protection .......................................................................................................................... 785 22.6.1 Hardware Protection ............................................................................................ 785 22.6.2 Software Protection.............................................................................................. 786 22.6.3 Error Protection.................................................................................................... 787 22.7 Flash Memory Emulation in RAM ................................................................................... 789 22.8 Usage Notes ...................................................................................................................... 792 22.8.1 Switching between User MAT and User Boot MAT........................................... 792 22.8.2 Interrupts during Programming/Erasing .............................................................. 793 Rev.2.0, 07/03, page xxxv of xxxviii 22.8.3 Other Notes .......................................................................................................... 797 22.9 Programmer Mode ............................................................................................................ 798 22.9.1 Pin Arrangement of Socket Adapter .................................................................... 799 22.9.2 Programmer Mode Operation .............................................................................. 801 22.9.3 Memory-Read Mode............................................................................................ 802 22.9.4 Auto-Program Mode ............................................................................................ 803 22.9.5 Auto-Erase Mode................................................................................................. 803 22.9.6 Status-Read Mode................................................................................................ 804 22.9.7 Status Polling ....................................................................................................... 804 22.9.8 Time Taken in Transition to Programmer Mode ................................................. 805 22.9.9 Notes on Programming in Programmer Mode..................................................... 805 22.10 Further Information........................................................................................................... 806 22.10.1 Serial Communication Interface Specification for Boot Mode............................ 806 22.10.2 AC Characteristics and Timing in Programmer Mode......................................... 830 22.10.3 Storable Area for Procedure Program and Programming Data............................ 837 Section 23 RAM ................................................................................................845 23.1 Overview........................................................................................................................... 845 23.2 Operation .......................................................................................................................... 846 Section 24 Power-Down State...........................................................................847 24.1 Overview........................................................................................................................... 847 24.1.1 Power-Down States.............................................................................................. 847 24.1.2 Pin Configuration................................................................................................. 849 24.1.3 Related Registers ................................................................................................. 849 24.2 Register Descriptions ........................................................................................................ 850 24.2.1 Standby Control Register (SBYCR) .................................................................... 850 24.2.2 System Control Register (SYSCR) ...................................................................... 851 24.2.3 Module Standby Control Register (MSTCR) ...................................................... 852 24.2.4 Notes on Register Access..................................................................................... 853 24.3 Hardware Standby Mode .................................................................................................. 854 24.3.1 Transition to Hardware Standby Mode................................................................ 854 24.3.2 Canceling Hardware Standby Mode .................................................................... 854 24.3.3 Hardware Standby Mode Timing......................................................................... 854 24.4 Software Standby Mode.................................................................................................... 856 24.4.1 Transition to Software Standby Mode ................................................................. 856 24.4.2 Canceling Software Standby Mode...................................................................... 856 24.4.3 Software Standby Mode Application Example.................................................... 857 24.5 Sleep Mode ....................................................................................................................... 858 24.5.1 Transition to Sleep Mode..................................................................................... 858 24.5.2 Canceling Sleep Mode ......................................................................................... 858 Section 25 Reliability ........................................................................................859 Rev.2.0, 07/03, page xxxvi of xxxviii 25.1 Reliability.......................................................................................................................... 859 Section 26 Electrical Characteristics..................................................................861 26.1 Absolute Maximum Ratings ............................................................................................. 861 26.2 DC Characteristics ............................................................................................................ 863 26.3 AC Characteristics ............................................................................................................ 880 26.3.1 Timing for swicthing the power supply on/off .................................................... 880 26.3.2 Clock Timing ....................................................................................................... 881 26.3.3 Control Signal Timing ......................................................................................... 883 26.3.4 Bus Timing .......................................................................................................... 886 26.3.5 Advanced Timer Unit Timing and Advance Pulse Controller Timing ................ 890 26.3.6 I/O Port Timing.................................................................................................... 892 26.3.7 Watchdog Timer Timing...................................................................................... 893 26.3.8 Serial Communication Interface Timing.............................................................. 894 26.3.9 HCAN Timing ..................................................................................................... 896 26.3.10 A/D Converter Timing......................................................................................... 897 26.3.11 H-UDI Timing ..................................................................................................... 899 26.3.12 AUD Timing ........................................................................................................ 901 26.3.13 UBC Trigger Timing............................................................................................ 903 26.3.14 Measuring Conditions for AC Characteristics ..................................................... 904 26.4 A/D Converter Characteristics .......................................................................................... 905 26.5 Flash Memory Characteristics........................................................................................... 906 26.6 Usage Note........................................................................................................................ 907 26.6.1 Notes on Connecting External Capacitor for Current Stabilization ..................... 907 26.6.2 Notes on Mode Pin Input ..................................................................................... 907 Appendix A On-chip peripheral module Registers............................................909 A.1 A.2 Address ............................................................................................................................. 909 Register States in Reset and Power-Down States.............................................................. 951 Appendix B Pin States .......................................................................................956 Appendix C Product Lineup ..............................................................................959 Appendix D Package Dimensions .....................................................................960 Rev.2.0, 07/03, page xxxvii of xxxviii Rev.2.0, 07/03, page xxxviii of xxxviii Section 1 Overview 1.1 Features The SH7055SF is a single-chip RISC microcontroller that integrates a RISC CPU core using an original Renesas architecture with peripheral functions required for system configuration. The CPU has a RISC-type instruction set. Basic instructions can be executed in one state (one system clock cycle), which greatly improves instruction execution speed. In addition, the 32-bit internal architecture enhances data processing power. With this CPU, it has become possible to assemble low-cost, high-performance/high-functionality systems even for applications such as real-time control, which could not previously be handled by microcontrollers because of their high-speed processing requirements. In addition, the SH7055SF includes on-chip peripheral functions necessary for system configuration, such as a floating-point unit (FPU) , ROM , RAM, a direct memory access controller (DMAC), timers, a serial communication interface (SCI), controller area network (HCAN), A/D converter, interrupt controller (INTC), and I/O ports. ROM and SRAM can be directly connected by means of an external memory access support function, greatly reducing system cost. On-chip ROM is available as flash memory in the F-ZTATTM* (Flexible Zero Turn Around Time) version. The flash memory can be programmed with a programmer that supports SH7055SF programming, and can also be programmed and erased by software. Since the programming/erasing control program is included as firmware, programming and erasing can be performed by calling this program with a user program. This enables the chip to be programmed at the user site while mounted on a board. The features of the SH7055SF are summarized in table 1.1. Note: * F-ZTAT is a trademark of Renesas Technology Corp. Rev.2.0, 07/03, page 1 of 960 Table 1.1 Item CPU SH7055SF Features Features * * * * Maximum operating frequency: 40 MHz Original Hitachi SH-2E CPU 32-bit internal architecture General register machine Sixteen 32-bit general registers Three 32-bit control registers Four 32-bit system registers * * * Instruction execution time: Basic instructions execute in one state (25 ns/instruction at 40 MHz operation) Address space: Architecture supports 4 Gbytes Five-stage pipeline Operating modes Single-chip mode 8/16-bit bus expanded mode * Mode with on-chip ROM * Mode with no on-chip ROM * Processing states Reset state Program execution state Exception handling state Bus-released state * Power-down state Power-down state Sleep mode Software standby mode Hardware standby mode Module standby Operating states * Multiplier * 32 x 32 64 multiply operations executed in two to four cycles 32 x 32 + 64 64 multiply-and-accumulate operations executed in two to four cycles Rev.2.0, 07/03, page 2 of 960 Table 1.1 Item SH7055SF Features (cont) Features * * * * * * * * * * * SuperH architecture coprocessor Supports single-precision floating-point operations Supports a subset of the data types specified by the IEEE standard Supports invalid operation and division-by-zero exception detection (subset of IEEE standard) Supports Round to Zero as the rounding mode (subset of IEEE standard) Sixteen 32-bit floating-point data registers Supports the FMAC instruction (multiply-and-accumulate instruction) Supports the FDIV instruction (divide instruction) Supports the FLDI0/FLDI1 instructions (constant 0/1 load instructions) Instruction delay time: Two cycles for each of FMAC, FADD, FSUB, and FMUL instructions Execution pitch: One cycle for each of FMAC, FADD, FSUB, and FMUL instructions On-chip clock pulse generator (maximum operating frequency: 40 MHz) Independent generation of CPU system clock and peripheral clock for peripheral modules On-chip clock-multiplication PLL circuit (x4) Internal clock frequency range: 5 to 10 MHz Nine external interrupt pins (NMI, IRQ0 to IRQ7) 115 internal interrupt sources (ATU-II x 75, SCI x 20, DMAC x 4, A/D x 3, WDT x 1, UBC x 1, CMT x 2, HCAN x 8, H-UDI x 1) * 16 programmable priority levels Requests an interrupt when the CPU or DMAC generates a bus cycle with specified conditions (interrupt can also be masked) Trigger pulse output (UBCTRG) on break condition Selection of trigger pulse width ( x1, x4, x8, x16) * Simplifies configuration of an on-chip debugger Floating-point unit Clock pulse generator (CPG/PLL) * * * Interrupt controller (INTC) * * User break controller (UBC) * * Rev.2.0, 07/03, page 3 of 960 Table 1.1 Item SH7055SF Features (cont) Features * * * Supports external memory access (SRAM and ROM directly connectable) 8/16-bit bus space 3.3 V bus interface 16 MB address space divided into four areas, with the following parameters settable for each area: * * * Bus size (8 or 16 bits) Chip select signals (CS0 to CS3) output for each area Number of wait cycles Wait cycles can be inserted using an external WAIT signal External access in minimum of two cycles Provision for idle cycle insertion to prevent bus collisions DMA transfer possible for the following devices: * * * External memory, on-chip memory, on-chip peripheral modules (excluding DMAC, UBC, BSC) SCI, A/D converter, ATU-II, HCAN Bus state controller (BSC) Direct memory access controller (DMAC) (4 channels) * DMA transfer requests by on-chip modules Cycle steal or burst mode transfer Dual address mode Direct transfer mode Indirect transfer mode (channel 3 only) * * Advanced timer unit-II (ATU-II) * Address reload function (channel 2 only) Transfer data width: Byte/word/longword Maximum 65 inputs or outputs can be processed Four 32-bit input capture inputs Thirty 16-bit input capture inputs/output compare outputs Sixteen 16-bit one-shot pulse outputs Eight 16-bit PWM outputs * Advanced pulse controller (APC) * Six 8-bit event counters One gap detection function I/O pin output inversion function Maximum eight pulse outputs on reception of ATU-II (channel 11) compare-match signal Rev.2.0, 07/03, page 4 of 960 Table 1.1 Item SH7055SF Features (cont) Features * * * Can be switched between watchdog timer and interval timer function Internal reset, external signal, or interrupt generated by counter overflow Two kinds of internal reset Power-on reset Manual reset Watchdog timer (WDT) (1 channel) Compare-match timer (CMT) (2 channels) Serial communication interface (SCI) (5 channels) * * * * * * * Selection of 4 counter input clocks A compare-match interrupt can be requested independently for each channel Selection of asynchronous or synchronous mode Simultaneous transmission/reception (full-duplex) capability Serial data communication possible between multiple processors (asynchronous mode) Clock inversion function LSB-/MSB-first selection function for transmission CAN version: Bosch 2.0B active compatible Buffer size (per channel): Transmit/receive x 15, receive-only x 1 Receive message filtering capability Thirty-two channels Three sample-and-hold circuits Independent operation of 12 channels x 2 and 8 channels x 1 Selection of two conversion modes Single conversion mode Scan mode * Continuous scan mode * Single-cycle scan mode Controller area network (HCAN) (2 channels) A/D converter * * * * * * * * * HighPerformance user debug interface (H-UDI) * * * Can be activated by external trigger or ATU-II compare-match 10-bit resolution Accuracy: 2 LSB Five dedicated pins Bypass mode (test mode compliant with IEEE1149.1) H-UDI interrupt Rev.2.0, 07/03, page 5 of 960 Table 1.1 Item SH7055SF Features (cont) Features * * Eight dedicated pins RAM monitor mode Data input/output frequency: /4 or less Possible to read/write to a module connected to the internal/external bus * Branch address output mode Dual-function input/output pins: 149 Schmitt input pins: NMI, IRQn, RES, HSTBY, FWE, TCLK, IC, IC/OC, SCK, ADTRG Input port protection 512-kbyte flash memory 512 kbytes divided into 16 blocks Small blocks: Medium block: Large blocks: * * * 4 kB x 8 32 kB x 1 64 kB x 7 Advanced user debugger (AUD) I/O ports (including timer I/O pins, address and data buses) ROM * * * * * RAM emulation function (using 4 KB small block) Programming/erasing control program included as firmware Flash memory programming methods Boot mode User boot mode User program mode Programmer mode RAM * 32 kB SRAM Rev.2.0, 07/03, page 6 of 960 ; ;; ;; ;; 1.2 Block Diagram Port/control signals FWE MD2 MD1 MD0 NMI ROM (flash) 512 kB CK EXTAL XTAL PLLVCC PLLVSS PLLCAP Vcc (x8) PVcc1 (x4) PVcc2 (x6) VCL(x3) Vss (x21) AVref (x2) AVcc (x2) AVss (x2) AN31-0 Clock pulse generator CPU FPU DMAC (4 channels) Multiplier Interrupt controller BSC Port/data signals AUDMD AUDATA3-0 AUDCK TMS SCI (5 channels) HCAN (2 channels) TDI TDO TCK CMT (2 channels) AUD H-UDI PD0/TIO1A PD1/TIO1B PD2/TIO1C PD3/TIO1D PD4/TIO1E PD5/TIO1F PD6/TIO1G PD7/TIO1H PD8/PULS0 PD9/PULS1 PD10/PULS2 PD11/PULS3 PD12/PULS4 PD13/PULS6/HTxD0/HTxD1 PL0/TI10 PL1/TIO11A/ PL2/TIO11B/ PL3/TCLKB PL4/ PL5/ PL6/ADEND PL7/SCK2 PL8/SCK3 PL9/SCK4/ PL10/HTxD0/HTxD1/HTxD0 & HTxD1 PL11/HRxD0/HRxD1/HRxD0 & HRxD1 PL12/ PL13/ Port PK15/TO8P PK14/TO8O PK13/TO8N PK12/TO8M PK11/TO8L PK10/TO8K PK9/TO8J PK8/TO8I PK7/TO8H PK6/TO8G PK5/TO8F PK4/TO8E PK3/TO8D PK2/TO8C PK1/TO8B PK0/TO8A PJ15/TI9F PJ14/TI9E PJ13/TI9D PJ12/TI9C PJ11/TI9B PJ10/TI9A PJ9/TIO5D PJ8/TIO5C PJ7/TIO2H PJ6/TIO2G PJ5/TIO2F PJ4/TIO2E PJ3/TIO2D PJ2/TIO2C PJ1/TIO2B PJ0/TIO2A Port : Peripheral address bus (9 bits) : Peripheral data bus (16 bits) : Internal address bus (32 bits) : Internal upper data bus (16 bits) : Internal lower data bus (16 bits) Figure 1.1 Block Diagram Rev.2.0, 07/03, page 7 of 960 Port PF13/ PF12/ PF11/ PF10/ PF5/A21/ PF4/A20 PF3/A19 PF2/A18 PF1/A17 PF0/A16 PE15/A15 PE14/A14 PE13/A13 PE12/A12 PE11/A11 PE10/A10 PE9/A9 PE8/A8 PE7/A7 PE6/A6 PE5/A5 PE4/A4 PE3/A3 PE2/A2 PE1/A1 PE0/A0 Port/address signals RAM 32 kB PH15/D15 PH14/D14 PH13/D13 PH12/D12 PH11/D11 PH10/D10 PH9/D9 PH8/D8 PH7/D7 PH6/D6 PH5/D5 PH4/D4 PH3/D3 PH2/D2 PH1/D1 PH0/D0 ATU-II A/D converter WDT Port PF15/ PF14/ PF8/ PF9/ PF7/ PF6/ PA0/TI0A PA1/TI0B PA2/TI0C PA3/TI0D PA4/TIO3A PA5/TIO3B PA6/TIO3C PA7/TIO3D PA8/TIO4A PA9/TIO4B PA10/TIO4C PA11/TIO4D PA12/TIO5A PA13/TIO5B PA14/TxD0 PA15/RxD0 PB0/TO6A PB1/TO6B PB2/TO6C PB3/TO6D PB4/TO7A/TO8A PB5/TO7B/TO8B PB6/TO7C/TO8C PB7/TO7D/TO8D PB8/TxD3/TO8E PB9/RxD3/TO8F PB10/TxD4/HTxD0/TO8G PB11/RxD4/HRxD0/TO8H PB12/TCLKA/ PB13/SCK0 PB14/SCK1/TCLKB/TI10 PB15/PULS5/SCK2 PC0/TxD1 PC1/RxD1 PC2/TxD2 PC3/RxD2 PC4/ PG0/PULS7/HRxD0/HRxD1 PG1/ PG2/ /ADEND PG3/ / 1.3 1.3.1 TDI TDO TCK Vcc Vss AUDMD AUDATA0 AUDATA1 AUDATA2 AUDATA3 AUDCK Vss PK8/TO8I PK9/TO8J PK10/TO8K PK11/TO8L PK12/TO8M PK13/TO8N PVcc2 PK14/TO8O Vss PK15/TO8P PL0/TI10 PL1/TIO11A/ PL2/TIO11B/ PL3/TCLKB PL4/ PL5/ PL6/ADEND PL7/SCK2 PL8/SCK3 VCL PL9/SCK4/ Vss PL10/HTxD0/HTxD1/HTxD0 & HTxD1 PL11/HRxD0/HRxD1/HRxD0 & HRxD1 PL12/ PL13/ TMS Pin Arrangement PVcc2 PD0/TIO1A Vss PD1/TIO1B PD2/TIO1C PD3/TIO1D PD4/TIO1E PD5/TIO1F PD6/TIO1G PD7/TIO1H 205 206 207 208 209 210 211 212 213 214 215 216 217 218 219 220 221 222 223 224 225 226 227 228 229 230 231 232 233 234 235 236 237 238 239 240 241 242 243 244 245 246 247 248 249 250 251 252 253 254 255 256 Rev.2.0, 07/03, page 8 of 960 INDEX FP-256H (Top view) Pin Description Figure 1.2 Pin Arrangement MD0 PLLVcc PLLCAP PLLVss PH0/D0 PH1/D1 PH2/D2 PH3/D3 PH4/D4 PH5/D5 PH6/D6 PVcc1 PH7/D7 Vss PH8/D8 PH9/D9 Vcc PH10/D10 PD8/PULS0 PD9/PULS1 PD10/PULS2 PD11/PULS3 PD12/PULS4 PD13//PULS6/HTxD0/HTxD1 PE0/A0 PE1/A1 PE2/A2 PE3/A3 Vcc PE4/A4 Vss PE5/A5 PE6/A6 PE7/A7 PE8/A8 PE9/A9 PE10/A10 PVcc1 PE11/A11 Vss PE12/A12 PE13/A13 PE14/A14 PE15/A15 PF0/A16 PF1/A17 PF2/A18 VCL PF3/A19 Vss PF4/A20 PF5/A21/ PF6/ PF7/ PF8/ PF9/ PVcc1 PF10/ Vss PF11/ PF12/ PF13/ PF14/ PF15/ Vss CK Vcc MD2 EXTAL Vcc XTAL Vss MD1 FWE 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 204 203 202 201 200 199 198 197 196 195 194 193 192 191 190 189 188 187 186 185 184 183 182 181 180 179 178 177 176 175 174 173 172 171 170 169 168 167 166 165 164 163 162 161 160 159 158 157 156 155 154 153 152 151 150 149 148 147 146 145 144 143 142 141 140 139 138 137 136 135 134 133 132 131 130 129 128 127 126 125 124 123 122 121 120 119 118 117 116 115 114 113 112 111 110 109 108 107 106 105 104 103 102 101 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 PVcc2 PA1/TI0B Vss PA0/TI0A AN31 AN30 AVss AVref AVcc AN29 AN28 AN27 AN26 AN25 AN24 AN23 AN22 AN21 AN20 AN19 AN18 AN17 AN16 AN15 AN14 AN13 AVcc AVref AVss AN12 AN11 AN10 AN9 AN8 AN7 AN6 AN5 AN4 AN3 AN2 AN1 AN0 Vss NMI PVcc1 PH15/D15 PH14/D14 PH13/D13 PH12/D12 PH11/D11 Vss PK7/TO8H Vcc PK6/TO8G PK5/TO8F PK4/TO8E PK3/TO8D PK2/TO8C PK1/TO8B Vss PK0/TO8A PVcc2 PJ15/TI9F PJ14/TI9E PJ13/TI9D PJ12/TI9C PJ11/TI9B PJ10/TI9A Vcc PJ9/TIO5D Vss PJ8/TIO5C PJ7/TIO2H PJ6/TIO2G PJ5/TIO2F PJ4/TIO2E PJ3/TIO2D PJ2/TIO2C PJ1/TIO2B PJ0/TIO2A / PG3/ Vss /ADEND PG2/ PVcc2 PG1/ PG0/PULS7/HRxD0/HRxD1 PC4/ PC3/RxD2 PC2/TxD2 PC1/RxD1 PC0/TxD1 PB15/PULS5/SCK2 Vss PB14/SCK1/TCLKB/TI10 VCL PB13/SCK0 PB12/TCLKA/ PB11/RxD4/HRxD0/TO8H PB10/TxD4/HTxD0/TO8G PB9/RxD3/TO8F PB8/TxD3/TO8E PB7/TO7D/TO8D PB6/TO7C/TO8C PB5/TO7B/TO8B PB4/TO7A/TO8A Vss PB3/TO6D PVcc2 PB2/TO6C PB1/TO6B PB0/TO6A PA15/RxD0 PA14/TxD0 PA13/TIO5B Vss PA12/TIO5A Vcc PA11/TIO4D PA10/TIO4C PA9/TIO4B PA8/TIO4A PA7/TIO3D PA6/TIO3C PA5/TIO3B PA4/TIO3A PA3/TI0D PA2/TI0C 1.3.2 Pin Functions Table 1.2 summarizes the pin functions. Table 1.2 Type Power supply Pin Functions Symbol VCC Pin No. 11, 49, 52, 75, 139, 187, 203, 237 I/O Input Name Power supply Function Power supply for chip-internal and system ports (RES, MD2-MD0, FWE, HSTBY, NMI, CK, EXTAL, XTAL, HUDI port). Connect all VCC pins to the system power supply. The chip will not operate if there are any open pins. Power supply for bus ports (ports E, F, and H). Connect all PVCC1 pins to the system bus power supply. The chip will not operate if there are any open pins. Power supply for peripheral module ports (ports A, B, C, D, G, J, K, and L, the AUD port, and WDTOVF). Connect all PVCC2 pins to the system peripheral module power supply. The chip will not operate if there are any open pins. Pins for connection to a capacitor used for stablizing the voltage of the internal step-down power supply. Connect this pin to VSS throhgh a capacitor. The capacitor should be located near the pin. Do not connect to an external power supply. PVCC1 20, 39, 70, 83 Input Port power supply 1 PVCC2 128, 148, 172, 194, 212, 247 Input Port power supply 2 VCL 30, 161, 225 Input Internal stepdown power supply Rev.2.0, 07/03, page 9 of 960 Type Power supply Symbol VSS Pin No. 13, 22, 32, 41, 47, 54, 72, 77, 85, 126, 141, 150, 163, 174, 185, 196, 205, 214, 227, 239, 249 56 I/O Input Name Ground Function For connection to ground. Connect all VSS pins to the system ground. The chip will not operate if there are any open pins. Flash memory FWE Input Flash write enable Connected to ground in normal operation. Apply VCC during on-board programming. Rev.2.0, 07/03, page 10 of 960 Table 1.2 Type Clock Pin Functions (cont) Symbol PLLVCC Pin No. 60 I/O Input Name PLL power supply Function On-chip PLL oscillator power supply. For power supply connection, see section 5, Clock Pulse Generator (CPG). PLLVSS 62 Input PLL ground On-chip PLL oscillator ground. For power supply connection, see section 5, Clock Pulse Generator (CPG). PLLCAP 61 Input PLL capacitance On-chip PLL oscillator external capacitance connection pin. For external capacitance connection, see section 5, Clock Pulse Generator (CPG). EXTAL 51 Input External clock For connection to a crystal resonator. An external clock source can also be connected to the EXTAL pin. For connection to a crystal resonator. Supplies the system clock to peripheral devices. Executes a power-on reset when driven low. WDT overflow output signal. Driven low when an external device requests the bus. Indicates that the bus has been granted to an external device. The device that output the BREQ signal recognizes that the bus has been acquired when it receives the BACK signal. XTAL CK System control RES WDTOVF BREQ BACK 53 48 58 124 46 45 Input Output Input Output Input Output Crystal System clock Power-on reset Watchdog timer overflow Bus request Bus request acknowledge Rev.2.0, 07/03, page 11 of 960 Table 1.2 Type Operating mode control Pin Functions (cont) Symbol MD0 to MD2 Pin No. 59, 55, 50 I/O Input Name Mode setting Function These pins determine the operating mode. Do not change the input values during operation. When driven low, this pin forces a transition to hardware standby mode. Nonmaskable interrupt request pin. Acceptance on the rising edge or falling edge can be selected. IRQ0 to IRQ7 169, 171, 173, 175, 230, 226, 217, 218 231 Input Interrupt requests 0 to 7 Interrupt request output Maskable interrupt request pins. Level input or edge input can be selected. Indicates that an interrupt has been generated. Enables interrupt generation to be recognized in the busreleased state. Address output pins. HSTBY 57 Input Hardware standby Nonmaskable interrupt Interrupts NMI 84 Input IRQOUT Output Address bus A0-A21 7-10, 12, 14-19, 21, 23-29, 31, 33, 34 63-69, 71, 73, 74, 76, 78-82 40, 42-44 38 36 35 37 Output Address bus Data bus D0-D15 Input/ output Output Output Output Output Input Data bus 16-bit bidirectional data bus pins. Chip select signals for external memory or devices. Indicates reading from an external device. Indicates writing of the upper 8 bits of external data. Indicates writing of the lower 8 bits of external data. Input for wait cycle insertion in bus cycles during external space access. Bus control CS0-CS3 RD WRH WRL WAIT Chip select 0 to 3 Read Upper write Lower write Wait Rev.2.0, 07/03, page 12 of 960 Table 1.2 Type Advanced timer unit-II (ATU-II) Pin Functions (cont) Symbol TCLKA TCLKB Pin No. 159, 162, 219 I/O Input Input Name ATU-II timer clock input ATU-II input capture (channel 0) ATU-II input capture/output compare (channel 1) ATU-II input capture/output compare (channel 2) ATU-II input capture/output compare/ PWM output (channel 3) ATU-II input capture/output compare/ PWM output (channel 4) ATU-II input capture/output compare/ PWM output (channel 5) ATU-II PWM output (channel 6) ATU-II PWM output (channel 7) Function ATU-II counter external clock Input pins. Channel 0 input capture input pins. Channel 1 input capture input/output compare output pins. Channel 2 input capture input/output compare output pins. Channel 3 input capture input/output compare/PWM output pins. TI0A-TI0D 125, 127, 129, 130 TIO1A- TIO1H 248, 250-256 Input/ output TIO2A- TIO2H 176-183 Input/ output TIO3A- TIO3D 131-134 Input/ output TIO4A- TIO4D 135-138 Input/ output Channel 4 input capture input/output compare/PWM output pins. TIO5A- TIO5D 140, 142, 184, 186 Input/ output Channel 5 input capture input/output compare/PWM output pins. TO6A- TO6D TO7A- TO7D TO8A- TO8P 145-147, 149 151-154 Output Channel 6 PWM output pins. Output Channel 7 PWM output pins. 151-158, 195, 197-202, 204, 206-211, 213, 215 Output ATU-II Channel 8 down-counter oneone-shot pulse shot pulse output pins. (channel 8) Rev.2.0, 07/03, page 13 of 960 Table 1.2 Type Advanced timer unit-II (ATU-II) Pin Functions (cont) Symbol TI9A- TI9F TI10 Pin No. 188-193 I/O Input Name ATU-II event input (channel 9) Function Channel 9 event counter input pins. 162, 216 Input ATU-II Channel 10 external clock multiplied clock input pin. generation (channel 10) ATU-II input capture/output compare APC pulse outputs 0 to 7 Transmit data (channels 0 to 4) Receive data (channels 0 to 4) Serial clock (channels 0 to 4) Transmit data Receive data Analog power supply Channel 11 input capture input/output compare output pins. APC pulse output pins. TIO11A, TIO11B Advanced PULS0- pulse controller PULS7 (APC) Serial TxD0- communication TxD4 interface (SCI) RxD0- RxD4 SCK0- SCK4 Controller area HTxD0, HTxD1 network (HCAN) HRxD0, HRxD1 A/D converter AVCC AVSS AVref 217, 218 Input/ output Output 1-6, 164, 170 143, 165, 167, 155, 157 144, 166, 168, 156, 158 160, 162, 223, 224, 226, 164 157, 228, 6 158, 229, 170 101, 119 99, 121 100, 120 Output SCI0 to SCI4 transmit data output pins. SCI0 to SCI4 receive data input pins. SCI0 to SCI4 clock input/output pins. CAN bus transmit data output pins. CAN bus receive data input pins. A/D converter power supply. Input Input/ output Output input Input Input Input Analog ground A/D converter power supply. Analog reference power supply Analog input Analog reference power supply input pins. Analog signal input pins. AN0-AN31 86-98, 102-118, 122, 123 ADTRG0, ADTRG1 ADEND 175, 220, 221 173, 222 Input Input Output A/D conversion External trigger input pins for trigger input starting A/D conversion. ADEND output A/D2 channel 31 conversion timing monitor output pins. Rev.2.0, 07/03, page 14 of 960 Table 1.2 Type Pin Functions (cont) Symbol Pin No. 159 236 232 234 235 233 I/O Output Input Input Input Output Input Input/ output Name User break trigger output Test clock Test mode select Test data input Test data output Test reset AUD data Function UBC condition match trigger output pin. Test clock input pin. Test mode select signal input pin. Instruction/data serial input pin. Instruction/data serial output pin. Initialization signal input pin. Realtime trace mode: Branch destination address output pins. RAM monitor mode: Monitor address input / data input/output pins. AUDRST AUDMD 238 240 Input Input AUD reset AUD mode Reset signal input pin. Mode select signal input pin. Realtime trace mode: Low RAM monitor mode: High AUDCK 245 Input/ output AUD clock Realtime trace mode: Serial clock output pin. RAM monitor mode: Serial clock input pin. AUDSYNC 246 Input/ output AUD Realtime trace mode: Data synchronization start position identification signal signal output pin. RAM monitor mode: Data start position identification signal input pin. User break UBCTRG controller (UBC) HighPerformance user debug interface (H-UDI) TCK TMS TDI TDO TRST Advanced AUDATA0- 241-244 user debugger AUDATA3 (AUD) I/O ports POD 34 Input Port output disable Port A Input pin for port pin drive control when general port is set for output. General input/output port pins. Input or output can be specified bit by bit. PA0-PA15 125, 127, 129-138, 140, 142-144 Input/ output Rev.2.0, 07/03, page 15 of 960 Table 1.2 Type I/O ports Pin Functions (cont) Symbol Pin No. I/O Input/ output Name Port B Function General input/output port pins. Input or output can be specified bit by bit. Port C General input/output port pins. Input or output can be specified bit by bit. Port D General input/output port pins. Input or output can be specified bit by bit. Port E General input/output port pins. Input or output can be specified bit by bit. Port F General input/output port pins. Input or output can be specified bit by bit. Port G General input/output port pins. Input or output can be specified bit by bit. Port H General input/output port pins. Input or output can be specified bit by bit. Port J General input/output port pins. Input or output can be specified bit by bit. Port K General input/output port pins. Input or output can be specified bit by bit. PB0-PB15 145-147, 149, 151-160, 162, 164 PC0-PC4 165-169 Input/ output Input/ output Input/ output Input/ output Input/ output Input/ output Input/ output Input/ output PD0-PD13 248, 250-256, 1-6 PE0-PE15 7-10, 12, 14-19, 21, 23-26 PF0-PF15 27-29, 31, 33-38, 40, 42-46 PG0-PG3 170, 171, 173, 175 PH0-PH15 63-69, 71, 73, 74, 76, 78-82 PJ0-PJ15 176-184, 186, 188-193 PK0-PK15 195, 197-202, 204, 206-211, 213, 215 PL0-PL13 216-224, 226, 228-231 Input/ output Port L General input/output port pins. Input or output can be specified bit by bit. Rev.2.0, 07/03, page 16 of 960 1.3.3 Table 1.3 Pin No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 Pin Assignments Pin Assignments MCU Mode PD8/PULS0 PD9/PULS1 PD10/PULS2 PD11/PULS3 PD12/PULS4 PD13/PULS6/HTxD0/HTxD1 PE0/A0 PE1/A1 PE2/A2 PE3/A3 Vcc PE4/A4 Vss PE5/A5 PE6/A6 PE7/A7 PE8/A8 PE9/A9 PE10/A10 PVcc1 PE11/A11 Vss PE12/A12 PE13/A13 PE14/A14 PE15/A15 PF0/A16 PF1/A17 PF2/A18 VCL Programmer Mode N.C N.C N.C N.C N.C N.C A0 A1 A2 A3 Vcc A4 Vss A5 A6 A7 A8 A9 A10 Vcc A11 Vss A12 A13 A14 A15 A16 A17 A18 VCL Rev.2.0, 07/03, page 17 of 960 Table 1.3 Pin No. 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 Pin Assignments (cont) MCU Mode PF3/A19 Vss PF4/A20 PF5/A21/POD PF6/WRL PF7/WRH PF8/WAIT PF9/RD PVcc1 PF10/CS0 Vss PF11/CS1 PF12/CS2 PF13/CS3 PF14/BACK PF15/BREQ Vss CK Vcc MD2 EXTAL Vcc XTAL Vss MD1 FWE HSTBY RES MD0 PLLVcc PLLCAP Programmer Mode A19 Vss N.C. N.C. N.C. N.C. Vcc N.C. Vcc N.C. Vss Vcc Vcc Vss N.C. Vcc Vss N.C. Vcc Vss EXTAL Vcc XTAL Vss Vcc FWE Vcc RES Vcc PLLVcc PLLCAP Rev.2.0, 07/03, page 18 of 960 Table 1.3 Pin No. 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 Pin Assignments (cont) MCU Mode PLLVss PH0/D0 PH1/D1 PH2/D2 PH3/D3 PH4/D4 PH5/D5 PH6/D6 PVcc1 PH7/D7 Vss PH8/D8 PH9/D9 Vcc PH10/D10 Vss PH11/D11 PH12/D12 PH13/D13 PH14/D14 PH15/D15 PVcc1 NMI Vss AN0 AN1 AN2 AN3 AN4 AN5 AN6 Programmer Mode PLLVss D0 D1 D2 D3 D4 D5 D6 Vcc D7 Vss N.C. N.C. Vcc N.C. Vss N.C. N.C. N.C. N.C. N.C. Vcc Vss Vss N.C. N.C. N.C. N.C. N.C. N.C. N.C. Rev.2.0, 07/03, page 19 of 960 Table 1.3 Pin No. 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 Pin Assignments (cont) MCU Mode AN7 AN8 AN9 AN10 AN11 AN12 AVss AVref AVcc AN13 AN14 AN15 AN16 AN17 AN18 AN19 AN20 AN21 AN22 AN23 AN24 AN25 AN26 AN27 AN28 AN29 AVcc AVref AVss AN30 AN31 Programmer Mode N.C. N.C. N.C. N.C. N.C. N.C. Vss Vcc Vcc N.C. N.C. N.C. N.C. N.C. N.C. N.C. N.C. N.C. N.C. N.C. N.C. N.C. N.C. N.C. N.C. N.C. Vcc Vcc Vss N.C. N.C. Rev.2.0, 07/03, page 20 of 960 Table 1.3 Pin No. 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 154 Pin Assignments (cont) MCU Mode WDTOVF PA0/TI0A Vss PA1/TI0B PVcc2 PA2/TI0C PA3/TI0D PA4/TIO3A PA5/TIO3B PA6/TIO3C PA7/TIO3D PA8/TIO4A PA9/TIO4B PA10/TIO4C PA11/TIO4D Vcc PA12/TIO5A Vss PA13/TIO5B PA14/TxD0 PA15/RxD0 PB0/TO6A PB1/TO6B PB2/TO6C PVcc2 PB3/TO6D Vss PB4/TO7A/TO8A PB5/TO7B/TO8B PB6/TO7C/TO8C PB7/TO7D/TO8D Programmer Mode N.C. N.C. Vss N.C. Vcc N.C. N.C. N.C. N.C. N.C. N.C. N.C. N.C. N.C. N.C. Vcc N.C. Vss N.C. N.C. N.C. N.C. N.C. N.C. Vcc N.C. Vss N.C. N.C. N.C. N.C. Rev.2.0, 07/03, page 21 of 960 Table 1.3 Pin No. 155 156 157 158 159 160 161 162 163 164 165 166 167 168 169 170 171 172 173 174 175 176 177 178 179 180 181 182 183 184 185 Pin Assignments (cont) MCU Mode PB8/TxD3/TO8E PB9/RxD3/TO8F PB10/TxD4/HTxD0/TO8G PB11/RxD4/HRxD0/TO8H PB12/TCLKA/UBCTRG PB13/SCK0 VCL PB14/SCK1/TCLKB/TI10 Vss PB15/PULS5/SCK2 PC0/TxD1 PC1/RxD1 PC2/TxD2 PC3/RxD2 PC4/IRQ0 PG0/PULS7/HRxD0/HRxD1 PG1/IRQ1 PVcc2 PG2/IRQ2/ADEND Vss PG3/IRQ3/ADTRG0 PJ0/TIO2A PJ1/TIO2B PJ2/TIO2C PJ3/TIO2D PJ4/TIO2E PJ5/TIO2F PJ6/TIO2G PJ7/TIO2H PJ8/TIO5C Vss Programmer Mode N.C. N.C. N.C. N.C. N.C. N.C. VCL N.C. Vss N.C. N.C. N.C. N.C. N.C. N.C. N.C. N.C. Vcc N.C. Vss N.C. N.C. N.C. N.C. N.C. N.C. N.C. N.C. N.C. N.C. Vss Rev.2.0, 07/03, page 22 of 960 Table 1.3 Pin No. 186 187 188 189 190 191 192 193 194 195 196 197 198 199 200 201 202 203 204 205 206 207 208 209 210 211 212 213 214 215 216 Pin Assignments (cont) MCU Mode PJ9/TIO5D Vcc PJ10/TI9A PJ11/TI9B PJ12/TI9C PJ13/TI9D PJ14/TI9E PJ15/TI9F PVcc2 PK0/TO8A Vss PK1/TO8B PK2/TO8C PK3/TO8D PK4/TO8E PK5/TO8F PK6/TO8G Vcc PK7/TO8H Vss PK8/TO8I PK9/TO8J PK10/TO8K PK11/TO8L PK12/TO8M PK13/TO8N PVcc2 PK14/TO8O Vss PK15/TO8P PL0/TI10 Programmer Mode N.C. Vcc N.C. N.C. N.C. N.C. N.C. N.C. Vcc N.C. Vss N.C. N.C. N.C. N.C. N.C. N.C. Vcc N.C. Vss N.C. N.C. N.C. N.C N.C. N.C. Vcc N.C. Vss N.C. N.C. Rev.2.0, 07/03, page 23 of 960 Table 1.3 Pin No. 217 218 219 220 221 222 223 224 225 226 227 228 229 230 231 232 233 234 235 236 237 238 239 240 241 242 243 244 245 246 247 Pin Assignments (cont) MCU Mode PL1/TIO11A/IRQ6 PL2/TIO11B/IRQ7 PL3/TCLKB PL4/ADTRG0 PL5/ADTRG1 PL6/ADEND PL7/SCK2 PL8/SCK3 VCL PL9/SCK4/IRQ5 Vss PL10/HTxD0/HTxD1/HTxD0 & HTxD1 PL11/HRxD0/HRxD1/HRxD0 & HRxD1 PL12/IRQ4 PL13/IRQOUT TMS TRST TDI TDO TCK Vcc AUDRST Vss AUDMD AUDATA0 AUDATA1 AUDATA2 AUDATA3 AUDCK AUDSYNC PVcc2 Programmer Mode N.C. CE N.C. N.C. N.C. N.C. N.C. N.C. VCL WE Vss N.C. N.C. OE N.C. N.C. N.C. N.C. N.C. N.C. Vcc N.C. Vss N.C. N.C. N.C. N.C. N.C. N.C. N.C. Vcc Rev.2.0, 07/03, page 24 of 960 Table 1.3 Pin No. 248 249 250 251 252 253 254 255 256 Pin Assignments (cont) MCU Mode PD0/TIO1A Vss PD1/TIO1B PD2/TIO1C PD3/TIO1D PD4/TIO1E PD5/TIO1F PD6/TIO1G PD7/TIO1H Programmer Mode N.C. Vss N.C. N.C. N.C. N.C. N.C. N.C. N.C. Rev.2.0, 07/03, page 25 of 960 Rev.2.0, 07/03, page 26 of 960 Section 2 CPU 2.1 Register Configuration The register set consists of sixteen 32-bit general registers, three 32-bit control registers and four 32-bit system registers. In addition, the FPU has eighteen internal registers: sixteen 32-bit floating-point registers and two 32-bit floating-point system registers. 2.1.1 General Registers (Rn) The sixteen 32-bit general registers (Rn) are numbered R0-R15. General registers are used for data processing and address calculation. R0 is also used as an index register. Several instructions have R0 fixed as their only usable register. R15 is used as the hardware stack pointer (SP). Saving and recovering the status register (SR) and program counter (PC) in exception processing is accomplished by referencing the stack using R15. Figure 2.1 shows the general registers. 31 R0*1 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15, SP (hardware stack pointer)*2 Notes: *1. R0 functions as an index register in the indirect indexed register addressing mode and indirect indexed GBR addressing mode. In some instructions, R0 functions as a fixed source register or destination register. *2. R15 functions as a hardware stack pointer (SP) during exception processing. 0 Figure 2.1 General Registers Rev.2.0, 07/03, page 27 of 960 2.1.2 Control Registers The 32-bit control registers consist of the 32-bit status register (SR), global base register (GBR), and vector base register (VBR). The status register indicates processing states. The global base register functions as a base address for the indirect GBR addressing mode to transfer data to the registers of on-chip peripheral modules. The vector base register functions as the base address of the exception processing vector area (including interrupts). Figure 2.2 shows the control registers. 31 SR 9 8 7 6 5 4 32 1 0 M Q I3 I2 I1 I0 ST SR: Status register T bit: The MOVT, CMP/cond, TAS, TST, BT (BT/S), BF (BF/S), SETT, CLRT, and FCMP/cond instructions use the T bit to indicate true (1) or false (0). The ADDV, ADDC, SUBV, SUBC, NEGC, DIV0U, DIV0S, DIV1, SHAR, SHAL, SHLR, SHLL, ROTR, ROTL, ROTCR, and ROTCL instructions also use the T bit to indicate carry/borrow or overflow/underflow. S bit: Used by the MAC instruction. Reserved bits. These bits always read 0. The write value should always be 0. Bits I3-I0: Interrupt mask bits. M and Q bits: Used by the DIV0U, DIV0S, and DIV1 instructions. Reserved bits. These bits always read 0. The write value should always be 0. 31 GBR 0 Global base register (GBR): Indicates the base address of the indirect GBR addressing mode. The indirect GBR addressing mode is used in data transfer for on-chip peripheral module register areas and in logic operations. 0 VBR Vector base register (VBR): Stores the base address of the exception processing vector area. 31 Figure 2.2 Control Register Configuration Rev.2.0, 07/03, page 28 of 960 2.1.3 System Registers System registers consist of four 32-bit registers: high and low multiply and accumulate registers (MACH and MACL), the procedure register (PR), and the program counter (PC). The multiplyand-accumulate registers store the results of multiply-and-accumulate operations. The procedure register stores the return address from a subroutine procedure. The program counter stores program addresses to control the flow of the processing. Figure 2.3 shows the system registers. 31 MACH MACL 0 Multiply-and-accumulate (MAC) registers high and low (MACH, MACL): Store the results of multiply-and-accumulate operations. Procedure register (PR): Stores the return address from a subroutine procedure. Program counter (PC): Indicates the fourth byte (second instruction) after the current instruction. 31 PR 0 31 PC 0 Figure 2.3 System Register Configuration Rev.2.0, 07/03, page 29 of 960 2.1.4 Floating-Point Registers There are sixteen 32-bit floating-point registers, designated FR0 to FR15, which are used by floating-point instructions. FR0 functions as the index register for the FMAC instruction. These registers are incorporated into the floating-point unit (FPU). For details, see section 3, FloatingPoint Unit (FPU). 31 FR0 FR1 FR2 FR3 FR4 FR5 FR6 FR7 FR8 FR9 FR10 FR11 FR12 FR13 FR14 FR15 0 FR0 functions as the index register for the FMAC instruction. Figure 2.4 Floating-Point Registers Rev.2.0, 07/03, page 30 of 960 2.1.5 Floating-Point System Registers There are two 32-bit floating-point system registers: the floating-point communication register (FPUL) and the floating-point status/control register (FPSCR). FPUL is used for communication between the CPU and the floating-point unit (FPU). FPSCR indicates and stores status/control information relating to FPU exceptions. These registers are incorporated into the floating-point unit (FPU). For details, see section 3, Floating-Point Unit (FPU). 31 FPUL 31 FPSCR 0 FPSCR: Floating-point status/control register Indicates and stores status/control information relating to FPU exceptions. 0 FPUL: Floating-point communication register Used for communication between the CPU and the FPU. Figure 2.5 Floating-Point System Registers 2.1.6 Initial Values of Registers Table 2.1 lists the values of the registers after reset. Table 2.1 Initial Values of Registers Register R0-R14 R15 (SP) Control registers SR GBR VBR System registers MACH, MACL, PR PC Floating-point registers Floating-point system registers FR0-FR15 FPUL FPSCR Initial Value Undefined Value of the stack pointer in the vector address table Bits I3-I0 are 1111 (H'F), reserved bits are 0, and other bits are undefined Undefined H'00000000 Undefined Value of the program counter in the vector address table Undefined Undefined H'00040001 Classification General registers Rev.2.0, 07/03, page 31 of 960 2.2 2.2.1 Data Formats Data Format in Registers Register operands are always longwords (32 bits). When the memory operand is only a byte (8 bits) or a word (16 bits), it is sign-extended into a longword when loaded into a register (figure 2.6). 31 Longword 0 Figure 2.6 Data Format in Registers 2.2.2 Data Formats in Memory Memory data formats are classified into bytes, words, and longwords. Byte data can be accessed from any address, but an address error will occur if an attempt is made to access word data starting from an address other than 2n or longword data starting from an address other than 4n. In such cases, the data accessed cannot be guaranteed. The hardware stack area, referred to by the hardware stack pointer (SP, R15), uses only longword data starting from address 4n because this area holds the program counter and status register (figure 2.7). Address m + 1 Address m 31 Byte Address 2n Address 4n 23 Byte Word Longword 15 Byte Address m + 3 7 Byte Word 0 Address m + 2 Figure 2.7 Data Formats in Memory 2.2.3 Immediate Data Format Byte (8 bit) immediate data resides in an instruction code. Immediate data accessed by the MOV, ADD, and CMP/EQ instructions is sign-extended and handled in registers as longword data. Immediate data accessed by the TST, AND, OR, and XOR instructions is zero-extended and handled as longword data. Consequently, AND instructions with immediate data always clear the upper 24 bits of the destination register. Rev.2.0, 07/03, page 32 of 960 Word or longword immediate data is not located in the instruction code, but instead is stored in a memory table. An immediate data transfer instruction (MOV) accesses the memory table using the PC relative addressing mode with displacement. 2.3 2.3.1 Instruction Features RISC-Type Instruction Set All instructions are RISC type. This section details their functions. 16-Bit Fixed Length: All instructions are 16 bits long, increasing program code efficiency. One Instruction per Cycle: The microprocessor can execute basic instructions in one cycle using the pipeline system. Instructions are executed in 25 ns at 40 MHz. Data Length: Longword is the standard data length for all operations. Memory can be accessed in bytes, words, or longwords. Byte or word data accessed from memory is sign-extended and handled as longword data. Immediate data is sign-extended for arithmetic operations or zeroextended for logic operations. It also is handled as longword data (table 2.2). Table 2.2 Sign Extension of Word Data Description Example of Conventional CPU ADD.W #H'1234,R0 SH7055SF CPU MOV.W ADD .DATA.W @(disp,PC),R1 Data is sign-extended to 32 bits, and R1 becomes R1,R0 H'00001234. It is next ......... operated upon by an ADD instruction. H'1234 Note: @(disp, PC) accesses the immediate data. Load-Store Architecture: Basic operations are executed between registers. For operations that involve memory access, data is loaded to the registers and executed (load-store architecture). Instructions such as AND that manipulate bits, however, are executed directly in memory. Delayed Branch Instructions: Unconditional branch instructions are delayed branch instructions. With a delayed branch instruction, the branch is taken after execution of the instruction following the delayed branch instruction. There are two types of conditional branch instructions: delayed branch instructions and ordinary branch instructions. Rev.2.0, 07/03, page 33 of 960 Table 2.3 Delayed Branch Instructions Description Executes the ADD before branching to TRGET. Example of Conventional CPU ADD.W BRA R1,R0 TRGET SH7055SF CPU BRA ADD TRGET R1,R0 Multiply/Multiply-and-Accumulate Operations: 16-bit x 16-bit 32-bit multiply operations are executed in one to two cycles. 16-bit x 16-bit + 64-bit 64-bit multiply-and-accumulate operations are executed in two to three cycles. 32-bit x 32-bit 64-bit multiply and 32-bit x 32bit + 64bit 64-bit multiply-and-accumulate operations are executed in two to four cycles. T Bit: The T bit in the status register changes according to the result of the comparison, and in turn is the condition (true/false) that determines if the program will branch. The number of instructions that change the T bit is kept to a minimum to improve the processing speed (table 2.4). Table 2.4 T Bit Description T bit is set when R0 = R1. The program branches to TRGET0 when R0 = R1 and to TRGET1 when R0 < R1. T bit is not changed by ADD. T bit is set when R0 = 0. The program branches if R0 = 0. Example of Conventional CPU CMP.W BGE BLT SUB.W BEQ R1,R0 TRGET0 TRGET1 #1,R0 TRGET SH7055SF CPU CMP/GE BT BF ADD CMP/EQ BT R1,R0 TRGET0 TRGET1 #1,R0 #0,R0 TRGET Immediate Data: Byte (8-bit) immediate data resides in the instruction code. Word or longword immediate data is not input via instruction codes but is stored in a memory table. An immediate data transfer instruction (MOV) accesses the memory table using the PC relative addressing mode with displacement (table 2.5). Rev.2.0, 07/03, page 34 of 960 Table 2.5 Immediate Data Accessing SH7055SF CPU MOV MOV.W #H'12,R0 @(disp,PC),R0 ................. .DATA.W H'1234 @(disp,PC),R0 ................. .DATA.L H'12345678 MOV.L #H'12345678,R0 Example of Conventional CPU MOV.B MOV.W #H'12,R0 #H'1234,R0 Classification 8-bit immediate 16-bit immediate 32-bit immediate MOV.L Note: @(disp, PC) accesses the immediate data. Absolute Address: When data is accessed by absolute address, the value already in the absolute address is placed in the memory table. Loading the immediate data when the instruction is executed transfers that value to the register and the data is accessed in the indirect register addressing mode (table 2.6). Table 2.6 Absolute Address Accessing SH7055SF CPU MOV.L MOV.B @(disp,PC),R1 @R1,R0 .................. .DATA.L H'12345678 Note: @(disp,PC) accesses the immediate data. Example of Conventional CPU MOV.B @H'12345678,R0 Classification Absolute address 16-Bit/32-Bit Displacement: When data is accessed by 16-bit or 32-bit displacement, the preexisting displacement value is placed in the memory table. Loading the immediate data when the instruction is executed transfers that value to the register and the data is accessed in the indirect indexed register addressing mode (table 2.7). Table 2.7 Displacement Accessing SH7055SF CPU MOV.W MOV.W @(disp,PC),R0 @(R0,R1),R2 .................. .DATA.W H'1234 Note: @(disp,PC) accesses the immediate data. Example of Conventional CPU MOV.W @(H'1234,R1),R2 Classification 16-bit displacement Rev.2.0, 07/03, page 35 of 960 2.3.2 Addressing Modes Table 2.8 describes addressing modes and effective address calculation. Table 2.8 Addressing Mode Direct register addressing Indirect register addressing Post-increment indirect register addressing Addressing Modes and Effective Addresses Instruction Format Effective Address Calculation Rn @Rn The effective address is register Rn. (The operand is the contents of register Rn.) Equation -- The effective address is the contents of register Rn. Rn Rn @Rn+ Rn Rn (After the instruction executes) Byte: Rn + 1 Rn Word: Rn + 2 Rn Longword: Rn + 4 Rn Byte: Rn - 1 Rn Word: Rn - 2 Rn Longword: Rn - 4 Rn (Instruction executed with Rn after calculation) The effective address is the contents of register Rn. A constant is added to the content of Rn after the instruction is executed. 1 is added for a byte operation, 2 for a word operation, and 4 for a longword operation. Rn Rn + 1/2/4 1/2/4 + Rn Pre-decrement indirect register addressing @-Rn The effective address is the value obtained by subtracting a constant from Rn. 1 is subtracted for a byte operation, 2 for a word operation, and 4 for a longword operation. Rn Rn - 1/2/4 1/2/4 - Rn - 1/2/4 Rev.2.0, 07/03, page 36 of 960 Table 2.8 Addressing Mode Addressing Modes and Effective Addresses (cont) Instruction Format Effective Address Calculation @(disp:4, The effective address is Rn plus a 4-bit displacement (disp). The value of disp is zeroRn) extended, and remains the same for a byte operation, is doubled for a word operation, and is quadrupled for a longword operation. Rn disp (zero-extended) x 1/2/4 + Rn + disp x 1/2/4 Equation Byte: Rn + disp Word: Rn + disp x 2 Longword: Rn + disp x 4 Indirect register addressing with displacement Indirect indexed @(R0, Rn) The effective address is the Rn value plus R0. register Rn addressing + R0 Rn + R0 Rn + R0 Indirect GBR addressing with displacement @(disp:8, The effective address is the GBR value plus an 8-bit displacement (disp). The value of disp is zeroGBR) extended, and remains the same for a byte operation, is doubled for a word operation, and is quadrupled for a longword operation. GBR disp (zero-extended) x 1/2/4 + GBR + disp x 1/2/4 Byte: GBR + disp Word: GBR + disp x 2 Longword: GBR + disp x 4 Rev.2.0, 07/03, page 37 of 960 Table 2.8 Addressing Mode Addressing Modes and Effective Addresses (cont) Instruction Format Effective Address Calculation Equation GBR + R0 Indirect indexed @(R0, GBR)The effective address is the GBR value plus R0. GBR addressing GBR + R0 GBR + R0 Indirect PC addressing with displacement @(disp:8, The effective address is the PC value plus an 8-bit displacement (disp). The value of disp is zeroPC) extended, and is doubled for a word operation, and quadrupled for a longword operation. For a longwordoperation, the lowest two bits of the PC value are masked. PC & H'FFFFFFFC disp (zero-extended) x 2/4 (for longword) PC + disp x 2 or PC & H'FFFFFFFC + disp x 4 Word: PC + disp x 2 Longword: PC & H'FFFFFFFC + disp x 4 + Rev.2.0, 07/03, page 38 of 960 Table 2.8 Addressing Mode PC relative addressing Addressing Modes and Effective Addresses (cont) Instruction Format Effective Addresses Calculation disp:8 The effective address is the PC value sign-extended with an 8-bit displacement (disp), doubled, and addedto the PC value. PC disp (sign-extended) x 2 + PC + disp x 2 Equation PC + disp x 2 disp:12 The effective address is the PC value sign-extended PC + disp x with a 12-bit displacement (disp), doubled, and added 2 to the PC value. PC disp (sign-extended) x 2 + PC + disp x 2 Rn The effective address is the register PC value plus Rn. PC + Rn PC + Rn PC + Rn Immediate addressing #imm:8 #imm:8 #imm:8 The 8-bit immediate data (imm) for the TST, AND, OR, and XOR instructions is zero-extended. The 8-bit immediate data (imm) for the MOV, ADD, and CMP/EQ instructions is sign-extended. The 8-bit immediate data (imm) for the TRAPA instruction is zero-extended and quadrupled. -- -- -- Rev.2.0, 07/03, page 39 of 960 2.3.3 Instruction Format Table 2.9 lists the instruction formats for the source operand and the destination operand. The meaning of the operand depends on the instruction code. The symbols used are as follows: 1. xxxx: Instruction code 2. mmmm: Source register 3. nnnn: Destination register 4. iiii: Immediate data 5. dddd: Displacement Table 2.9 Instruction Formats Source Operand -- 0 xxxx xxxx xxxx Instruction Formats 0 format 15 xxxx Destination Operand -- Example NOP n format 15 xxxx nnnn xxxx xxxx 0 -- Control register or system register Control register or system register nnnn: Direct register nnnn: Direct register MOVT STS Rn MACH,Rn nnnn: Indirect pre- STC.L decrement register Control register or system register Control register or system register -- -- LDC LDC.L SR,@-Rn m format 15 xxxx mmmm xxxx xxxx 0 mmmm: Direct register mmmm: Indirect post-increment register mmmm: Direct register mmmm: PC relative using Rm Rm,SR @Rm+,SR JMP BRAF @Rm Rm Rev.2.0, 07/03, page 40 of 960 Table 2.9 Instruction Formats (cont) Destination Source Operand Operand 0 Instruction Formats nm format 15 xxxx nnnn mmmm xxxx Example ADD MOV.L Rm,Rn Rm,@Rn mmmm: Direct register mmmm: Direct register mmmm: Indirect post-increment register (multiplyand-accumulate) nnnn*: Indirect post-increment register (multiplyand-accumulate) mmmm: Indirect post-increment register mmmm: Direct register mmmm: Direct register nnnn: Direct register nnnn: Indirect register MACH, MACL MAC.W @Rm+,@Rn+ nnnn: Direct register nnnn: Indirect predecrement register nnnn: Indirect indexed register R0 (Direct register) MOV.L @Rm+,Rn MOV.L Rm,@-Rn MOV.L Rm,@(R0,Rn) MOV.B @(disp,Rn),R0 md format 15 xxxx xxxx mmmm dddd 0 mmmmdddd: Indirect register with displacement R0 (Direct register) nd4 format 15 xxxx xxxx nnnn dddd nmd format 0 nnnndddd: Indirect register with displacement nnnndddd: Indirect register with displacement nnnn: Direct register MOV.B R0,@(disp,Rn) 15 xxxx nnnn mmmm dddd 0 mmmm: Direct register mmmmdddd: Indirect register with displacement MOV.L Rm,@(disp,Rn) MOV.L @(disp,Rm),Rn Note: * In multiply-and-accumulate instructions, nnnn is the source register. Rev.2.0, 07/03, page 41 of 960 Table 2.9 Instruction Formats (cont) Destination Source Operand Operand 0 Instruction Formats d format 15 xxxx xxxx dddd dddd Example MOV.L @(disp,GBR),R0 dddddddd: Indirect GBR with displacement R0 (Direct register) dddddddd: PC relative with displacement -- R0 (Direct register) dddddddd: Indirect GBR with displacement R0 (Direct register) dddddddd: PC relative dddddddddddd: PC relative MOV.L R0,@(disp,GBR) MOVA @(disp,PC),R0 BF BRA label label d12 format -- 15 xxxx dddd dddd dddd nd8 format 15 xxxx nnnn dddd dddd 0 dddddddd: PC relative with displacement iiiiiiii: Immediate (label = disp + PC) MOV.L @(disp,PC),Rn 0 nnnn: Direct register i format 15 xxxx xxxx iiii iiii 0 iiiiiiii: Immediate iiiiiiii: Immediate Indirect indexed GBR R0 (Direct register) -- nnnn: Direct register AND.B #imm,@(R0,GBR) AND TRAPA ADD #imm,R0 #imm #imm,Rn ni format 15 xxxx nnnn iiii iiii 0 iiiiiiii: Immediate 2.4 2.4.1 Instruction Set by Classification Instruction Set by Classification Table 2.10 lists the instructions according to their classification. Rev.2.0, 07/03, page 42 of 960 Table 2.10 Classification of Instructions Operation Classification Types Code Function Data transfer 5 MOV Data transfer, immediate data transfer, peripheral module data transfer, structure data transfer Effective address transfer T bit transfer Swap of upper and lower bytes Extraction of the middle of registers connected Binary addition Binary addition with carry Binary addition with overflow check 33 No. of Instructions 39 MOVA MOVT SWAP XTRCT Arithmetic operations 21 ADD ADDC ADDV CMP/cond Comparison DIV1 DIV0S DIV0U DMULS DMULU DT EXTS EXTU MAC MUL MULS MULU NEG NEGC SUB SUBC SUBV Division Initialization of signed division Initialization of unsigned division Signed double-length multiplication Unsigned double-length multiplication Decrement and test Sign extension Zero extension Multiply-and-accumulate, double-length multiply-and-accumulate operation Double-length multiply operation Signed multiplication Unsigned multiplication Negation Negation with borrow Binary subtraction Binary subtraction with borrow Binary subtraction with underflow Rev.2.0, 07/03, page 43 of 960 Table 2.10 Classification of Instructions (cont) Operation Classification Types Code Function Logic operations 6 AND NOT OR TAS TST XOR Shift 10 ROTL ROTR ROTCL ROTCR SHAL SHAR SHLL SHLLn SHLR SHLRn Branch 9 BF BT BRA BRAF BSR BSRF JMP JSR RTS Logical AND Bit inversion Logical OR Memory test and bit set Logical AND and T bit set Exclusive OR One-bit left rotation One-bit right rotation One-bit left rotation with T bit One-bit right rotation with T bit One-bit arithmetic left shift One-bit arithmetic right shift One-bit logical left shift n-bit logical left shift One-bit logical right shift n-bit logical right shift Conditional branch, conditional branch with delay (Branch when T = 0) Conditional branch, conditional branch with delay (Branch when T = 1) Unconditional branch Unconditional branch Branch to subroutine procedure Branch to subroutine procedure Unconditional branch Branch to subroutine procedure Return from subroutine procedure 11 14 No. of Instructions 14 Rev.2.0, 07/03, page 44 of 960 Table 2.10 Classification of Instructions (cont) Operation Classification Types Code Function System control 11 CLRT CLRMAC LDC LDS NOP RTE SETT SLEEP STC STS TRAPA Floating-point 15 instructions FABS FADD FCMP FDIV FLDI0 FLDI1 FLDS FLOAT FMAC FMOV FMUL FNEG FSTS FSUB FTRC FPU-related CPU instructions Total: 2 LDS STS 79 T bit clear MAC register clear Load to control register Load to system register No operation Return from exception processing T bit set Transition to power-down mode Store control register data Store system register data Trap exception handling Floating-point absolute value Floating-point addition Floating-point comparison Floating-point division Floating-point load immediate 0 Floating-point load immediate 1 Floating-point load into system register FPUL Integer-to-floating-point conversion Floating-point multiply-and-accumulate operation Floating-point data transfer Floating-point multiplication Floating-point sign inversion Floating-point store from system register FPUL Floating-point subtraction Floating-point conversion with rounding to integer Load into floating-point system register Store from floating-point system register 172 8 22 No. of Instructions 31 Rev.2.0, 07/03, page 45 of 960 Table 2.11 shows the format used in tables 2.12 to 2.19, which list instruction codes, operation, and execution states in order by classification. Table 2.11 Instruction Code Format Item Instruction Format OP.Sz SRC,DEST Explanation OP: Operation code Sz: Size (B: byte, W: word, or L: longword) SRC: Source DEST: Destination Rm: Source register Rn: Destination register imm: Immediate data disp: Displacement*1 mmmm: Source register nnnn: Destination register 0000: R0 0001: R1 1111: R15 iiii: Immediate data dddd: Displacement Direction of transfer Memory operand Flag bits in the SR Logical AND of each bit Logical OR of each bit Exclusive OR of each bit Logical NOT of each bit n-bit left shift n-bit right shift Value when no wait states are inserted*2 Value of T bit after instruction is executed. An em-dash (--) in the column means no change. Instruction code MSB LSB Operation , (xx) M/Q/T & | ^ ~ < Execution cycles T bit -- -- Notes: *1. Depending on the operand size, displacement is scaled x1, x2, or x4. For details, see the SH-2E Programming Manual. *2. Instruction execution cycles: The execution cycles shown in the table are minimums. The actual number of cycles may be increased when (1) contention occurs between instruction fetches and data access, or (2) when the destination register of the load instruction (memory register) and the register used by the next instruction are the same. Rev.2.0, 07/03, page 46 of 960 Table 2.12 Data Transfer Instructions Execution Cycles 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 T Bit -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- Instruction MOV #imm,Rn Instruction Code 1110nnnniiiiiiii 1001nnnndddddddd 1101nnnndddddddd 0110nnnnmmmm0011 0010nnnnmmmm0000 0010nnnnmmmm0001 0010nnnnmmmm0010 0110nnnnmmmm0000 0110nnnnmmmm0001 0110nnnnmmmm0010 0010nnnnmmmm0100 0010nnnnmmmm0101 0010nnnnmmmm0110 0110nnnnmmmm0100 0110nnnnmmmm0101 0110nnnnmmmm0110 10000000nnnndddd 10000001nnnndddd 0001nnnnmmmmdddd 10000100mmmmdddd 10000101mmmmdddd 0101nnnnmmmmdddd 0000nnnnmmmm0100 Operation #imm Sign extension Rn (disp x 2 + PC) Sign extension Rn (disp x 4 + PC) Rn Rm Rn Rm (Rn) Rm (Rn) Rm (Rn) (Rm) Sign extension Rn (Rm) Sign extension Rn (Rm) Rn Rn-1 Rn, Rm (Rn) Rn-2 Rn, Rm (Rn) Rn-4 Rn, Rm (Rn) (Rm) Sign extension Rn,Rm + 1 Rm (Rm) Sign extension Rn,Rm + 2 Rm (Rm) Rn,Rm + 4 Rm R0 (disp + Rn) R0 (disp x 2 + Rn) Rm (disp x 4 + Rn) (disp + Rm) Sign extension R0 (disp x 2 + Rm) Sign extension R0 (disp x 4 + Rm) Rn Rm (R0 + Rn) MOV.W @(disp,PC),Rn MOV.L @(disp,PC),Rn MOV Rm,Rn MOV.B Rm,@Rn MOV.W Rm,@Rn MOV.L Rm,@Rn MOV.B @Rm,Rn MOV.W @Rm,Rn MOV.L @Rm,Rn MOV.B Rm,@-Rn MOV.W Rm,@-Rn MOV.L Rm,@-Rn MOV.B @Rm+,Rn MOV.W @Rm+,Rn MOV.L @Rm+,Rn MOV.B R0,@(disp,Rn) MOV.W R0,@(disp,Rn) MOV.L Rm,@(disp,Rn) MOV.B @(disp,Rm),R0 MOV.W @(disp,Rm),R0 MOV.L @(disp,Rm),Rn MOV.B Rm,@(R0,Rn) Rev.2.0, 07/03, page 47 of 960 Table 2.12 Data Transfer Instructions (cont) Execution Cycles 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 T Bit -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- Instruction MOV.W MOV.L MOV.B MOV.W MOV.L MOV.B MOV.W MOV.L MOV.B MOV.W MOV.L MOVA MOVT Rm,@(R0,Rn) Rm,@(R0,Rn) @(R0,Rm),Rn @(R0,Rm),Rn @(R0,Rm),Rn Instruction Code 0000nnnnmmmm0101 0000nnnnmmmm0110 0000nnnnmmmm1100 0000nnnnmmmm1101 0000nnnnmmmm1110 Operation Rm (R0 + Rn) Rm (R0 + Rn) (R0 + Rm) Sign extension Rn (R0 + Rm) Sign extension Rn (R0 + Rm) Rn R0 (disp + GBR) R0 (disp x 2 + GBR) R0 (disp x 4 + GBR) (disp + GBR) Sign extension R0 (disp x 2 + GBR) Sign extension R0 (disp x 4 + GBR) R0 disp x 4 + PC R0 T Rn Rm Swap bottom two bytes Rn Rm Swap two consecutive words Rn Rm: Middle 32 bits of Rn Rn R0,@(disp,GBR) 11000000dddddddd R0,@(disp,GBR) 11000001dddddddd R0,@(disp,GBR) 11000010dddddddd @(disp,GBR),R0 11000100dddddddd @(disp,GBR),R0 11000101dddddddd @(disp,GBR),R0 11000110dddddddd @(disp,PC),R0 Rn 11000111dddddddd 0000nnnn00101001 0110nnnnmmmm1000 0110nnnnmmmm1001 0010nnnnmmmm1101 SWAP.B Rm,Rn SWAP.W Rm,Rn XTRCT Rm,Rn Rev.2.0, 07/03, page 48 of 960 Table 2.13 Arithmetic Operation Instructions Execution Cycles 1 1 1 1 1 1 Instruction ADD ADD ADDC ADDV Rm,Rn #imm,Rn Rm,Rn Rm,Rn Instruction Code 0011nnnnmmmm1100 0111nnnniiiiiiii 0011nnnnmmmm1110 0011nnnnmmmm1111 10001000iiiiiiii 0011nnnnmmmm0000 0011nnnnmmmm0010 0011nnnnmmmm0011 0011nnnnmmmm0110 0011nnnnmmmm0111 0100nnnn00010101 0100nnnn00010001 0010nnnnmmmm1100 Operation Rn + Rm Rn Rn + imm Rn Rn + Rm + T Rn, Carry T Rn + Rm Rn, Overflow T If R0 = imm, 1 T If Rn = Rm, 1 T T Bit -- -- Carry Overflow Comparison result Comparison result Comparison result Comparison result Comparison result Comparison result Comparison result Comparison result Comparison result Calculation result Calculation result 0 CMP/EQ #imm,R0 CMP/EQ Rm,Rn CMP/HS Rm,Rn CMP/GE Rm,Rn CMP/HI Rm,Rn CMP/GT Rm,Rn CMP/PL Rn CMP/PZ Rn CMP/STR Rm,Rn If Rn=Rm with unsigned 1 data, 1 T If Rn = Rm with signed data, 1 T If Rn > Rm with unsigned data, 1 T If Rn > Rm with signed data, 1 T If Rn > 0, 1 T If Rn = 0, 1 T If Rn and Rm have anequivalent byte, 1T Single-step division (Rn / Rm) MSB of Rn Q, MSB of Rm M, M ^ Q T 0 M/Q/T 1 1 1 1 1 1 DIV1 DIV0S DIV0U Rm,Rn Rm,Rn 0011nnnnmmmm0100 0010nnnnmmmm0111 0000000000011001 1 1 1 Rev.2.0, 07/03, page 49 of 960 Table 2.13 Arithmetic Operation Instructions (cont) Execution Cycles 2 to 4* Instruction DMULS.L Rm,Rn Instruction Code 0011nnnnmmmm1101 Operation Signed operation of Rn x Rm MACH, MACL 32 x 32 64 bits T Bit -- DMULU.L Rm,Rn 0011nnnnmmmm0101 2 to 4* Unsigned operation of Rn x Rm MACH, MACL 32 x 32 64 bits Rn - 1 Rn, when Rn 1 is 0, 1 T. When Rn is nonzero, 0 T Byte in Rm is signextended Rn Word in Rm is signextended Rn Byte in Rm is zeroextended Rn Word in Rm is zeroextended Rn Signed operation of (Rn) x (Rm) + MAC MAC 32 x 32 + 64 64 bits Signed operation of (Rn) x (Rm) + MAC MAC 16 x 16 + 64 64 bits Rn x Rm MACL, 32 x 32 32 bits Signed operation of Rn x Rm MACL 16 x 16 32 bits Unsigned operation of Rn x Rm MACL 16 x 16 32 bits 0 - Rm Rn 0 - Rm - T Rn, Borrow T 1 1 1 1 3/(2 to 4)* -- DT Rn 0100nnnn00010000 Comparison result -- -- -- -- -- EXTS.B Rm,Rn EXTS.W Rm,Rn EXTU.B Rm,Rn EXTU.W Rm,Rn MAC.L 0110nnnnmmmm1110 0110nnnnmmmm1111 0110nnnnmmmm1100 0110nnnnmmmm1101 @Rm+,@Rn+ 0000nnnnmmmm1111 MAC.W @Rm+,@Rn+ 0100nnnnmmmm1111 3/(2)* -- MUL.L Rm,Rn 0000nnnnmmmm0111 0010nnnnmmmm1111 2 to 4* 1 to 3* -- -- MULS.W Rm,Rn MULU.W Rm,Rn 0010nnnnmmmm1110 1 to 3* -- NEG NEGC Rm,Rn Rm,Rn 0110nnnnmmmm1011 0110nnnnmmmm1010 1 1 -- Borrow Rev.2.0, 07/03, page 50 of 960 Table 2.13 Arithmetic Operation Instructions (cont) Execution Cycles 1 1 1 Instruction SUB SUBC SUBV Rm,Rn Rm,Rn Rm,Rn Instruction Code 0011nnnnmmmm1000 0011nnnnmmmm1010 0011nnnnmmmm1011 Operation Rn - Rm Rn Rn - Rm - T Rn, Borrow T Rn - Rm Rn, Underflow T T Bit -- Borrow Overflow Note: * The normal minimum number of execution cycles. (The number in parentheses is the number of cycles when there is contention with following instructions.) Table 2.14 Logic Operation Instructions Execution Cycles 1 1 3 1 1 1 3 4 1 1 Instruction AND AND Rm,Rn #imm,R0 Instruction Code 0010nnnnmmmm1001 11001001iiiiiiii 11001101iiiiiiii 0110nnnnmmmm0111 0010nnnnmmmm1011 11001011iiiiiiii 11001111iiiiiiii 0100nnnn00011011 0010nnnnmmmm1000 11001000iiiiiiii 11001100iiiiiiii 0010nnnnmmmm1010 11001010iiiiiiii 11001110iiiiiiii Operation Rn & Rm Rn R0 & imm R0 (R0 + GBR) & imm (R0 + GBR) ~Rm Rn Rn | Rm Rn R0 | imm R0 (R0 + GBR) | imm (R0 + GBR) If (Rn) is 0, 1 T; 1 MSB of (Rn) Rn & Rm; if the result is 0, 1 T R0 & imm; if the result is 0, 1 T T Bit -- -- -- -- -- -- -- Test result Test result Test result Test result -- -- -- AND.B #imm,@(R0,GBR) NOT OR OR OR.B Rm,Rn Rm,Rn #imm,R0 #imm,@(R0,GBR) TAS.B @Rn TST TST Rm,Rn #imm,R0 TST.B #imm,@(R0,GBR) XOR XOR Rm,Rn #imm,R0 (R0 + GBR) & imm; if the 3 result is 0, 1 T Rn ^ Rm Rn R0 ^ imm R0 (R0 + GBR) ^ imm (R0 + GBR) 1 1 3 XOR.B #imm,@(R0,GBR) Rev.2.0, 07/03, page 51 of 960 Table 2.15 Shift Instructions Execution Cycles 1 1 1 1 1 1 1 1 1 1 1 1 1 1 Instruction ROTL ROTR ROTCL ROTCR SHAL SHAR SHLL SHLR SHLL2 SHLR2 SHLL8 SHLR8 Rn Rn Rn Rn Rn Rn Rn Rn Rn Rn Rn Rn Instruction Code 0100nnnn00000100 0100nnnn00000101 0100nnnn00100100 0100nnnn00100101 0100nnnn00100000 0100nnnn00100001 0100nnnn00000000 0100nnnn00000001 0100nnnn00001000 0100nnnn00001001 0100nnnn00011000 0100nnnn00011001 0100nnnn00101000 0100nnnn00101001 Operation T Rn MSB LSB Rn T T Rn T T Rn T T Rn 0 MSB Rn T T Rn 0 0 Rn T Rn<<2 Rn Rn>>2 Rn Rn<<8 Rn Rn>>8 Rn Rn<<16 Rn Rn>>16 Rn T Bit MSB LSB MSB LSB MSB LSB MSB LSB -- -- -- -- -- -- SHLL16 Rn SHLR16 Rn Rev.2.0, 07/03, page 52 of 960 Table 2.16 Branch Instructions Execution Cycles 3/1* 2/1* 3/1* 2/1* 2 2 2 2 2 2 2 Instruction BF label Instruction Code 10001011dddddddd 10001111dddddddd 10001001dddddddd 10001101dddddddd 1010dddddddddddd 0000mmmm00100011 1011dddddddddddd 0000mmmm00000011 0100mmmm00101011 0100mmmm00001011 0000000000001011 Operation If T = 0, disp x 2 + PC PC; if T = 1, nop Delayed branch, if T = 0, disp x 2 + PC PC; if T = 1, nop If T = 1, disp x 2 + PC PC; if T = 0, nop Delayed branch, if T = 1, disp x 2 + PC PC; if T = 0, nop Delayed branch, disp x 2 + PC PC Delayed branch, Rm + PC PC Delayed branch, PC PR, disp x 2 + PC PC Delayed branch, PC PR, Rm+PC PC Delayed branch, Rm PC Delayed branch, PC PR, Rm PC Delayed branch, PR PC T Bit -- -- -- -- -- -- -- -- -- -- -- BF/S label BT label BT/S label BRA label BRAF Rm BSR label BSRF Rm JMP JSR RTS @Rm @Rm Note: * One state when the program does not branch. Rev.2.0, 07/03, page 53 of 960 Table 2.17 System Control Instructions Execution Cycles 1 1 1 1 1 3 3 3 1 1 1 Instruction CLRT CLRMAC LDC LDC LDC Rm,SR Rm,GBR Rm,VBR Instruction Code 0000000000001000 0000000000101000 0100mmmm00001110 0100mmmm00011110 0100mmmm00101110 0100mmmm00000111 0100mmmm00010111 0100mmmm00100111 0100mmmm00001010 0100mmmm00011010 0100mmmm00101010 0100mmmm00000110 0100mmmm00010110 0100mmmm00100110 0000000000001001 0000000000101011 0000000000011000 0000000000011011 Operation 0T 0 MACH, MACL Rm SR Rm GBR Rm VBR (Rm) SR, Rm + 4 Rm (Rm) GBR, Rm + 4 Rm (Rm) VBR, Rm + 4 Rm Rm MACH Rm MACL Rm PR (Rm) MACL, Rm + 4 Rm (Rm) PR, Rm + 4 Rm No operation Delayed branch, stack area PC/SR 1T Sleep SR Rn GBR Rn VBR Rn Rn - 4 Rn, SR (Rn) Rn - 4 Rn, GBR (Rn) Rn - 4 Rn, BR (Rn) MACH Rn MACL Rn PR Rn T Bit 0 -- LSB -- -- LSB -- -- -- -- -- -- -- -- -- -- 1 -- -- -- -- -- -- -- -- -- -- LDC.L @Rm+,SR LDC.L @Rm+,GBR LDC.L @Rm+,VBR LDS LDS LDS Rm,MACH Rm,MACL Rm,PR LDS.L @Rm+,MACH LDS.L @Rm+,MACL LDS.L @Rm+,PR NOP RTE SETT SLEEP STC STC STC STC.L STC.L STC.L STS STS STS SR,Rn GBR,Rn VBR,Rn SR,@-Rn GBR,@-Rn VBR,@-Rn MACH,Rn MACL,Rn PR,Rn (Rm) MACH, Rm + 4 Rm 1 1 1 1 4 1 3* 1 1 1 2 2 2 1 1 1 0000nnnn00000010 0000nnnn00010010 0000nnnn00100010 0100nnnn00000011 0100nnnn00010011 0100nnnn00100011 0000nnnn00001010 0000nnnn00011010 0000nnnn00101010 Rev.2.0, 07/03, page 54 of 960 Table 2.17 System Control Instructions (cont) Execution Cycles 1 1 1 Instruction STS.L STS.L STS.L TRAPA MACH,@-Rn MACL,@-Rn PR,@-Rn #imm Instruction Code 0100nnnn00000010 0100nnnn00010010 0100nnnn00100010 11000011iiiiiiii Operation Rn - 4 Rn, MACH (Rn) Rn - 4 Rn, MACL (Rn) Rn - 4 Rn, PR (Rn) T Bit -- -- -- -- PC/SR stack area, (imm x 4 8 + VBR) PC Note: * The number of execution cycles before the chip enters sleep mode: The execution cycles shown in the table are minimums. The actual number of cycles may be increased when (1) contention occurs between instruction fetches and data access, or (2) when the destination register of the load instruction (memory register) and the register used by the next instruction are the same. Rev.2.0, 07/03, page 55 of 960 Table 2.18 Floating-Point Instructions Execution Cycles T Bit 1 1 -- -- Comparison result Comparison result -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- Instruction FABS FADD FRn FRm,FRn Instruction Code Operation 1111nnnn01011101 |FRn| FRn 1111nnnnmmmm0000 FRn + FRm FRn FCMP/EQ FRm,FRn FCMP/GT FRm,FRn FDIV FLDI0 FLDI1 FLDS FLOAT FMAC FMOV FRm,FRn FRn FRn FRm,FPUL FPUL,FRn FR0,FRm,FRn FRm, FRn 1111nnnnmmmm0100 (FRn = FRm)? 1:0 T 1 1111nnnnmmmm0101 (FRn > FRm)? 1:0 T 1 1111nnnnmmmm0011 FRn/FRm FRn 1111nnnn10001101 0x00000000 FRn 1111nnnn10011101 0x3F800000 FRn 1111mmmm00011101 FRm FPUL 1111nnnn00101101 (float) FPUL FRn 1111nnnnmmmm1110 FR0 x FRm + FRn FRn 1111nnnnmmmm1100 FRm FRn 1111nnnnmmmm0110 (R0 + Rm) FRn 1111nnnnmmmm1001 (Rm) FRn, Rm+ = 4 1111nnnnmmmm1000 (Rm) FRn 1111nnnnmmmm0111 FRm (R0 + Rn) 1111nnnnmmmm1011 Rn- = 4, FRm (Rn) 1111nnnnmmmm1010 FRm (Rn) 1111nnnnmmmm0010 FRn x FRm FRn 1111nnnn01001101 -FRn FRn 1111nnnn00001101 FPUL FRn 1111nnnnmmmm0001 FRn - FRm FRn 1111mmmm00111101 (long) FRm FPUL 13 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 FMOV.S @(R0,Rm),FRn FMOV.S @Rm+,FRn FMOV.S @Rm,FRn FMOV.S FRm,@(R0,Rn) FMOV.S FRm,@-Rn FMOV.S FRm,@Rn FMUL FNEG FSTS FSUB FTRC FRm,FRn FRn FPUL,FRn FRm,FRn FRm,FPUL Rev.2.0, 07/03, page 56 of 960 Table 2.19 FPU-Related CPU Instructions Execution Cycles 1 1 1 1 1 1 1 1 Instruction LDS LDS LDS.L LDS.L STS STS STS.L STS.L Rm,FPSCR Rm,FPUL @Rm+, FPSCR @Rm+, FPUL FPSCR, Rn FPUL,Rn FPSCR,@-Rn FPUL,@-Rn Instruction Code Operation T Bit -- -- -- -- -- -- -- -- 0100mmmm01101010 Rm FPSCR 0100mmmm01011010 Rm FPUL 0100mmmm01100110 @Rm FPSCR, Rm+ = 4 0100mmmm01010110 @Rm FPUL, Rm+ = 4 0000nnnn01101010 FPSCR Rn 0000nnnn01011010 FPUL Rn 0100nnnn01100010 Rn- = 4, FPCSR @Rn 0100nnnn01010010 Rn- = 4, FPUL @Rn 2.5 2.5.1 Processing States State Transitions The CPU has five processing states: power-on reset, exception processing, bus release, program execution and power-down. Figure 2.8 shows the transitions between the states. Rev.2.0, 07/03, page 57 of 960 From any state =0 when =1 and Power-on reset state =0 =1 =1 When an interrupt source or DMA address error occurs Exception processing state Bus request cleared Bus request generated Bus release state Exception processing source occurs Bus request cleared NMI interrupt source occurs Exception processing ends Bus request generated Bus request generated Bus request cleared Program execution state SBY bit set for SLEEP instruction SBY bit cleared for SLEEP instruction Sleep mode Software standby mode Hardware standby mode Power-down state From any state when = 0 and =0 Note: An internal reset due to the WDT causes a transition from the program execution state or sleep mode to the exception processing state. Figure 2.8 Transitions between Processing States Rev.2.0, 07/03, page 58 of 960 Power-On Reset State: The CPU resets in the reset state. When the HSTBY pin is driven high and the RES pin level goes low, the power-on reset state is entered. Exception Processing State: The exception processing state is a transient state that occurs when exception processing sources such as resets or interrupts alter the CPU's processing state flow. For a reset, the initial values of the program counter (PC) (execution start address) and stack pointer (SP) are fetched from the exception processing vector table and stored; the CPU then branches to the execution start address and execution of the program begins. For an interrupt, the stack pointer (SP) is accessed and the program counter (PC) and status register (SR) are saved to the stack area. The exception service routine start address is fetched from the exception processing vector table; the CPU then branches to that address and the program starts executing, thereby entering the program execution state. Program Execution State: In the program execution state, the CPU sequentially executes the program. Power-Down State: In the power-down state, the CPU operation halts and power consumption declines. The SLEEP instruction places the CPU in the sleep mode or the software standby mode. If the HSTBY pin is driven low when the RES pin is low, the CPU will enter the hardware standby mode. Bus Release State: In the bus release state, the CPU releases access rights to the bus to the device that has requested them. Rev.2.0, 07/03, page 59 of 960 Rev.2.0, 07/03, page 60 of 960 Section 3 Floating-Point Unit (FPU) 3.1 Overview The SH7055SF has an on-chip floating-point unit (FPU), The FPU's register configuration is shown in figure 3.1. Floating-point registers 31 FR0 FR1 FR2 FR3 FR4 FR5 FR6 FR7 FR8 FR9 FR10 FR11 FR12 FR13 FR14 FR15 0 FR0 functions as the index register for the FMAC instruction. Floating-point system registers 31 FPUL 31 FPSCR 0 0 Floating-point communication register Specifies buffer as communication register between CPU and FPU*. Floating-point status/control register Indicates status/control information relating to FPU exceptions*. Note: * For details, see section 3.2, Floating-Point Registers and Floating-Point System Registers. Figure 3.1 Overview of Register Configuration (Floating-Point Registers and Floating-Point System Registers) Rev.2.0, 07/03, page 61 of 960 3.2 3.2.1 Floating-Point Registers and Floating-Point System Registers Floating-Point Register File The SH7055SF has sixteen 32-bit single-precision floating-point registers. Register specifications are always made as 4 bits. In assembly language, the floating-point registers are specified as FR0, FR1, FR2, and so on. FR0 functions as the index register for the FMAC instruction. 3.2.2 Floating-Point Communication Register (FPUL) Information for transfer between the FPU and the CPU is transferred via the FPUL communication register, which resembles MACL and MACH in the integer unit. The SH7055SF is provided with this communication register since the integer and floating-point formats are different. The 32-bit FPUL is a system register, and is accessed by the CPU by means of LDS and STS instructions. 3.2.3 Floating-Point Status/Control Register (FPSCR) The SH7055SF has a floating-point status/control register (FPSCR) that functions as a system register accessed by means of LDS and STS instructions (figure 3.2). FPSCR can be written to by a user program. This register is part of the process context, and must be saved when the context is switched. It may also be necessary to save this register when a procedure call is made. FPSCR is a 32-bit register that controls the storage of detailed information relating to the rounding mode, asymptotic underflow (denormalized numbers), and FPU exceptions. The module stop bit that disables the FPU itself is provided in the module standby control register (MSTCR). For details, see section 24, Power-Down State. After a reset start, the FPU is enabled. Table 3.1 shows the flags corresponding the five kinds of FPU exception. A sixth flag is also provided as an FPU error flag that indicates an floating-point unit error state not covered by the other five flags. Table 3.1 Flag E V Z O U I Floating-Point Exception Flags Meaning FPU error Invalid operation Division by zero Overflow (value not expressed) Underflow (value not expressed) Inexact (result not expressed) Support in SH7055SF -- Yes Yes -- -- -- Rev.2.0, 07/03, page 62 of 960 The bits in the cause field indicate the exception cause for the instruction executing at the time. The cause bits are modified by a floating-point instruction. These bits are set to 1 or cleared to 0 according to whether or not an exception state occurred during execution of a single instruction. The bits in the enable field specify the kinds of exception to be enabled, allowing the flow to be changed to exception processing. If the cause bit corresponding to an enable bit is set by the currently executing instruction, an exception occurs. The bits in the flag field are used to keep a tally of all exceptions that occur during a series of instructions. Once one of these bits is set by an instruction, it is not reset by a subsequent instruction. The bits in this field can only be reset by the explicit execution of a store operation on FPSCR. Rev.2.0, 07/03, page 63 of 960 31 Reserved 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Cause field Enable field Flag field DN CE CV CZ CO CU CI EV EZ EO EU EI FV FZ FO FU FI RM DN: Denormalized bit In the SH7055SF this bit is always set to 1, and the source or destination operand of a denormalized number is 0. This bit cannot be modified even by an LDS instruction. Invalid operation cause bit When 1: Indicates that an invalid operation exception occurred during execution of the current instruction. When 0: Indicates that an invalid operation exception has not occurred. Division-by-zero cause bit When 1: Indicates that a division-by-zero exception occurred during execution of the current instruction. When 0: Indicates that a division-by-zero exception has not occurred. Invalid operation exception enable When 1: Enables invalid operation exception generation. When 0: An invalid operation exception is not generated, and a qNAN is returned as the result. Division-by-zero exception enable When 1: Enables exception generation due to division-by-zero during execution of the current instruction. When 0: A division-by-zero exception is not generated, and infinity with the sign (+ or -) of the current expression is returned as the result. CV: CZ: EV: EZ: FV: Invalid operation exception flag bit When 1: Indicates that an invalid operation exception occurred during instruction execution. When 0: Indicates that an invalid operation exception has not occurred. FZ: Division-by-zero exception flag bit When 1: Indicates that a division-by-zero exception occurred during instruction execution. When 0: Indicates that a division-by-zero exception has not occurred. RM: Rounding bit. In the SH7055SF, the value of these bits is always 01, meaning that rounding to zero (RZ mode) is being used. These bits cannot be modified even by an LDS instruction. In the SH7055SF, the cause field EOUI bits (CE, CO, CU, and CI), enable field OUI bits (EO, EU, and EI), and flag field OUI bits (FO, FU, and FI), and the reserved area, are preset to 0, and cannot be modified even by using an LDS instruction. Figure 3.2 Floating-Point Status/Control Register Rev.2.0, 07/03, page 64 of 960 3.3 3.3.1 Floating-Point Format Floating-Point Format The SH7055SF supports single-precision floating-point operations, and fully complies with the IEEE754 floating-point standard. A floating-point number consists of the following three fields: * Sign (s) * Exponent (e) * Fraction (f) The exponent is expressed in biased form, as follows: e = E + bias The range of unbiased exponent E is Emin - 1 to Emax + 1. The two values Emin - 1 and Emax + 1 are distinguished as follows. Emin - 1 indicates zero (both positive and negative sign) and a denormalized number, and Emax + 1 indicates positive or negative infinity or a non-number (NaN). In a single-precision operation, the bias value is 127, Emin is -126, and Emax is 127. 31 30 s e 23 22 f 0 Figure 3.3 Floating-Point Number Format Floating-point number value v is determined as follows: If E = Emax + 1 and f! = 0, v is a non-number (NaN) irrespective of sign s s If E = Emax + 1 and f = 0, v = (-1) (infinity) [positive or negative infinity] sE If Emin <= E <= Emax , v = (-1) 2 (1.f) [normalized number] s Emin If E = Emin - 1 and f! = 0, v = (-1) 2 (0.f) [denormalized number] s If E = Emin - 1 and f = 0, v = (-1) 0 [positive or negative zero] Rev.2.0, 07/03, page 65 of 960 3.3.2 Non-Numbers (NaN) With non-number (NaN) representation in a single-precision operation value, at least one of bits 22 to 0 is set. If bit 22 is set, this indicates a signaling NaN (sNaN). If bit 22 is reset, the value is a quiet NaN (qNaN). The bit pattern of a non-number (NaN) is shown in the figure below. Bit N in the figure is set for a signaling NaN and reset for a quiet NaN. x indicates a don't care bit (with the proviso that at least one of bits 22 to 0 is set). In a non-number (NaN), the sign bit is a don't care bit. 31 30 x 11111111 23 22 Nxxxxxxxxxxxxxxxxxxxxxx 0 N = 1: sNaN N = 0: qNaN Figure 3.4 NaN Bit Pattern If a non-number (sNaN) is input in an operation that generates a floating-point value: * When the EV bit in the FPSCR register is reset, the operation result (output) is a quiet NaN (qNaN). * When the EV bit in the FPSCR register is set, an invalid operation exception will be generated. In this case, the contents of the operation destination register do not change. If a quiet NaN is input in an operation that generates a floating-point value, and a signaling NaN has not been input in that operation, the output will always be a quiet NaN irrespective of the setting of the EV bit in the FPSCR register. An exception will not be generated in this case. Refer to the SH-2E Programming Manual for details of floating-point operations when a nonnumber (NaN) is input. 3.3.3 Denormalized Number Values For a denormalized number floating-point value, the biased exponent is expressed as 0, the fraction as a non-zero value, and the hidden bit as 0. In the SH7055SF's floating-point unit, a denormalized number (operand source or operation result) is always flushed to 0 in a floatingpoint operation that generates a value (an operation other than copy). Rev.2.0, 07/03, page 66 of 960 3.3.4 Other Special Values Floating-point value representations include the seven different kinds of special values shown in table 3.2. Table 3.2 Value +0.0 -0.0 Denormalized number +INF -INF qNaN (quiet NaN) sNaN (signaling NaN) Representation of Special Values in Single-Precision Floating-Point Operations Specified by IEEE754 Standard Representation 0x00000000 0x80000000 As described in 3.3.3, Denormalized Number Values 0x7F800000 0xFF800000 As described in 3.3.2, Non-Numbers (NaN) As described in 3.3.2, Non-Numbers (NaN) Rev.2.0, 07/03, page 67 of 960 3.4 3.4.1 Floating-Point Exception Model Enable State Exceptions Invalid operation and division-by-zero exceptions are both placed in the enable state by setting the enable bit. All exceptions generated by the FPU are mapped as the same exception event. The meaning of a particular exception is determined by software by reading system register FPSCR and analyzing the information held there. 3.4.2 Disable State Exceptions If the EV enable bit is not set, a qNaN will be generated as the result of an invalid operation (except for FCMP and FTRC). If the EZ enable bit is not set, division-by-zero will return infinity with the sign (+ or -) of the current expression. Overflow will generate a finite number which is the largest value that can be expressed by an absolute value in the format, with the correct sign. Underflow will generate zero with the correct sign. If the operation result is inexact, the destination register will store that inexact result. 3.4.3 FPU Exception Event and Code All FPU exceptions have a vector table address offset in address H'00000034 as the same general exception event; that is, an FPU exception. 3.4.4 Floating-Point Data Arrangement in Memory Single-precision floating-point data is located in memory at a 4-byte boundary; that is, it is arranged in the same form as an SH7055SF long integer. 3.4.5 Arithmetic Operations Involving Special Operands All arithmetic operations involving special operands (qNaN, sNaN, +INF, -INF, +0, -0) comply with the specifications of the IEEE754 standard. Refer to the SH-2E Programming Manual for details. Rev.2.0, 07/03, page 68 of 960 3.5 Synchronization with CPU Synchronization with CPU: Floating-point instructions and CPU instructions are executed in turn, according to their order in the program, but in some cases operations may not be completed in the program order due to a difference in execution cycles. When a floating-point instruction accesses only FPU resources, there is no need for synchronization with the CPU, and a CPU instruction following an FPU instruction can finish its operation before completion of the FPU operation. Consequently, in an optimized program, it is possible to effectively conceal the execution cycle of a floating-point instruction that requires a long execution cycle, such as a divide instruction. On the other hand, a floating-point instruction that accesses CPU resources, such as a compare instruction, must be synchronized to ensure that the program order is observed. Floating-Point Instructions That Require Synchronization: Load, store, and compare instructions, and instructions that access the FPUL or FPSCR register, must be synchronized because they access CPU resources. Load and store instructions access a general register. Postincrement load and pre-decrement store instructions change the contents of a general register. A compare instruction modifies the T bit. An FPUL or FPSCR access instruction references or changes the contents of the FPUL or FPSCR register. These references and changes must all be synchronized with the CPU. 3.6 Usage Notes 1. When using the FPU (using FPU instructions or FPU-related CPU instructions) a. Limitations on using the BT and BF instructions on the SH7055F are abolished. The BT and BF instructions can be used on the SH7055SF. b. The branch destination of TRAP instruction and interrupt/exception handling must be located at a 4n address. In this case, do not place an FPU instruction or FPU-related CPU instruction at address 4n or 4n+2. 2. When not using the FPU (not using FPU instructions or FPU-related CPU instructions) After a power-on reset, the FPU should be placed in the module standby state until a DMAC or AUD bus cycle is generated. Specifically, write 1 to bit 1 in the module standby control register. This operation is also effective in reducing current dissipation. When the FPU enters the module standby state, any subsequent FPU instruction or FPUrelated CPU instruction will be subjected to exception handling as an illegal instruction. 3. Restrictions of the FADD and FSUB instructions In this FPU, values calculated by the following two arithmetic operations with a special operand have a sign which is different from values' expected in the IEEE Standard 754. 1) FADD FRm, FRn FRm = -INF(0xFF80000) FRn = MAX(0x7F7FFFFF) Rev.2.0, 07/03, page 69 of 960 At this time, + INF (0x7F800000) is generated as a result to the expected value -INF (0xFF800000) in the IEEE754. 2) FSUB FRm, FRn FRm = -INF(0xFF80000) FRn = MAX(0x7F7FFFFF) At this time, + INF (0x7F800000) is generated as a result to the expected value -INF (0xFF800000) in the IEEE754. Rev.2.0, 07/03, page 70 of 960 Section 4 Operating Modes 4.1 Operating Mode Selection The SH7055SF has five operating modes that are selected by pins MD2 to MD0 and FWE. The mode setting pins should not be changed during operation of the SH7055SF, and only the setting combinations shown in table 4.1 should be used. The PVCC1 power supply voltage must be within the range shown in table 4.1. Table 4.1 Operating Mode Selection Area 0 Bus Width 8 bits 16 bits Enabled MCU single-chip mode Boot mode Enabled Enabled Set by BCR1 -- Set by BCR1 -- User program mode Enabled Set by BCR1 -- User boot mode Enabled Set by BCR1 -- Programmer mode -- -- 5.0 V 0.5 V 3.3 V 0.3 V 5.0 V 0.5 V 3.3 V 0.3 V 5.0 V 0.5 V 3.3 V 0.3 V 5.0 V 0.5 V 3.3 V 0.3 V Pin Settings Operating Mode No. FWE MD2 MD1 MD0 Mode 0 Mode 1 Mode 2 Mode 3 Mode 4 Mode 5 Mode 6 Mode 7 Mode 8 Mode 9 -- 0 0 0 0 1 1 1 1 1 1 0/1 1 1 1 1 1 1 1 1 0 0 0 0 0 1 1 0 0 1 1 0 0 1 0 1 0 1 0 1 0 1 1 1 1 Mode Name MCU expanded mode On-Chip ROM Disabled PVCC1 Voltage 3.3 V 0.3 V There are two MCU operating modes: MCU single-chip mode and MCU expanded mode. Modes in which the flash memory can be programmed are boot mode, user boot mode and user program mode (the two on-board programming modes) and programmer mode in which programming is performed with an EPROM programmer (a type which supports programming of this device). For details, see section 22, ROM. Rev.2.0, 07/03, page 71 of 960 Rev.2.0, 07/03, page 72 of 960 Section 5 Clock Pulse Generator (CPG) 5.1 Overview The clock pulse generator (CPG) supplies clock pulses inside the SH7055SF chip and to external devices. The SH7055SF CPG consists of an oscillator circuit and a PLL multiplier circuit. There are two methods of generating a clock with the CPG: by connecting a crystal resonator, or by inputting an external clock. The oscillator circuit oscillates at the same frequency as the input clock. A chip operating frequency of 4 times the oscillator frequency is generated by the PLL multiplier circuit. The CPG is halted in software standby mode and hardware standby mode. 5.1.1 Block Diagram A block diagram of the clock pulse generator is shown in figure 5.1. CPG EXTAL Oscillator circuit XTAL PLLVcc PLLVss PLLCAP PLL multiplier circuit CK (system clock) fx4 Internal clock Figure 5.1 Block Diagram of Clock Pulse Generator Rev.2.0, 07/03, page 73 of 960 5.1.2 Pin Configuration The pins relating to the clock pulse generator are shown in table 5.1. Table 5.1 Pin Name External clock Crystal System clock PLL power supply PLL ground PLL capacitance CPG Pins Abbreviation EXTAL XTAL CK PLLVCC PLLVSS PLLCAP I/O Input Input Output Input Input Input Description Crystal resonator or external clock input Crystal resonator connection System clock output PLL multiplier circuit power supply PLL multiplier circuit ground PLL multiplier circuit oscillation external capacitance pin 5.2 Frequency Ranges The input frequency and operating frequency ranges are shown in table 5.2. Table 5.2 Input Frequency and Operating Frequency PLL Multiplication Factor x4 Operating Frequency Range (MHz) 20-40 Input Frequency Range (MHz) 5-10 Note: Crystal resonator and external clock input For the chip operating frequency, a frequency of 4 times the input frequency (EXTAL pin) is generated as the internal clock () by the on-chip PLL circuit. The system clock (CK pin) output frequency is the same as that of the internal clock (). Some on-chip peripheral modules operate on a peripheral clock (P) obtained by dividing the internal clock () by 2. Figure 5.2 shows the relationship between the various clocks. As regards the system clock, since the input clock is multiplied by the PLL multiplier circuit, the phases of both clocks are not determined uniformly. Rev.2.0, 07/03, page 74 of 960 Input clock (EXTAL pin) System clock (CK pin) Internal clock () Peripheral clock (P) Figure 5.2 Input Clock and System Clock 5.3 Clock Source Clock pulses can be supplied from a connected crystal resonator or an external clock. 5.3.1 Connecting a Crystal Oscillator Circuit Configuration: Figure 5.3 shows an example of connecting a crystal resonator. Use the damping resistance (Rd) shown in table 5.3. An AT-cut parallel-resonance type crystal resonator should be used. Load capacitors (CL1, CL2) must be connected as shown in the figure. The clock pulses generated by the crystal resonator and internal oscillator are sent to the PLL multiplier circuit, where a multiplied frequency is selected and supplied inside the SH7055SF chip and to external devices. The crystal oscillator manufacturer should be consulted concerning the compatibility between the crystal oscillator and the chip. CL2 EXTAL CL1 XTAL Rd CL1 = CL2 = 18-22pF (recommended value) Figure 5.3 Connection of Crystal Oscillator (Example) Rev.2.0, 07/03, page 75 of 960 Table 5.3 Damping Resistance Values (Recommended Values) Frequency (MHz) Parameter Rd () 5 500 10 0 Crystal Oscillator: Figure 5.4 shows an equivalent circuit of the crystal oscillator. Use a crystal oscillator with the characteristics listed in table 5.4. L EXTAL C0 CL Rs XTAL Figure 5.4 Crystal Oscillator Equivalent Circuit Table 5.4 Crystal Oscillator Parameters (Recommended Values) Frequency (MHz) Parameter Rs max () C0 max (pF) 5 100 7 10 50 7 The crystal oscillator manufacturer should be consulted concerning the compatibility between the crystal oscillator and the chip. 5.3.2 External Clock Input Method An example of external clock input connection is shown in figure 5.5. When the XTAL pin is placed in the open state, the parasitic capacitance should be 10 pF or less. Even when an external clock is input, provide for a wait of at least the oscillation settling time when powering on or exiting standby mode in order to secure the PLL settling time. Rev.2.0, 07/03, page 76 of 960 Open XTAL External clock input EXTAL Figure 5.5 External Clock Input Method (Example) 5.4 Usage Notes Notes on Board Design: When connecting a crystal oscillator, observe the following precautions: * To prevent induction from interfering with correct oscillation, do not route any signal lines near the oscillator circuitry (figure 5.6). * When designing the board, place the crystal oscillator and its load capacitors as close as possible to the XTAL and EXTAL pins. Figure 5.6 shows the precautions regarding oscillator circuit system board design. Crossing of signal lines prohibited CL1 XTAL CL2 EXTAL Figure 5.6 Precautions for Oscillator Circuit System Board Design PLL Oscillation Power Supply: Separate PLLVCC and PLLVSS from the other VCC and VSS lines at the board power supply source, and be sure to insert bypass capacitors CPB and CB close to the pins. Rev.2.0, 07/03, page 77 of 960 PLLCAP Rp PLLVCC CPB PLLVSS VCC CB VSS Recommended values CPB, CB: 0.1F Rp: 200 Figure 5.7 Points for Caution in PLL Power Supply Connection PLLVSS PLLCAP PLLVCC XTAL VCC EXTAL VSS Figure 5.8 Actual Example of Board Design Rev.2.0, 07/03, page 78 of 960 Section 6 Exception Processing 6.1 6.1.1 Overview Types of Exception Processing and Priority Exception processing is started by four sources: resets, address errors, interrupts and instructions and have the priority shown in table 6.1. When several exception processing sources occur at once, they are processed according to the priority shown. Table 6.1 Exception Reset Types of Exception Processing and Priority Order Source Power-on reset Manual reset Priority High Address error CPU address error DMAC address error Instructions FPU exception Interrupt NMI User break H-UDI IRQ On-chip peripheral modules: * * * * * * * * * * * Direct memory access controller (DMAC) Advanced timer unit-II (ATU-II) Compare match timer 0 (CMT0) A/D converter channel 0 (A/D0) Compare match timer 1 (CMT1) A/D converter channel 1 (A/D1) A/D converter channel 2 (A/D2) Serial communication interface (SCI) Controller area network 0 (HCAN0) Watchdog timer (WDT) Controller area network 1 (HCAN 1) Low Rev.2.0, 07/03, page 79 of 960 Table 6.1 Exception Types of Exception Processing and Priority Order (cont) Source Priority High Instructions Trap instruction (TRAPA instruction) General illegal instructions (undefined code) Illegal slot instructions (undefined code placed directly after a delay branch Low 1 2 instruction* or instructions that rewrite the PC* ) Notes: *1. Delayed branch instructions: JMP, JSR, BRA, BSR, RTS, RTE, BF/S, BT/S, BSRF, BRAF. *2. Instructions that rewrite the PC: JMP, JSR, BRA, BSR, RTS, RTE, BT, BF, TRAPA, BF/S, BT/S, BSRF, BRAF. 6.1.2 Exception Processing Operations The exception processing sources are detected and begin processing according to the timing shown in table 6.2. Table 6.2 Exception Reset Timing of Exception Source Detection and Start of Exception Processing Source Power-on reset Manual reset Timing of Source Detection and Start of Processing Starts when the RES pin changes from low to high or when the WDT overflows. Starts when the WDT overflows. Detected when instruction is decoded and starts when the previous executing instruction finishes executing. Detected when instruction is decoded and starts when the previous executing instruction finishes executing. Trap instruction General illegal instructions Illegal slot instructions Floating point instructions Starts from the execution of a TRAPA instruction. Starts from the decoding of undefined code anytime except after a delayed branch instruction (delay slot). Starts from the decoding of undefined code placed in a delayed branch instruction (delay slot) or of instructions that rewrite the PC. Starts when a floating-point instruction causes an invalid operation exception (IEEE754 specification) or division-by-zero exception. Address error Interrupts Instructions Rev.2.0, 07/03, page 80 of 960 When exception processing starts, the CPU operates as follows: 1. Exception processing triggered by reset: The initial values of the program counter (PC) and stack pointer (SP) are fetched from the exception processing vector table (PC and SP are respectively the H'00000000 and H'00000004 addresses for power-on resets and the H'00000008 and H'0000000C addresses for manual resets). See section 6.1.3, Exception Processing Vector Table, for more information. H'00000000 is then written to the vector base register (VBR) and H'F (1111) is written to the interrupt mask bits (I3-I0) of the status register (SR). The program begins running from the PC address fetched from the exception processing vector table. 2. Exception processing triggered by address errors, interrupts and instructions: SR and PC are saved to the stack indicated by R15. For interrupt exception processing, the interrupt priority level is written to the SR's interrupt mask bits (I3-I0). For address error and instruction exception processing, the I3-I0 bits are not affected. The start address is then fetched from the exception processing vector table and the program begins running from that address. 6.1.3 Exception Processing Vector Table Before exception processing begins running, the exception processing vector table must be set in memory. The exception processing vector table stores the start addresses of exception service routines. (The reset exception processing table holds the initial values of PC and SP.) All exception sources are given different vector numbers and vector table address offsets, from which the vector table addresses are calculated. During exception processing, the start addresses of the exception service routines are fetched from the exception processing vector table, which is indicated by this vector table address. Table 6.3 shows the vector numbers and vector table address offsets. Table 6.4 shows how vector table addresses are calculated. Table 6.3 Exception Processing Vector Table Vector Numbers PC SP Manual reset PC SP General illegal instruction (Reserved by system) 0 1 2 3 4 5 Vector Table AddressOffset H'00000000-H'00000003 H'00000004-H'00000007 H'00000008-H'0000000B H'0000000C-H'0000000F H'00000010-H'00000013 H'00000014-H'00000017 Exception Sources Power-on reset Rev.2.0, 07/03, page 81 of 960 Table 6.3 Exception Processing Vector Table (cont) Vector Numbers 6 7 8 Vector Table AddressOffset H'00000018-H'0000001B H'0000001C-H'0000001F H'00000020-H'00000023 H'00000024-H'00000027 H'00000028-H'0000002B H'0000002C-H'0000002F H'00000030-H'00000033 H'00000034-H'00000037 H'00000038-H'0000003B H'0000003C-H'00000043 : H'0000007C-H'0000007F H'00000080-H'00000083 : H'000000FC-H'000000FF H'00000100-H'00000103 H'00000104-H'00000107 H'00000108-H'0000010B H'0000010C-H'0000010F H'00000110-H'00000113 H'00000114-H'00000117 H'00000118-H'0000011B H'0000011C-H'0000011F H'00000120-H'00000124 : H'000003FC-H'000003FF Exception Sources Slot illegal instruction (Reserved by system) CPU address error DMAC address error Interrupts NMI User break FPU exception H-UDI (Reserved by system) 9 10 11 12 13 14 16 : 31 Trap instruction (user vector) 32 : 63 Interrupts IRQ0 IRQ1 IRQ2 IRQ3 IRQ4 IRQ5 IRQ6 IRQ7 64 65 66 67 68 69 70 71 72 : 255 On-chip peripheral module* Note: * The vector numbers and vector table address offsets for each on-chip peripheral module interrupt are given in table 7.3, Interrupt Exception Processing Vectors and Priorities, in section 7, Interrupt Controller (INTC). Rev.2.0, 07/03, page 82 of 960 Table 6.4 Calculating Exception Processing Vector Table Addresses Vector Table Address Calculation Vector table address = (vector table address offset) = (vector number) x 4 Vector table address = VBR + (vector table address offset) = VBR + (vector number) x 4 Exception Source Resets Address errors, interrupts, instructions Notes: 1. VBR: Vector base register 2. Vector table address offset: See table 6.3. 3. Vector number: See table 6.3. Rev.2.0, 07/03, page 83 of 960 6.2 6.2.1 Resets Types of Reset A reset is the highest-priority exception processing source. There are two kinds of reset, power-on and manual. As shown in table 6.5, the CPU state is initialized in both a power-on reset and a manual reset. On-chip peripheral module registers are also initialized by a power-on reset, but not by a manual reset. Table 6.5 Exception Source Detection and Exception Processing Start Timing Conditions for Transition to Reset State WDT Overflow -- Power-on reset Manual reset CPU/MULT/ FPU/INTC Initialized Initialized Initialized Internal States On-Chip Peripheral Modules Initialized Initialized Not initialized Type Power-on reset RES Low High PFC, IO Port Initialized Not initialized Not initialized Manual reset High 6.2.2 Power-On Reset Power-On Reset by Means of RES Pin: When the RES pin is driven low, the chip enters the power-on reset state. To reliably reset the chip, the RES pin should be kept at the low level for at least the duration of the oscillation settling time at power-on or when in standby mode (when the clock is halted), or at least 20 tcyc when the clock is running. In the power-on reset state, the CPU's internal state and all the on-chip peripheral module registers are initialized. See Appendix B, Pin States, for the state of individual pins in the power-on reset state. In the power-on reset state, power-on reset exception processing starts when the RES pin is first driven low for a set period of time and then returned to high. The CPU operates as follows: 1. The initial value (execution start address) of the program counter (PC) is fetched from the exception processing vector table. 2. The initial value of the stack pointer (SP) is fetched from the exception processing vector table. 3. The vector base register (VBR) is cleared to H'00000000 and the interrupt mask bits (I3-I0) of the status register (SR) are set to H'F (1111). 4. The values fetched from the exception processing vector table are set in the PC and SP, and the program begins executing. Be certain to always perform power-on reset processing when turning the system power on. Rev.2.0, 07/03, page 84 of 960 Power-On Reset Initiated by WDT: When a setting is made for a power-on reset to be generated in the WDT's watchdog timer mode, and the WDT's TCNT overflows, the chip enters the poweron reset state. The pin function controller (PFC) registers and I/O port registers are not initialized by the reset signal generated by the WDT (these registers are only initialized by a power-on reset from offchip). If reset caused by the input signal at the RES pin and a reset caused by WDT overflow occur simultaneously, the RES pin reset has priority, and the WOVF bit in RSTCSR is cleared to 0. When WDT-initiated power-on reset processing is started, the CPU operates as follows: 1. The initial value (execution start address) of the program counter (PC) is fetched from the exception processing vector table. 2. The initial value of the stack pointer (SP) is fetched from the exception processing vector table. 3. The vector base register (VBR) is cleared to H'00000000 and the interrupt mask bits (I3-I0) of the status register (SR) are set to H'F (1111). 4. The values fetched from the exception processing vector table are set in the PC and SP, and the program begins executing. 6.2.3 Manual Reset When a setting is made for a manual reset to be generated in the WDT's watchdog timer mode, and the WDT's TCNT overflows, the chip enters the power-on reset state. When WDT-initiated manual reset processing is started, the CPU operates as follows: 1. The initial value (execution start address) of the program counter (PC) is fetched from the exception processing vector table. 2. The initial value of the stack pointer (SP) is fetched from the exception processing vector table. 3. The vector base register (VBR) is cleared to H'00000000 and the interrupt mask bits (I3-I0) of the status register (SR) are set to H'F (1111). 4. The values fetched from the exception processing vector table are set in the PC and SP, and the program begins executing. When a manual reset is generated, the bus cycle is retained, but if a manual reset occurs while the bus is released or during DMAC burst transfer, manual reset exception processing will be deferred until the CPU acquires the bus. However, if the interval from generation of the manual reset until the end of the bus cycle is equal to or longer than the internal manual reset interval of 512 cycles, the internal manual reset source is ignored instead of being deferred, and manual reset exception processing is not executed. Rev.2.0, 07/03, page 85 of 960 6.3 6.3.1 Address Errors Address Error Sources Address errors occur when instructions are fetched or data read or written, as shown in table 6.6. Table 6.6 Bus Cycles and Address Errors Bus Cycle Type Instruction fetch Bus Master CPU Bus Cycle Description Instruction fetched from even address Instruction fetched from odd address Instruction fetched from other than on-chip peripheral module space* Instruction fetched from on-chip peripheral module space* Instruction fetched from external memory space when in single chip mode Data read/write CPU or DMAC Word data accessed from even address Word data accessed from odd address Longword data accessed from a longword boundary Longword data accessed from other than a long-word boundary Byte or word data accessed in on-chip peripheral module space* Longword data accessed in 16-bit on-chip peripheral module space* Longword data accessed in 8-bit on-chip peripheral module space* External memory space accessed when in single chip mode Address Errors None (normal) Address error occurs None (normal) Address error occurs Address error occurs None (normal) Address error occurs None (normal) Address error occurs None (normal) None (normal) Address error occurs Address error occurs Note: * See section 9, Bus State Controller (BSC), for details of the on-chip peripheral module space. Rev.2.0, 07/03, page 86 of 960 6.3.2 Address Error Exception Processing When an address error occurs, the bus cycle in which the address error occurred ends. When the executing instruction then finishes, address error exception processing starts up. The CPU operates as follows: 1. The status register (SR) is saved to the stack. 2. The program counter (PC) is saved to the stack. The PC value saved is the start address of the instruction to be executed after the last executed instruction. 3. The exception service routine start address is fetched from the exception processing vector table that corresponds to the address error that occurred and the program starts executing from that address. The jump that occurs is not a delayed branch. 6.4 6.4.1 Interrupts Interrupt Sources Table 6.7 shows the sources that start up interrupt exception processing. These are divided into NMI, user breaks, H-UDI, IRQ, and on-chip peripheral modules. Table 6.7 Interrupt Sources Number of Sources Type NMI User break H-UDI IRQ On-chip peripheral module Request Source NMI pin (external input) User break controller High-performance user debug interface IRQ0-IRQ7 (external input) Direct memory access controller (DMAC) Advanced timer unit (ATU-II) Compare match timer (CMT) A/D converter Serial communication interface (SCI) Watchdog timer (WDT) Controller area network (HCAN) 1 1 1 8 4 75 2 3 20 1 8 Each interrupt source is allocated a different vector number and vector table offset. See table 7.3, Interrupt Exception Processing Vectors and Priorities, in section 7, Interrupt Controller (INTC), for more information on vector numbers and vector table address offsets. Rev.2.0, 07/03, page 87 of 960 6.4.2 Interrupt Priority Level The interrupt priority order is predetermined. When multiple interrupts occur simultaneously (overlap), the interrupt controller (INTC) determines their relative priorities and starts up processing according to the results. The priority order of interrupts is expressed as priority levels 0-16, with priority 0 the lowest and priority 16 the highest. The NMI interrupt has priority 16 and cannot be masked, so it is always accepted. The user break interrupt and H-UDI interrupt priority level is 15. IRQ interrupts and onchip peripheral module interrupt priority levels can be set freely using the INTC's interrupt priority registers A through L (IPRA to IPRL) as shown in table 6.8. The priority levels that can be set are 0-15. Level 16 cannot be set. See section 7.3.1, Interrupt Priority Registers A-L (IPRAIPRL), for details of the interrupt priority registers. Table 6.8 Type NMI User break H-UDI IRQ On-chip peripheral module Interrupt Priority Order Priority Level 16 15 15 0-15 0-15 Comment Fixed priority level. Cannot be masked. Fixed priority level. Fixed priority level. Set with interrupt priority level setting registers A through L (IPRA to IPRL). Set with interrupt priority level setting registers A through L (IPRA to IPRL). 6.4.3 Interrupt Exception Processing When an interrupt occurs, its priority level is ascertained by the interrupt controller (INTC). NMI is always accepted, but other interrupts are only accepted if they have a priority level higher than the priority level set in the interrupt mask bits (I3-I0) of the status register (SR). When an interrupt is accepted, exception processing begins. In interrupt exception processing, the CPU saves SR and the program counter (PC) to the stack. The priority level value of the accepted interrupt is written to SR bits I3-I0. For NMI, however, the priority level is 16, but the value set in I3-I0 is H'F (level 15). Next, the start address of the exception service routine is fetched from the exception processing vector table for the accepted interrupt, that address is jumped to and execution begins. See section 7.4, Interrupt Operation, for further details. Rev.2.0, 07/03, page 88 of 960 6.5 6.5.1 Exceptions Triggered by Instructions Types of Exceptions Triggered by Instructions Exception processing can be triggered by trap instructions, general illegal instructions, and illegal slot instructions, and floating-point instructions, as shown in table 6.9. Table 6.9 Type Trap instructions Illegal slot instructions Types of Exceptions Triggered by Instructions Source Instruction TRAPA Undefined code placed immediately after a delayed branch instruction (delay slot) and instructions that rewrite the PC Undefined code anywhere besides in a delay slot Instruction causing an invalid operation exception defined in the IEEE754 standard or a division-by-zero exception FADD, FSUB, FMUL, FDIV, FMAC, FCMP/EQ, FCMP/GT, FNEG, FABS, FTRC Delayed branch instructions: JMP, JSR, BRA, BSR, RTS, RTE, BF/S, BT/S, BSRF, BRAF Instructions that rewrite the PC: JMP, JSR, BRA, BSR, RTS, RTE, BT, BF, TRAPA, BF/S, BT/S, BSRF, BRAF Comment General illegal instructions Floating-point instructions 6.5.2 Trap Instructions When a TRAPA instruction is executed, trap instruction exception processing starts up. The CPU operates as follows: 1. The status register (SR) is saved to the stack. 2. The program counter (PC) is saved to the stack. The PC value saved is the start address of the instruction to be executed after the TRAPA instruction. 3. The exception service routine start address is fetched from the exception processing vector table that corresponds to the vector number specified in the TRAPA instruction. That address is jumped to and the program starts executing. The jump that occurs is not a delayed branch. Rev.2.0, 07/03, page 89 of 960 6.5.3 Illegal Slot Instructions An instruction placed immediately after a delayed branch instruction is said to be placed in a delay slot. When the instruction placed in the delay slot is undefined code, illegal slot exception processing starts up when that undefined code is decoded. Illegal slot exception processing also starts up when an instruction that rewrites the program counter (PC) is placed in a delay slot. The processing starts when the instruction is decoded. The CPU handles an illegal slot instruction as follows: 1. The status register (SR) is saved to the stack. 2. The program counter (PC) is saved to the stack. The PC value saved is the jump address of the delayed branch instruction immediately before the undefined code or the instruction that rewrites the PC. 3. The exception service routine start address is fetched from the exception processing vector table that corresponds to the exception that occurred. That address is jumped to and the program starts executing. The jump that occurs is not a delayed branch. 6.5.4 General Illegal Instructions When undefined code placed anywhere other than immediately after a delayed branch instruction (i.e., in a delay slot) is decoded, general illegal instruction exception processing starts up. The CPU handles general illegal instructions in the same way as illegal slot instructions. Unlike processing of illegal slot instructions, however, the program counter value stored is the start address of the undefined code. When the FPU has been stopped by means of the module stop bit, floating-point instructions and FPU-related CPU instructions are treated as illegal instructions. 6.5.5 Floating-Point Instructions When the V or Z bit is set in the enable field of the FPSCR register, an FPU exception occurs. This indicates that a floating-point instruction has caused an invalid operation exception defined in the IEEE754 standard or a division-by-zero exception. Floating-point instructions which can cause an exception are as follows: FADD, FSUB, FMUL, FDIV, FMAC, FCMP/EQ, FCMP/GT, FNEG, FABS, FTRC An FPU exception occurs only if the corresponding enable bit is set. When the FPU detects an exception source, FPU operation is suspended and the occurrence of the exception is reported to the CPU. When exception processing is started, the CPU saves the SR and PC contents to the stack (the PC value saved is the start address of the instruction following the last instruction executed), and branches to VBR + H'00000034. Rev.2.0, 07/03, page 90 of 960 The exception flag bits in the FPSCR are always updated, regardless of whether or not an FPU exception is accepted, and remain set until the user clears them explicitly with an instruction. FPSCR cause bits change each time an FPU instruction is executed. Exception events other than those defined in the IEEE754 standard (i.e., underflow, overflow, and inexact exceptions) are detected by the FPU but do not result in the generation of any kind of exception. Neither is an FPU exception generated by a floating-point instruction relating to data transfer, such as FLOAT. 6.6 When Exception Sources Are Not Accepted When an address error or interrupt is generated after a delayed branch instruction or interruptdisabled instruction, it is sometimes not accepted immediately but stored instead, as shown in table 6.10. When this happens, it will be accepted when an instruction that can accept the exception is decoded. Table 6.10 Generation of Exception Sources Immediately after a Delayed Branch Instruction or Interrupt-Disabled Instruction Exception Source Point of Occurrence Immediately after a delayed branch instruction*1 Immediately after an interrupt-disabled instruction*2 Immediately after an FPU instruction*3 Bus Error Not accepted Not accepted*4 Not accepted Interrupt Not accepted Not accepted Not accepted FPU Exception Not accepted Accepted Accepted Notes: *1. Delayed branch instructions: JMP, JSR, BRA, BSR, RTS, RTE, BF/S, BT/S, BSRF, BRAF *2. Interrupt-disabled instructions: LDC, LDC.L, STC, STC.L, LDS, LDS.L, STS, STS.L *3. FPU instructions: Table 2.18, Floating-Point Instructions, and table 2.19, FPU-Related CPU Instructions, in section 2.4.1, Instruction Set by Classification. *4. In the SH-2 a bus error is accepted. Rev.2.0, 07/03, page 91 of 960 6.7 Stack Status after Exception Processing Ends The status of the stack after exception processing ends is as shown in table 6.11. Table 6.11 Stack Status After Exception Processing Ends Exception Type Address error SP Address of instruction 32 bits after executed instruction SR 32 bits Stack Status Trap instruction SP Address of instruction after TRAPA instruction SR 32 bits 32 bits General illegal instruction SP Address of general illegal instruction SR 32 bits 32 bits Interrupt SP Address of instruction after executed instruction 32 bits SR 32 bits Illegal slot instruction SP Jump destination address of delay branch instruction 32 bits SR 32 bits FPU exception SP Address of instruction after FPU exception instruction 32 bits SR 32 bits Rev.2.0, 07/03, page 92 of 960 6.8 6.8.1 Usage Notes Value of Stack Pointer (SP) The value of the stack pointer must always be a multiple of four. If it is not, an address error will occur when the stack is accessed during exception processing. 6.8.2 Value of Vector Base Register (VBR) The value of the vector base register must always be a multiple of four. If it is not, an address error will occur when the stack is accessed during exception processing. 6.8.3 Address Errors Caused by Stacking of Address Error Exception Processing When the stack pointer is not a multiple of four, an address error will occur during stacking of the exception processing (interrupts, etc.) and address error exception processing will start up as soon as the first exception processing is ended. Address errors will then also occur in the stacking for this address error exception processing. To ensure that address error exception processing does not go into an endless loop, no address errors are accepted at that point. This allows program control to be shifted to the address error exception service routine and enables error processing. When an address error occurs during exception processing stacking, the stacking bus cycle (write) is executed. During stacking of the status register (SR) and program counter (PC), the SP is decremented by 4 for both, so the value of SP will not be a multiple of four after the stacking either. The address value output during stacking is the SP value, so the address where the error occurred is itself output. This means the write data stacked will be undefined. 6.8.4 Interrupt Processing Timing Gap Caused in SCO Processing If an interrupt processing is generated in an SCO processing, the interrupt generation timing is different because the interrupt processing is started after the SCO* processing. For details on the arbitration with the SCO processing, refer to section 22.8.2(1). Note: SCO is the processing to download the flash memory programming/erasing program on the on-chip RAM. Rev.2.0, 07/03, page 93 of 960 Rev.2.0, 07/03, page 94 of 960 Section 7 Interrupt Controller (INTC) 7.1 Overview The interrupt controller (INTC) ascertains the priority of interrupt sources and controls interrupt requests to the CPU. The INTC has registers for setting the priority of each interrupt which can be used by the user to order the priorities in which the interrupt requests are processed. 7.1.1 Features The INTC has the following features: * 16 levels of interrupt priority By setting the twelve interrupt-priority level registers, the priorities of IRQ interrupts and onchip peripheral module interrupts can be set in 16 levels for different request sources. * NMI noise canceler function NMI input level bits indicate the NMI pin status. By reading these bits with the interrupt exception service routine, the pin status can be confirmed, enabling it to be used as a noise canceler. * Notification of interrupt occurrence can be reported externally (IRQOUT pin) For example, it is possible to request the bus if an external bus master is informed that a peripheral module interrupt has occurred when the chip has released the bus. Rev.2.0, 07/03, page 95 of 960 7.1.2 Block Diagram Figure 7.1 is a block diagram of the INTC. NMI Input control CPU/ DMAC request judgment Priority ranking judgment Comparator Interrupt request SR UBC H-UDI DMAC ATU-II CMT A/D SCI WDT HCAN (Interrupt request) (Interrupt request) (Interrupt request) (Interrupt request) (Interrupt request) (Interrupt request) (Interrupt request) (Interrupt request) (Interrupt request) I3 I2 I1 I0 CPU ICR ISR IPR IPRA-IPRL Bus interface Module bus INTC SCI: Serial communication interface UBC: User break controller WDT: Watchdog timer H-UDI: High-performance user debug HCAN: Controller area network interface ICR: Interrupt control register DMAC: Direct memory access controller ISR: IRQ status register ATU-II: Advanced timer unit IPRA-IPRL: Interrupt priority level setting registers A to L CMT: Compare match timer SR: Status register A/D: A/D converter Figure 7.1 INTC Block Diagram Rev.2.0, 07/03, page 96 of 960 Internal bus 7.1.3 Pin Configuration Table 7.1 shows the INTC pin configuration. Table 7.1 Name Non-maskable interrupt input pin Interrupt request input pins Interrupt request output pin Pin Configuration Abbreviation NMI IRQ0-IRQ7 IRQOUT I/O I I O Function Input of non-maskable interrupt request signal Input of maskable interrupt request signals Output of notification signal when an interrupt has occurred 7.1.4 Register Configuration The INTC has the 14 registers shown in table 7.2. These registers set the priority of the interrupts and control external interrupt input signal detection. Table 7.2 Name Interrupt priority register A Interrupt priority register B Interrupt priority register C Interrupt priority register D Interrupt priority register E Interrupt priority register F Interrupt priority register G Interrupt priority register H Interrupt priority register I Interrupt priority register J Interrupt priority register K Interrupt priority register L Interrupt control register IRQ status register Register Configuration Abbr. IPRA IPRB IPRC IPRD IPRE IPRF IPRG IPRH IPRI IPRJ IPRK IPRL ICR ISR R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R(W)* 2 Initial Value H'0000 H'0000 H'0000 H'0000 H'0000 H'0000 H'0000 H'0000 H'0000 H'0000 H'0000 H'0000 * 1 Address H'FFFF ED00 H'FFFF ED02 H'FFFF ED04 H'FFFF ED06 H'FFFF ED08 H'FFFF ED0A H'FFFF ED0C H'FFFF ED0E H'FFFF ED10 H'FFFF ED12 H'FFFF ED14 H'FFFF ED16 H'FFFF ED18 H'FFFF ED1A Access Sizes 8, 16, 32 8, 16, 32 8, 16, 32 8, 16, 32 8, 16, 32 8, 16, 32 8, 16, 32 8, 16, 32 8, 16, 32 8, 16, 32 8, 16, 32 8, 16, 32 8, 16, 32 8, 16, 32 H'0000 Notes: Three access cycles are required for byte access and word access, and six cycles for longword access. *1. The value when the NMI pin is high is H'8000; when the NMI pin is low, it is H'0000. *2. Only 0 can be written, in order to clear flags. Rev.2.0, 07/03, page 97 of 960 7.2 Interrupt Sources There are five types of interrupt sources: NMI, user breaks, H-UDI, IRQ, and on-chip peripheral modules. Each interrupt has a priority expressed as a priority level (0 to 16, with 0 the lowest and 16 the highest). Giving an interrupt a priority level of 0 masks it. 7.2.1 NMI Interrupts The NMI interrupt has priority 16 and is always accepted. Input at the NMI pin is detected by edge. Use the NMI edge select bit (NMIE) in the interrupt control register (ICR) to select either the rising or falling edge. NMI interrupt exception processing sets the interrupt mask level bits (I3-I0) in the status register (SR) to level 15. 7.2.2 User Break Interrupt A user break interrupt has a priority of level 15, and occurs when the break condition set in the user break controller (UBC) is satisfied. User break interrupt requests are detected by edge and are held until accepted. User break interrupt exception processing sets the interrupt mask level bits (I3-I0) in the status register (SR) to level 15. For more information about the user break interrupt, see section 8, User Break Controller (UBC). 7.2.3 H-UDI Interrupt A serial debug interface (H-UDI) interrupt has a priority level of 15, and occurs when an H-UDI interrupt instruction is serially input. H-UDI interrupt requests are detected by edge and are held until accepted. H-UDI exception processing sets the interrupt mask level bits (I3-I0) in the status register (SR) to level 15. For more information about the H-UDI interrupt, see section 18, HighPerformance User Debug Interface (H-UDI). 7.2.4 IRQ Interrupts IRQ interrupts are requested by input from pins IRQ0-IRQ7. Set the IRQ sense select bits (IRQ0S-IRQ7S) of the interrupt control register (ICR) to select low level detection or falling edge detection for each pin. The priority level can be set from 0 to 15 for each pin using interrupt priority registers A and B (IPRA-IPRB). When IRQ interrupts are set to low level detection, an interrupt request signal is sent to the INTC during the period the IRQ pin is low. Interrupt request signals are not sent to the INTC when the IRQ pin becomes high. Interrupt request levels can be confirmed by reading the IRQ flags (IRQ0F-IRQ7F) of the IRQ status register (ISR). Rev.2.0, 07/03, page 98 of 960 When IRQ interrupts are set to falling edge detection, interrupt request signals are sent to the INTC upon detecting a change on the IRQ pin from high to low level. IRQ interrupt request detection results are maintained until the interrupt request is accepted. Confirmation that IRQ interrupt requests have been detected is possible by reading the IRQ flags (IRQ0F-IRQ7F) of the IRQ status register (ISR), and by writing a 0 after reading a 1, IRQ interrupt request detection results can be withdrawn. In IRQ interrupt exception processing, the interrupt mask bits (I3-I0) of the status register (SR) are set to the priority level value of the accepted IRQ interrupt. 7.2.5 On-Chip Peripheral Module Interrupts On-chip peripheral module interrupts are interrupts generated by the following on-chip peripheral modules: * Direct memory access controller (DMAC) * Advanced timer unit (ATU-II) * Compare match timer (CMT) * A/D converter (A/D) * Serial communication interface (SCI) * Watchdog timer (WDT) * Controller area network (HCAN) A different interrupt vector is assigned to each interrupt source, so the exception service routine does not have to decide which interrupt has occurred. Priority levels between 0 and 15 can be assigned to individual on-chip peripheral modules in interrupt priority registers C-L (IPRC- IPRL). On-chip peripheral module interrupt exception processing sets the interrupt mask level bits (I3-I0) in the status register (SR) to the priority level value of the on-chip peripheral module interrupt that was accepted. Rev.2.0, 07/03, page 99 of 960 7.2.6 Interrupt Exception Vectors and Priority Rankings Table 7.3 lists interrupt sources and their vector numbers, vector table address offsets and interrupt priorities. Each interrupt source is allocated a different vector number and vector table address offset. Vector table addresses are calculated from vector numbers and address offsets. In interrupt exception processing, the exception service routine start address is fetched from the vector table indicated by the vector table address. See table 6.4, Calculating Exception Processing Vector Table Addresses, in section 6, Exception Processing. IRQ interrupts and on-chip peripheral module interrupt priorities can be set freely between 0 and 15 for each pin or module by setting interrupt priority registers A-L (IPRA-IPRL). The ranking of interrupt sources for IPRC-IPRL, however, must be the order listed under Priority within IPR Setting Range in table 7.3 and cannot be changed. A power-on reset assigns priority level 0 to IRQ interrupts and on-chip peripheral module interrupts. If the same priority level is assigned to two or more interrupt sources and interrupts from those sources occur simultaneously, their priority order is the default priority order indicated at the right in table 7.3. Rev.2.0, 07/03, page 100 of 960 Table 7.3 Interrupt Exception Processing Vectors and Priorities Interrupt Vector Vector Table Vector Address Offset No. 11 12 14 64 65 66 67 68 69 70 71 DEI0 DEI1 DEI2 DEI3 72 74 76 78 Interrupt Priority (Initial Value) Priority within IPR Corresponding Setting IPR (Bits) Range -- -- -- -- -- -- -- -- -- -- -- -- -- -- 1 2 1 2 Low Interrupt Source NMI UBC H-UDI IRQ0 IRQ1 IRQ2 IRQ3 IRQ4 IRQ5 IRQ6 IRQ7 DMAC0 DMAC1 DMAC2 DMAC3 Default Priority High H'0000002C to 16 H'0000002F H'00000030 to 15 H'00000033 H'00000038 to 15 H'00000038 H'00000100 to 0 to 15 (0) IPRA H'00000103 (15-12) H'00000104 to 0 to 15 (0) IPRA H'00000107 (11-8) H'00000108 to 0 to 15 (0) IPRA H'0000010B (7-4) H'0000010C to 0 to 15 (0) IPRA H'0000010F (3-0) H'00000110 to 0 to 15 (0) IPRB H'00000113 (15-12) H'00000114 to 0 to 15 (0) IPRB H'00000117 (11-8) H'00000118 to 0 to 15 (0) IPRB H'0000011B (7-4) H'0000011C to 0 to 15 (0) IPRB H'0000011F (3-0) H'00000120 to 0 to 15 (0) IPRC H'00000123 (15-12) H'00000128 to 0 to 15 (0) H'0000012B H'00000130 to 0 to 15 (0) IPRC H'00000133 (11-8) H'00000138 to 0 to 15 (0) H'0000013B Rev.2.0, 07/03, page 101 of 960 Table 7.3 Interrupt Exception Processing Vectors and Priorities (cont) Interrupt Vector Vector Table Vector Address Offset No. ITV1/ ITV2A/ ITV2B ICI0A ICI0B 80 Interrupt Priority (Initial Value) Priority within IPR CorreDefault sponding Setting Priority IPR (Bits) Range High Interrupt Source ATU0 ATU01 H'00000140 to 0 to 15 (0) IPRC H'00000143 (7-4) H'00000150 to 0 to 15 (0) IPRC H'00000153 (3-0) H'00000158 to H'0000015B H'00000160 to 0 to 15 (0) IPRD H'00000163 (15-12) H'00000168 to H'0000016B H'00000170 to 0 to 15 (0) IPRD H'00000173 (11-8) H'00000180 to 0 to 15 (0) IPRD H'00000183 (7-4) H'00000184 to H'00000187 H'00000188 to H'0000018B H'0000018C to H'0000018F H'00000190 to 0 to 15 (0) IPRD H'00000193 (3-0) H'00000194 to H'00000197 H'00000198 to H'0000019B H'0000019C to H'0000019F H'000001A0 to 0 to 15 (0) IPRE H'000001A3 (15-12) 1 2 3 4 1 2 3 4 1 2 1 2 ATU02 84 86 88 90 92 ATU03 ICI0C ICI0D ATU04 ATU1 ATU11 OVI0 IMI1A/C 96 MI1 IMI1B IMI1C IMI1D 97 98 99 100 101 102 103 104 ATU12 IMI1E IMI1F IMI1G IMI1H ATU13 OVI1A/ OVI1B Low Rev.2.0, 07/03, page 102 of 960 Table 7.3 Interrupt Exception Processing Vectors and Priorities (cont) Interrupt Vector Vector Table Vector Address Offset No. IMI2A/C 108 MI2A IMI2B/C 109 MI2B IMI2C/C 110 MI2C IMI2D/C 111 MI2D Interrupt Priority (Initial Value) Priority within IPR Corresponding Setting IPR (Bits) Range 1 2 3 4 1 2 3 4 Interrupt Source ATU2 ATU21 Default Priority High H'000001B0 to 0 to 15 (0) IPRE H'000001B3 (11-8) H'000001B4 to H'000001B7 H'000001B8 to H'000001BB H'000001BC to H'000001BF H'000001C0 to 0 to 15 (0) IPRE H'000001C3 (7-4) H'000001C4 to H'000001C7 H'000001C8 to H'000001CB H'000001CC to H'000001CF H'000001D0 to 0 to 15 (0) IPRE H'000001D3 (3-0) H'000001E0 to 0 to 15 (0) IPRF H'000001E3 (15-12) H'000001E4 to H'000001E7 H'000001E8 to H'000001EB H'000001EC to H'000001EF H'000001F0 to 0 to 15 (0) IPRF H'000001F3 (11-8) ATU22 IMI2E/C 112 MI2E IMI2F/C 113 MI2F IMI2G/C 114 MI2G IMI2H/C 115 MI2H ATU23 ATU3 ATU31 OVI2A/O 116 VI2B IMI3A IMI3B IMI3C IMI3D 120 121 122 123 124 1 2 3 4 Low ATU32 OVI3 Rev.2.0, 07/03, page 103 of 960 Table 7.3 Interrupt Exception Processing Vectors and Priorities (cont) Interrupt Vector Table Priority (Initial Vector Address Value) Offset No. IMI4A IMI4B IMI4C IMI4D 128 129 130 131 132 136 137 138 139 140 144 145 146 147 Interrupt Vector Priority within IPR Corresponding Setting IPR (Bits) Range 1 2 3 4 Interrupt Source ATU4 ATU41 Default Priority High H'00000200 to 0 to 15 (0) IPRF H'00000203 (7-4) H'00000204 to H'00000207 H'00000208 to H'0000020B H'0000020C to H'0000020F H'00000210 to 0 to 15 (0) IPRF H'00000213 (3-0) H'00000220 to 0 to 15 (0) IPRG H'00000223 (15-12) H'00000224 to H'00000227 H'00000228 to H'0000022B H'0000022C to H'0000022F H'00000230 to 0 to 15 (0) IPRG H'00000233 (11-8) H'00000240 to 0 to 15 (0) IPRG H'00000243 (7-4) H'00000244 to H'00000247 H'00000248 to H'0000024B H'0000024C to H'0000024F ATU42 ATU5 ATU51 OVI4 IMI5A IMI5B IMI5C IMI5D 1 2 3 4 ATU52 ATU6 OVI5 CMI6A CMI6B CMI6C CMI6D 1 2 3 4 Low Rev.2.0, 07/03, page 104 of 960 Table 7.3 Interrupt Exception Processing Vectors and Priorities (cont) Interrupt Vector Vector Table Vector Address Offset No. CMI7A CMI7B CMI7C CMI7D 148 149 150 151 152 153 154 155 156 157 158 159 160 161 162 163 Interrupt Priority (Initial Value) Priority within IPR Corresponding Setting IPR (Bits) Range 1 2 3 4 1 2 3 4 1 2 3 4 1 2 3 4 Low Interrupt Source ATU7 Default Priority High H'00000250 to 0 to 15 (0) IPRG H'00000253 (3-0) H'00000254 to H'00000257 H'00000258 to H'0000025B H'0000025C to H'0000025F H'00000260 to 0 to 15 (0) IPRH H'00000263 (15-12) H'00000264 to H'00000267 H'00000268 to H'0000026B H'0000026C to H'0000026F H'00000270 to 0 to 15 (0) IPRH H'00000273 (11-8) H'00000274 to H'00000277 H'00000278 to H'0000027B H'0000027C to H'0000027F H'00000280 to 0 to 15 (0) IPRH H'00000283 (7-4) H'00000284 to H'00000287 H'00000288 to H'0000028B H'0000028C to H'0000028F ATU8 ATU81 OSI8A OSI8B OSI8C OSI8D ATU82 OSI8E OSI8F OSI8G OSI8H ATU83 OSI8I OSI8J OSI8K OSI8L Rev.2.0, 07/03, page 105 of 960 Table 7.3 Interrupt Exception Processing Vectors and Priorities (cont) Interrupt Vector Vector Table Vector Address Offset No. OSI8M OSI8N OSI8O OSI8P 164 165 166 167 168 169 170 171 172 174 Interrupt Priority (Initial Value) Priority within IPR Corresponding Setting IPR (Bits) Range 1 2 3 4 1 2 3 IPRI (3-0) 1 2 3 Low 4 1 2 1 2 Interrupt Source ATU8 ATU84 Default Priority High H'00000290 to 0 to 15 (0) IPRH H'00000293 (3-0) H'00000294 to H'00000297 H'00000298 to H'0000029B H'0000029C to H'0000029F H'000002A0 to 0 to 15 (0) IPRI H'000002A3 (15-12) H'000002A4 to H'000002A7 H'000002A8 to H'000002AB H'000002AC to H'000002AF H'000002B0 to 0 to 15 (0) IPRI (11-8) H'000002B3 H'000002B8 to H'000002BB H'000002C0 to 0 to 15 (0) IPRI H'000002C3 (7-4) H'000002C8 to H'000002CB H'000002D0 to 0 to 15(0) H'000002D3 ATU9 ATU91 CMI9A CMI9B CMI9C CMI9D ATU92 CMI9E CMI9F ATU10 ATU101 CMI10A 176 CMI10B 178 ATU102 ICI10A/C 180 MI10G ATU11 IMI11A IMI11B OVI11 184 186 187 H'000002E0 to 0 to 15 (0) IPRJ (15-12) H'000002E3 H'000002E8 to H'000002EB H'000002EC to H'000002EF Rev.2.0, 07/03, page 106 of 960 Table 7.3 Interrupt Exception Processing Vectors and Priorities (cont) Interrupt Vector Vector Table Vector Address Offset No. CMTI0 ADI0 CMTI1 ADI1 ADI2 ERI0 RXI0 TXI0 TEI0 188 190 192 194 196 200 201 202 203 204 205 206 207 208 209 210 211 Interrupt Priority (Initial Value) Priority within IPR Corresponding Setting IPR (Bits) Range 1 2 1 2 Interrupt Source CMT0 A/D0 CMT1 A/D1 A/D2 SCI0 Default Priority High H'000002F0 to 0 to 15 (0) I PRJ (11-8) H'000002F3 H'000002F8 to H'000002FB H'00000300 to 0 to 15 (0) IPRJ (7-4) H'00000303 H'00000308 to H'0000030B H'00000310 to 0 to 15 (0) IPRJ H'00000313 (3-0) H'00000320 to 0 to 15 (0) IPRK H'00000323 (15-12) H'00000324 to H'00000327 H'00000328 to H'0000032B H'0000032C to H'0000032F H'00000330 to 0 to 15 (0) IPRK H'00000333 (11-8) H'00000334 to H'00000337 H'00000338 to H'0000033B H'0000033C to H'0000033F H'00000340 to 0 to 15 (0) IPRK H'00000343 (7-4) H'00000344 to H'00000347 H'00000348 to H'0000034B H'0000034C to H'0000034F 1 2 3 4 1 2 3 SCI1 ERI1 RXI1 TXI1 TEI1 4 1 2 3 SCI2 ERI2 RXI2 TXI2 TEI2 4 Low Rev.2.0, 07/03, page 107 of 960 Table 7.3 Interrupt Exception Processing Vectors and Priorities (cont) Interrupt Vector Vector Table Vector Address Offset No. ERI3 RXI3 TXI3 TEI3 212 213 214 215 216 217 218 219 220 221 222 223 224 228 229 230 231 Interrupt Priority (Initial Value) Priority within IPR Corresponding Setting IPR (Bits) Range 1 2 3 4 1 2 3 4 1 2 3 4 Interrupt Source SCI3 Default Priority High H'00000350 to 0 to 15 (0) IPRK H'00000353 (3-0) H'00000354 to H'00000357 H'00000358 to H'0000035B H'0000035C to H'0000035F H'00000360 to 0 to 15 (0) IPRL H'00000363 (15-12) H'00000364 to H'00000367 H'00000368 to H'0000036B H'0000036C to H'0000036F H'00000370 to 0 to 15 (0) IPRL H'00000373 (11-8) H'00000374 to H'00000377 H'00000378 to H'0000037B H'0000037C to H'0000037F H'00000380 to 0 to 15 (0) IPRL H'00000383 (7-4) H'00000390 to 0 to 15 (0) IPRL H'00000393 (3-0) H'00000394 to H'00000397 H'00000398 to H'0000039B H'0000039C to H'0000039F SCI4 ERI4 RXI4 TXI4 TEI4 HCAN0 ERS0 OVR0 RM0 SLE0 WDT HCAN1 ITI ERS1 OVR1 RM1 SLE1 1 2 3 4 Low Rev.2.0, 07/03, page 108 of 960 7.3 7.3.1 Description of Registers Interrupt Priority Registers A-L (IPRA-IPRL) Interrupt priority registers A-L (IPRA-IPRL) are 16-bit readable/writable registers that set priority levels from 0 to 15 for IRQ interrupts and on-chip peripheral module interrupts. Correspondence between interrupt request sources and each of the IPRA-IPRL bits is shown in table 7.4. Bit: 15 14 13 12 11 10 9 8 Initial value: R/W: Bit: 0 R/W 7 0 R/W 6 0 R/W 5 0 R/W 4 0 R/W 3 0 R/W 2 0 R/W 1 0 R/W 0 Initial value: R/W: 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W Table 7.4 Interrupt Request Sources and IPRA-IPRL Bits Register Interrupt priority register A Interrupt priority register B Interrupt priority register C Interrupt priority register D Interrupt priority register E Interrupt priority register F Interrupt priority register G Interrupt priority register H Interrupt priority register I Interrupt priority register J Interrupt priority register K Interrupt priority register L 15-12 IRQ0 IRQ4 DMAC0, 1 ATU03 ATU13 ATU31 ATU51 ATU81 ATU91 ATU11 SCI0 SCI4 11-8 IRQ1 IRQ5 DMAC2, 3 ATU04 ATU21 ATU32 ATU52 ATU82 ATU92 CMT0, A/D0 SCI1 HCAN0 7-4 IRQ2 IRQ6 ATU01 ATU11 ATU22 ATU41 ATU6 ATU83 ATU101 CMT1, A/D1 SCI2 WDT 3-0 IRQ3 IRQ7 ATU02 ATU12 ATU23 ATU42 ATU7 ATU84 ATU102 A/D2 SCI3 HCAN1 Rev.2.0, 07/03, page 109 of 960 As indicated in table 7.4, four IRQ pins or groups of 4 on-chip peripheral modules are allocated to each register. Each of the corresponding interrupt priority ranks are established by setting a value from H'0 (0000) to H'F (1111) in each of the four-bit groups 15-12, 11-8, 7-4, and 3-0. Interrupt priority rank becomes level 0 (lowest) by setting H'0, and level 15 (highest) by setting H'F. If multiple on-chip peripheral modules are assigned to the same bit (DMAC0 and DMAC1, DMAC2 and DMAC3, CMT0 and A/D0, and CMT1 and A/D1), those multiple modules are set to the same priority rank. IPRA-IPRL are initialized to H'0000 by a reset and in hardware standby mode. They are not initialized in software standby mode. 7.3.2 Interrupt Control Register (ICR) ICR is a 16-bit register that sets the input signal detection mode of the external interrupt input pin NMI and IRQ0 -IRQ7 and indicates the input signal level at the NMI pin. A reset and hardware standby mode initialize ICR but the software standby mode does not. Bit: 15 NMIL Initial value: R/W: Bit: * R 7 IRQ0S Initial value: R/W: 0 R/W 14 -- 0 R 6 IRQ1S 0 R/W 13 -- 0 R 5 IRQ2S 0 R/W 12 -- 0 R 4 IRQ3S 0 R/W 11 -- 0 R 3 IRQ4S 0 R/W 10 -- 0 R 2 IRQ5S 0 R/W 9 -- 0 R 1 IRQ6S 0 R/W 8 NMIE 0 R/W 0 IRQ7S 0 R/W Note: * When NMI input is high: 1; when NMI input is low: 0 * Bit 15--NMI Input Level (NMIL): Sets the level of the signal input at the NMI pin. This bit can be read to determine the NMI pin level. This bit cannot be modified. Bit 15: NMIL 0 1 Description NMI input level is low NMI input level is high * Bits 14 to 9--Reserved: These bits always read 0. The write value should always be 0. Rev.2.0, 07/03, page 110 of 960 * Bit 8--NMI Edge Select (NMIE) Bit 8: NMIE 0 1 Description Interrupt request is detected on falling edge of NMI input (Initial value) Interrupt request is detected on rising edge of NMI input * Bits 7 to 0--IRQ0-IRQ7 Sense Select (IRQ0S-IRQ7S): These bits set the IRQ0-IRQ7 interrupt request detection mode. Bits 7-0: IRQ0S-IRQ7S 0 1 Description Interrupt request is detected on low level of IRQ input Interrupt request is detected on falling edge of IRQ input (Initial value) 7.3.3 IRQ Status Register (ISR) ISR is a 16-bit register that indicates the interrupt request status of the external interrupt input pins IRQ0-IRQ7. When IRQ interrupts are set to edge detection, held interrupt requests can be withdrawn by writing 0 to IRQnF after reading IRQnF = 1. A reset and hardware standby mode initialize ISR but software standby mode does not. Bit: 15 -- Initial value: R/W: Bit: 0 R 7 IRQ0F Initial value: R/W: 0 R/W 14 -- 0 R 6 IRQ1F 0 R/W 13 -- 0 R 5 IRQ2F 0 R/W 12 -- 0 R 4 IRQ3F 0 R/W 11 -- 0 R 3 IRQ4F 0 R/W 10 -- 0 R 2 IRQ5F 0 R/W 9 -- 0 R 1 IRQ6F 0 R/W 8 -- 0 R 0 IRQ7F 0 R/W * Bits 15 to 8--Reserved: These bits always read 0. The write value should always be 0. Rev.2.0, 07/03, page 111 of 960 * Bits 7 to 0--IRQ0-IRQ7 Flags (IRQ0F-IRQ7F): These bits display the IRQ0-IRQ7 interrupt request status. Bits 7-0: IRQ0F-IRQ7F 0 Detection Setting Level detection Description No IRQn interrupt request exists [Clearing condition] When IRQn input is high Edge detection No IRQn interrupt request was detected [Clearing conditions] * * When 0 is written after reading IRQnF = 1 When IRQn interrupt exception processing has been executed (Initial value) 1 Level detection Edge detection An IRQn interrupt request exists Setting condition: When IRQn input is low An IRQn interrupt request was detected Setting condition: When a falling edge occurs at an IRQn input n = 7 to 0 Rev.2.0, 07/03, page 112 of 960 7.4 7.4.1 Interrupt Operation Interrupt Sequence The sequence of interrupt operations is explained below. Figure 7.2 is a flowchart of the operations. 1. The interrupt request sources send interrupt request signals to the interrupt controller. 2. The interrupt controller selects the highest priority interrupt in the interrupt requests sent, following the priority levels set in interrupt priority registers A-L (IPRA-IPRL). Lowerpriority interrupts are ignored. They are held pending until interrupt requests designated as edge-detect type are accepted. For IRQ interrupts, however, withdrawal is possible by accessing the IRQ status register (ISR). See section 7.2.4, IRQ Interrupts, for details. Interrupts held pending due to edge detection are cleared by a power-on reset or a manual reset. If two of these interrupts have the same priority level or if multiple interrupts occur within a single module, the interrupt with the highest default priority or the highest priority within its IPR setting range (as indicated in table 7.3) is selected. 3. The interrupt controller compares the priority level of the selected interrupt request with the interrupt mask bits (I3-I0) in the CPU's status register (SR). If the request priority level is equal to or less than the level set in I3-I0, the request is ignored. If the request priority level is higher than the level in bits I3-I0, the interrupt controller accepts the interrupt and sends an interrupt request signal to the CPU. 4. When the interrupt controller accepts an interrupt, a low level is output from the IRQOUT pin. 5. The CPU detects the interrupt request sent from the interrupt controller when it decodes the next instruction to be executed. Instead of executing the decoded instruction, the CPU starts interrupt exception processing (figure 7.4). 6. SR and PC are saved onto the stack. 7. The priority level of the accepted interrupt is copied to the interrupt mask level bits (I3 to I0) in the status register (SR). 8. When the accepted interrupt is sensed by level or is from an on-chip peripheral module, a high level is output from the IRQOUT pin. When the accepted interrupt is sensed by edge, a high level is output from the IRQOUT pin at the point when the CPU starts interrupt exception processing instead of instruction execution as noted in 5 above. However, if the interrupt controller accepts an interrupt with a higher priority than one it is in the process of accepting, the IRQOUT pin will remain low. 9. The CPU reads the start address of the exception service routine from the exception vector table for the accepted interrupt, jumps to that address, and starts executing the program there. This jump is not a delay branch. Rev.2.0, 07/03, page 113 of 960 Program execution state No Interrupt? Yes NMI? Yes No User break? Yes No H-UDI interrupt? Yes No Level 15 interrupt? Yes No = low level*1 Save SR to stack Save PC to stack Copy accept-interrupt level to I3 to I0 = high level*2 Read exception vector table Branch to exception service routine I3 to I0: Interrupt mask bits of status register Notes: *1. is the same signal as the interrupt request signal to the CPU (see figure 7.1). Thus, it is output when there is a higher priority interrupt request than the one in the I3 to I0 bits of SR. pin becomes high level at the *2. When the accepted interrupt is sensed by edge, the point when the CPU starts interrupt exception processing instead of instruction execution (before SR is saved to the stack). If the interrupt controller has accepted another interrupt with a higher priority and has pin will remain low. output an interrupt request to the CPU, the Yes Level 14 interrupt? Yes I3 to I0 level 13? No Yes No Level 1 interrupt? Yes I3 to I0 = level 0? No No I3 to I0 level 14? No Yes Figure 7.2 Interrupt Sequence Flowchart Rev.2.0, 07/03, page 114 of 960 7.4.2 Stack after Interrupt Exception Processing Figure 7.3 shows the stack after interrupt exception processing. Address 4n-n8 4n-n4 4n PC*1 SR 32 bits 32 bits SP*2 Notes: *1 *2 PC: Start address of the next instruction (return destination instruction) after the executing instruction Always be certain that SP is a multiple of 4 Figure 7.3 Stack after Interrupt Exception Processing Rev.2.0, 07/03, page 115 of 960 7.5 Interrupt Response Time Table 7.5 indicates the interrupt response time, which is the time from the occurrence of an interrupt request until the interrupt exception processing starts and fetching of the first instruction of the interrupt service routine begins. Figure 7.4 shows an example of pipeline operation when an IRQ interrupt is accepted. Table 7.5 Interrupt Response Time Number of States Item NMI, Peripheral Module IRQ 0 Notes 1 state required for interrupt signals for which DMAC activation is possible DMAC activation judgment 0 or 1 Compare identified interrupt priority with SR mask level Wait for completion of sequence currently being executed by CPU 2 3 X ( 0) The longest sequence is for interrupt or address-error exception processing (X = 4 + m1 + m2 + m3 + m4). If an interrupt-masking instruction follows, however, the time may be even longer. Performs the PC and SR saves and vector address fetch. Time from start of interrupt 5 + m1 + m2 + m3 exception processing until fetch of first instruction of exception service routine starts Interrupt response time Total: (7 or 8) + m1 + m2 + m3 + X 8 + m1 + m2 + m3 + X 11 12 + 2 (m1 + m2 + m3) + m4 Minimum: 10 Maximum: 12 + 2 (m1 + m2 + m3) + m4 0.25 to 0.28 s at 40 MHz 0.48 s at 40 MHz* Note: * When m1 = m2 = m3 = m4 = 1 m1-m4 are the number of states needed for the following memory accesses. m1: SR save (longword write) m2: PC save (longword write) m3: Vector address read (longword read) m4: Fetch first instruction of interrupt service routine Rev.2.0, 07/03, page 116 of 960 Interrupt acceptance 5 + m1 + m2 + m3 3 m1 m2 1 m3 1 3 IRQ Instruction (instruction replaced by interrupt exception processing) Overrun fetch Interrupt service routine start instruction FDEEMMEMEE F FDE F: Instruction fetch (instruction fetched from memory where program is stored). D: Instruction decoding (fetched instruction is decoded). E: Instruction execution (data operation and address calculation is performed according to the results of decoding). M: Memory access (data in memory is accessed). Figure 7.4 Example of Pipeline Operation when an IRQ Interrupt is Accepted Rev.2.0, 07/03, page 117 of 960 7.6 Data Transfer with Interrupt Request Signals The following data transfer can be carried out using interrupt request signals: * Activate DMAC only, without generating CPU interrupt Among interrupt sources, those designated as DMAC activating sources are masked and not input to the INTC. The masking condition is as follows: Mask condition = DME * (DE0 * source selection 0 + DE1 * source selection 1 + DE2 * source selection 2 + DE3 * source selection 3) 7.6.1 Handling CPU Interrupt Sources, but Not DMAC Activating Sources 1. Either do not select the DMAC as a source, or clear the DME bit to 0. 2. Activating sources are applied to the CPU when interrupts occur. 3. The CPU clears interrupt sources with its interrupt processing routine and performs the necessary processing. 7.6.2 Handling DMAC Activating Sources but Not CPU Interrupt Sources 1. Select the DMAC as a source and set the DME bit to 1. CPU interrupt sources are masked regardless of the interrupt priority level register settings. 2. Activating sources are applied to the DMAC when interrupts occur. 3. The DMAC clears activating sources at the time of data transfer. Rev.2.0, 07/03, page 118 of 960 Section 8 User Break Controller (UBC) 8.1 Overview The user break controller (UBC) provides functions that simplify program debugging. Break conditions are set in the UBC and a user break interrupt is generated according to the conditions of the bus cycle generated by the CPU or DMAC. This function makes it easy to design an effective self-monitoring debugger, enabling the chip to easily debug programs without using a large incircuit emulator. 8.1.1 Features The features of the user break controller are: * The following break compare conditions can be set: Address CPU cycle/DMA cycle Instruction fetch or data access Read or write Operand size: byte/word/longword * User break interrupt generated upon satisfying break conditions A user-designed user break interrupt exception processing routine can be run. * Select either to break in the CPU instruction fetch cycle before the instruction is executed or after. * Satisfaction of a break condition can be output to the UBCTRG pin. Rev.2.0, 07/03, page 119 of 960 8.1.2 Block Diagram Figure 8.1 shows a block diagram of the UBC. Module bus Bus interface Internal bus UBCR UBBR UBAMRH UBAMRL UBARH UBARL Break condition comparator User break interrupt generating circuit Interrupt request Trigger output generating circuit Interrupt controller pin output UBARH, UBARL: UBAMRH, UBAMRL: UBBR: UBCR: User break address registers H, L User break address mask registers H, L User break bus cycle register User break control register Figure 8.1 User Break Controller Block Diagram Rev.2.0, 07/03, page 120 of 960 8.1.3 Register Configuration The UBC has the six registers shown in table 8.1. Break conditions are established using these registers. Table 8.1 Name User break address register H User break address register L User break address mask register H User break address mask register L User break bus cycle register User break control register Register Configuration Abbr. UBARH UBARL UBAMRH UBAMRL UBBR UBCR R/W R/W R/W R/W R/W R/W R/W Initial Value H'0000 H'0000 H'0000 H'0000 H'0000 H'0000 Address* H'FFFFEC00 H'FFFFEC02 H'FFFFEC04 H'FFFFEC06 H'FFFFEC08 Access Size 8, 16, 32 8, 16, 32 8, 16, 32 8, 16, 32 8, 16, 32 H'FFFFEC0A 8, 16, 32 Note: * In register access, three cycles are required for byte access and word access, and six cycles for longword access. 8.2 8.2.1 UBARH: Register Descriptions User Break Address Register (UBAR) Bit: 15 UBA31 14 UBA30 0 R/W 6 UBA22 0 R/W 13 UBA29 0 R/W 5 UBA21 0 R/W 12 UBA28 0 R/W 4 UBA20 0 R/W 11 UBA27 0 R/W 3 UBA19 0 R/W 10 UBA26 0 R/W 2 UBA18 0 R/W 9 UBA25 0 R/W 1 UBA17 0 R/W 8 UBA24 0 R/W 0 UBA16 0 R/W Initial value: R/W: Bit: 0 R/W 7 UBA23 Initial value: R/W: 0 R/W Rev.2.0, 07/03, page 121 of 960 UBARL: Bit: 15 UBA15 Initial value: R/W: Bit: 0 R/W 7 UBA7 Initial value: R/W: 0 R/W 14 UBA14 0 R/W 6 UBA6 0 R/W 13 UBA13 0 R/W 5 UBA5 0 R/W 12 UBA12 0 R/W 4 UBA4 0 R/W 11 UBA11 0 R/W 3 UBA3 0 R/W 10 UBA10 0 R/W 2 UBA2 0 R/W 9 UBA9 0 R/W 1 UBA1 0 R/W 8 UBA8 0 R/W 0 UBA0 0 R/W The user break address register (UBAR) consists of user break address register H (UBARH) and user break address register L (UBARL). Both are 16-bit readable/writable registers. UBARH stores the upper bits (bits 31 to 16) of the address of the break condition, while UBARL stores the lower bits (bits 15 to 0). UBARH and UBARL are initialized to H'0000 by a power-on reset and in module standby mode. They are not initialized in software standby mode. * UBARH Bits 15 to 0--User Break Address 31 to 16 (UBA31 to UBA16): These bits store the upper bit values (bits 31 to 16) of the address of the break condition. * UBARL Bits 15 to 0--User Break Address 15 to 0 (UBA15 to UBA0): These bits store the lower bit values (bits 15 to 0) of the address of the break condition. 8.2.2 User Break Address Mask Register (UBAMR) UBAMRH: Bit: 15 UBM31 Initial value: R/W: Bit: 0 R/W 7 UBM23 Initial value: R/W: 0 R/W 14 UBM30 0 R/W 6 UBM22 0 R/W 13 UBM29 0 R/W 5 UBM21 0 R/W 12 UBM28 0 R/W 4 UBM20 0 R/W 11 UBM27 0 R/W 3 UBM19 0 R/W 10 UBM26 0 R/W 2 UBM18 0 R/W 9 UBM25 0 R/W 1 UBM17 0 R/W 8 UBM24 0 R/W 0 UBM16 0 R/W Rev.2.0, 07/03, page 122 of 960 UBAMRL: Bit: 15 UBM15 Initial value: R/W: Bit: 0 R/W 7 UBM7 Initial value: R/W: 0 R/W 14 UBM14 0 R/W 6 UBM6 0 R/W 13 UBM13 0 R/W 5 UBM5 0 R/W 12 UBM12 0 R/W 4 UBM4 0 R/W 11 UBM11 0 R/W 3 UBM3 0 R/W 10 UBM10 0 R/W 2 UBM2 0 R/W 9 UBM9 0 R/W 1 UBM1 0 R/W 8 UBM8 0 R/W 0 UBM0 0 R/W The user break address mask register (UBAMR) consists of user break address mask register H (UBAMRH) and user break address mask register L (UBAMRL). Both are 16-bit readable/writable registers. UBAMRH designates whether to mask any of the break address bits established in UBARH, and UBAMRL designates whether to mask any of the break address bits established in UBARL. UBAMRH and UBAMRL are initialized to H'0000 by a power-on reset and in module standby mode. They are not initialized in software standby mode. * UBAMRH Bits 15 to 0--User Break Address Mask 31 to 16 (UBM31 to UBM16): These bits designate whether to mask the corresponding break address 31 to 16 bits (UBA31 to UBA16) established in UBARH. * UBAMRL Bits 15 to 0--User Break Address Mask 15 to 0 (UBM15 to UBM0): These bits designate whether to mask the corresponding break address 15 to 0 bits (UBA15 to UBA0) established in UBARL. Bit 15-0: UBMn 0 1 Note: n = 31 to 0 Description Break address UBAn is included in the break conditions (Initial value) Break address UBAn is not included in the break conditions Rev.2.0, 07/03, page 123 of 960 8.2.3 User Break Bus Cycle Register (UBBR) Bit: 15 -- Initial value: R/W: Bit: 0 R 7 CP1 Initial value: R/W: 0 R/W 14 -- 0 R 6 CP0 0 R/W 13 -- 0 R 5 ID1 0 R/W 12 -- 0 R 4 ID0 0 R/W 11 -- 0 R 3 RW1 0 R/W 10 -- 0 R 2 RW0 0 R/W 9 -- 0 R 1 SZ1 0 R/W 8 -- 0 R 0 SZ0 0 R/W The user break bus cycle register (UBBR) is a 16-bit readable/writable register that selects from among the following four break conditions: 1. CPU cycle/DMA cycle 2. Instruction fetch/data access 3. Read/write 4. Operand size (byte, word, longword) UBBR is initialized to H'0000 by a power on reset and in module standby mode. It is not initialized in software standby mode. * Bits 15 to 8--Reserved: These bits always read 0. The write value should always be 0. * Bits 7 and 6--CPU Cycle/DMA Cycle Select (CP1, CP0): These bits designate break conditions for CPU cycles or DMA cycles. Bit 7: CP1 0 Bit 6: CP0 0 1 1 0 1 Description No user break interrupt occurs Break on CPU cycles Break on DMA cycles Break on both CPU and DMA cycles (Initial value) Rev.2.0, 07/03, page 124 of 960 * Bits 5 and 4--Instruction Fetch/Data Access Select (ID1, ID0): These bits select whether to break on instruction fetch and/or data access cycles. Bit 5: ID1 0 Bit 4: ID0 0 1 1 0 1 Description No user break interrupt occurs Break on instruction fetch cycles Break on data access cycles Break on both instruction fetch and data access cycles (Initial value) * Bits 3 and 2--Read/Write Select (RW1, RW0): These bits select whether to break on read and/or write cycles. Bit 3: RW1 0 Bit 2: RW0 0 1 1 0 1 Description No user break interrupt occurs Break on read cycles Break on write cycles Break on both read and write cycles (Initial value) * Bits 1 and 0--Operand Size Select (SZ1, SZ0): These bits select operand size as a break condition. Bit 1: SZ1 0 Bit 0: SZ0 0 1 1 0 1 Description Operand size is not a break condition Break on byte access Break on word access Break on longword access (Initial value) Note: When breaking on an instruction fetch, clear the SZ0 bit to 0. All instructions are considered to be word-size accesses (even when there are instructions in on-chip memory and two instruction fetches are performed simultaneously in one bus cycle). Operand size is word for instructions or determined by the operand size specified for the CPU/DMAC data access. It is not determined by the bus width of the space being accessed. Rev.2.0, 07/03, page 125 of 960 8.2.4 User Break Control Register (UBCR) Bit: 15 -- Initial value: R/W: Bit: 0 R 7 -- Initial value: R/W: 0 R 14 -- 0 R 6 -- 0 R 13 -- 0 R 5 -- 0 R 12 -- 0 R 4 -- 0 R 11 -- 0 R 3 -- 0 R 10 -- 0 R 2 CKS1 0 R/W 9 -- 0 R 1 CKS0 0 R/W 8 -- 0 R 0 UBID 0 R/W The user break control register (UBCR) is a 16-bit readable/writable register that (1) enables or disables user break interrupts and (2) sets the pulse width of the UBCTRG signal output in the event of a break condition match. UBCR is initialized to H'0000 by a power-on reset and in module standby mode. It is not initialized in software standby mode. * Bits 15 to 3--Reserved: These bits always read 0. The write value should always be 0. * Bits 2 and 1--Clock Select 1 and 0 (CKS1, CKS0): These bits specify the pulse width of the UBCTRG signal output in the event of a condition match. Bit 2: CKS1 0 Bit 1: CKS0 0 1 1 0 1 Note: : Internal clock Description UBCTRG pulse width is UBCTRG pulse width is /4 UBCTRG pulse width is /8 UBCTRG pulse width is /16 (Initial value) * Bit 0--User Break Disable (UBID): Enables or disables user break interrupt request generation in the event of a user break condition match. Bit 0: UBID 0 1 Description User break interrupt request is enabled User break interrupt request is disabled (Initial value) Rev.2.0, 07/03, page 126 of 960 8.3 8.3.1 Operation Flow of the User Break Operation The flow from setting of break conditions to user break interrupt exception processing is described below: 1. The user break addresses are set in the user break address register (UBAR), the desired masked bits in the addresses are set in the user break address mask register (UBAMR) and the breaking bus cycle type is set in the user break bus cycle register (UBBR). If even one of the three groups of the UBBR's CPU cycle/DMA cycle select bits (CP1, CP0), instruction fetch/data access select bits (ID1, ID0), and read/write select bits (RW1, RW0) is set to 00 (no user break generated), no user break interrupt will be generated even if all other conditions are in agreement. When using user break interrupts, always be certain to establish bit conditions for all of these three groups. 2. The UBC uses the method shown in figure 8.2 to judge whether set conditions have been fulfilled. When the set conditions are satisfied, the UBC sends a user break interrupt request signal to the interrupt controller (INTC). At the same time, a condition match signal is output at the UBCTRG pin with the pulse width set in bits CKS1 and CKS0. 3. The interrupt controller checks the accepted user break interrupt request signal's priority level. The user break interrupt has priority level 15, so it is accepted only if the interrupt mask level in bits I3-I0 in the status register (SR) is 14 or lower. When the I3-I0 bit level is 15, the user break interrupt cannot be accepted but it is held pending until user break interrupt exception processing can be carried out. Consequently, user break interrupts within NMI exception service routines cannot be accepted, since the I3-I0 bit level is 15. However, if the I3-I0 bit level is changed to 14 or lower at the start of the NMI exception service routine, user break interrupts become acceptable thereafter. See section 7, Interrupt Controller (INTC), describes the handling of priority levels in greater detail. 4. The INTC sends the user break interrupt request signal to the CPU, which begins user break interrupt exception processing upon receipt. See section 7.4, Interrupt Operation, for details on interrupt exception processing. Rev.2.0, 07/03, page 127 of 960 UBARH/UBARL UBAMRH/UBAMRL 32 Internal address bits 31-0 CP1 32 32 CP0 32 32 CPU cycle DMA cycle ID1 ID0 Instruction fetch User break interrupt Data access RW1 RW0 Read cycle Write cycle SZ1 SZ0 Byte size Word size Longword size UBID Figure 8.2 Break Condition Judgment Method Rev.2.0, 07/03, page 128 of 960 8.3.2 Break on On-Chip Memory Instruction Fetch Cycle On-chip memory (on-chip ROM and/or RAM) is always accessed as 32 bits in one bus cycle. Therefore, two instructions can be retrieved in one bus cycle when fetching instructions from onchip memory. At such times, only one bus cycle is generated, but by setting the start addresses of both instructions in the user break address register (UBAR) it is possible to cause independent breaks. In other words, when wanting to effect a break using the latter of two addresses retrieved in one bus cycle, set the start address of that instruction in UBAR. The break will occur after execution of the former instruction. 8.3.3 Program Counter (PC) Values Saved Break on Instruction Fetch: The program counter (PC) value saved to the stack in user break interrupt exception processing is the address that matches the break condition. The user break interrupt is generated before the fetched instruction is executed. If a break condition is set in an instruction fetch cycle placed immediately after a delayed branch instruction (delay slot), or on an instruction that follows an interrupt-disabled instruction, however, the user break interrupt is not accepted immediately, but the break condition establishing instruction is executed. The user break interrupt is accepted after execution of the instruction that has accepted the interrupt. In this case, the PC value saved is the start address of the instruction that will be executed after the instruction that has accepted the interrupt. Break on Data Access (CPU/DMA): The program counter (PC) value is the top address of the next instruction after the last instruction executed before the user break exception processing started. When data access (CPU/DMA) is set as a break condition, the place where the break will occur cannot be specified exactly. The break will occur at the instruction fetched close to where the data access that is to receive the break occurs. 8.4 8.4.1 Examples of Use Break on CPU Instruction Fetch Cycle UBARH = H'0000 UBARL = H'0404 UBBR = H'0054 UBCR = H'0000 Address: H'00000404 Bus cycle: CPU, instruction fetch, read (operand size not included in conditions) Interrupt requests enabled 1. Register settings: Conditions set: A user break interrupt will occur before the instruction at address H'00000404. If it is possible for the instruction at H'00000402 to accept an interrupt, the user break exception processing Rev.2.0, 07/03, page 129 of 960 will be executed after execution of that instruction. The instruction at H'00000404 is not executed. The PC value saved is H'00000404. 2. Register settings: UBARH = H'0015 UBARL = H'389C UBBR = H'0058 UBCR = H'0000 Address: H'0015389C Bus cycle: CPU, instruction fetch, write (operand size not included in conditions) Interrupt requests enabled UBARH = H'0003 UBARL = H'0147 UBBR = H'0054 UBCR = H'0000 Address: H'00030147 Bus cycle: CPU, instruction fetch, read (operand size not included in conditions) Interrupt requests enabled Conditions set: A user break interrupt does not occur because the instruction fetch cycle is not a write cycle. 3. Register settings: Conditions set: A user break interrupt does not occur because the instruction fetch was performed for an even address. However, if the first instruction fetch address after the branch is an odd address set by these conditions, user break interrupt exception processing will be carried out after address error exception processing. 8.4.2 Break on CPU Data Access Cycle UBARH = H'0012 UBARL = H'3456 UBBR = H'006A UBCR = H'0000 Address: H'00123456 Bus cycle: CPU, data access, write, word Interrupt requests enabled UBARH = H'00A8 UBARL = H'0391 UBBR = H'0066 UBCR = H'0000 Address: H'00A80391 Bus cycle: CPU, data access, read, word Interrupt requests enabled 1. Register settings: Conditions set: A user break interrupt occurs when word data is written into address H'00123456. 2. Register settings: Conditions set: Rev.2.0, 07/03, page 130 of 960 A user break interrupt does not occur because the word access was performed on an even address. 8.4.3 Break on DMA Cycle UBARH = H'0076 UBARL = H'BCDC UBBR = H'00A7 UBCR = H'0000 Address: H'0076BCDC Bus cycle: DMA, data access, read, longword Interrupt requests enabled UBARH = H'0023 UBARL = H'45C8 UBBR = H'0094 UBCR = H'0000 Address: H'002345C8 Bus cycle: DMA, instruction fetch, read (operand size not included in conditions) Interrupt requests enabled 1. Register settings: Conditions set: A user break interrupt occurs when longword data is read from address H'0076BCDC. 2. Register settings: Conditions set: A user break interrupt does not occur because no instruction fetch is performed in the DMA cycle. 8.5 8.5.1 Usage Notes Simultaneous Fetching of Two Instructions Two instructions may be simultaneously fetched from on-chip memory. If a break condition is set on the second of these two instructions but the contents of the UBC break condition registers are changed so as to alter the break condition immediately after the first of the two instructions is fetched, a user break interrupt will still occur when the second instruction is fetched. 8.5.2 Instruction Fetches at Branches When a conditional branch instruction or TRAPA instruction causes a branch, the order of instruction fetching and execution is as follows: 1. When branching with a conditional branch instruction: BT and BF instructions When branching with a TRAPA instruction: TRAPA instruction Rev.2.0, 07/03, page 131 of 960 Instruction fetch order: Branch instruction fetch next instruction overrun fetch overrun fetch of instruction after next branch destination instruction fetch Instruction execution order: Branch instruction execution branch destination instruction execution 2. When branching with a delayed conditional branch instruction: BT/S and BF/S instructions Instruction fetch order: Branch instruction fetch next instruction fetch (delay slot) overrun fetch of instruction after next branch destination instruction fetch Instruction execution order: Branch instruction execution delay slot instruction execution branch destination instruction execution Thus, when a conditional branch instruction or TRAPA instruction causes a branch, the branch destination instruction will be fetched after an overrun fetch of the next instruction or the instruction after next. However, as the instruction that is the object of the break does not break until fetching and execution of the instruction have been confirmed, the overrun fetches described above do not become objects of a break. If data accesses are also included as break conditions in addition to instruction fetch breaks, a break will occur because the instruction overrun fetch is also regarded as satisfying the data break condition. 8.5.3 Contention between User Break and Exception Processing If a user break is set for the fetch of a particular instruction, and exception processing with higher priority than a user break is in contention and is accepted in the decode stage for that instruction (or the next instruction), user break exception processing may not be performed after completion of the higher-priority exception service routine (on return by RTE). Thus, if a user break condition is applied to the branch destination instruction fetch after a branch (BRA, BRAF, BT, BF, BT/S, BF/S, BSR, BSRF, JMP, JSR, RTS, RTE, exception processing), and that branch instruction accepts exception processing with higher priority than a user break interrupt, user break exception processing is not performed after completion of the higher-priority exception service routine. Therefore, a user break condition should not be set for the fetch of the branch destination instruction after a branch. 8.5.4 Break at Non-Delay Branch Instruction Jump Destination When a branch instruction with no delay slot (including exception processing) jumps to the jump destination instruction on execution of the branch, a user break will not be generated even if a user break condition has been set for the first jump destination instruction fetch. Rev.2.0, 07/03, page 132 of 960 8.5.5 User Break Trigger Output Information on internal bus condition matches monitored by the UBC is output as UBCTRG. The trigger width can be set with clock select bits 1 and 0 (CKS1, CKS0) in the user break control register (UBCR). If a condition matches occurs again during trigger output, the UBCTRG pin continues to output a low level, and outputs a pulse of the length set in bits CKS1 and CKS0 from the cycle in which the last condition match occurs. The trigger output conditions differ from those in the case of a user break interrupt when a CPU instruction fetch condition is satisfied. When a condition occurs in an overrun fetch instruction as described in section 8.5.2, Instruction Fetch at Branches, a user break interrupt is not requested but a trigger is output from the UBCTRG pin. In other CPU data accesses and DMAC bus cycles, pulse output is performed under conditions similar to user break interrupt conditions. Setting the user break interrupt disable (UBID) bit to 1 in UBCR enables trigger output to be monitored externally without requesting a user break interrupt. 8.5.6 Module Standby After a power-on reset the UBC is in the module standby state, in which the clock supply is halted. When using the UBC, the module standby state must be cleared before making UBC register settings. Module standby is controlled by the module standby control register (MSTCR). See section 24.2.3, Module Standby Control Register (MSTCR), for further details. Rev.2.0, 07/03, page 133 of 960 Rev.2.0, 07/03, page 134 of 960 Section 9 Bus State Controller (BSC) 9.1 Overview The bus state controller (BSC) divides up the address spaces and outputs control for various types of memory. This enables memories like SRAM and ROM to be linked directly to the chip without external circuitry, simplifying system design and enabling high-speed data transfer to be achieved in a compact system. 9.1.1 Features The BSC has the following features: * Address space is divided into four spaces A maximum linear 2 Mbytes for on-chip ROM effective mode, and a maximum 4 Mbytes for on-chip ROM disabled mode, for address space CS0 A maximum linear 4 Mbytes for each of address spaces CS1-CS3 Bus width can be selected for each space (8 or 16 bits) Wait states can be inserted by software for each space Wait state insertion with WAIT pin in external memory space access Outputs control signals for each space according to the type of memory connected * On-chip ROM and RAM interfaces On-chip RAM access of 32 bits in 1 state On-chip Rom access of 32 bits in 1 state for a read and 2 states for a write Rev.2.0, 07/03, page 135 of 960 9.1.2 Block Diagram Figure 9.1 shows the BSC block diagram. Bus interface On-chip memory control unit RAMER BCR1 - Area control unit BCR2 Memory control unit , BSC WCR: Wait control register RAMER: RAM emulation register BCR1: BCR2: Bus control register 1 Bus control register 2 Figure 9.1 BSC Block Diagram Rev.2.0, 07/03, page 136 of 960 Module bus Wait control unit WCR Internal bus 9.1.3 Pin Configuration Table 9.1 shows the bus state controller pin configuration. Table 9.1 Name Address bus Data bus Chip select Read Upper write Lower write Wait Bus request Bus acknowledge Pin Configuration Abbr. A21-A0 D15-D0 CS0-CS3 RD WRH WRL WAIT BREQ BACK I/O O I/O O O O O I I O Description Address output 16-bit data bus Chip select signals indicating the area being accessed Strobe that indicates the read cycle for ordinary space/multiplex I/O Strobe that indicates a write cycle to the upper 8 bits (D15-D8) Strobe that indicates a write cycle to the lower 8 bits (D7-D0) Wait state request signal Bus release request input Bus use enable output Note: When an 8-bit bus width is selected for external space, WRL is enabled. When a 16-bit bus width is selected for external space, WRH and WRL are enabled. 9.1.4 Register Configuration The BSC has four registers. These registers are used to control wait states, bus width, and interfaces with memories like ROM and SRAM, as well as refresh control. The register configurations are listed in table 9.2. All registers are 16 bits. All BSC registers are all initialized by a power-on reset and in hardware standby mode. Values are retained in a manual reset and in software standby mode. Table 9.2 Name Bus control register 1 Bus control register 2 Wait state control register RAM emulation register Register Configuration Abbr. BCR1 BCR2 WCR RAMER R/W R/W R/W R/W R/W Initial Value Address H'000F H'FFFF H'7777 H'0000 Access Size H'FFFFEC20 8, 16, 32 H'FFFFEC22 8, 16, 32 H'FFFFEC24 8, 16, 32 H'FFFFEC26 8, 16, 32 Note: In register access, three cycles are required for byte access and word access, and six cycles for longword access. Rev.2.0, 07/03, page 137 of 960 9.1.5 Address Map Figure 9.2 shows the address format used by the SH7055SF. A31-A24 A23, A22 A21 A0 Output address: Output from the address pins CS space selection: Decoded, outputs to when A31 to A24 = 00000000 Space selection: Not output externally; used to select the type of space On-chip ROM space or CS0 to CS3 space when 00000000 (H'00) Reserved (do not access) when 00000001 to 11111110 (H'01 to H'FE) On-chip peripheral module space or on-chip RAM space when 11111111 (H'FF) Figure 9.2 Address Format This chip uses 32-bit addresses: * Bits A31 to A24 are used to select the type of space and are not output externally. * Bits A23 and A22 are decoded and output as chip select signals (CS0 to CS3) for the corresponding areas when bits A31 to A24 are 00000000. * A21 to A0 are output externally. Rev.2.0, 07/03, page 138 of 960 Table 9.3 shows the address map. Table 9.3 Address Map * On-chip ROM enabled mode Address H'0000 0000 to H'000F FFFF H'0010 0000 to H'001F FFFF H'0020 0000 to H'003F FFFF H'0040 0000 to H'007F FFFF H'0080 0000 to H'00BF FFFF H'00C0 0000 to H'00FF FFFF H'0100 0000 to H'FFFE FFFF H'FFFF 0000 to H'FFFF BFFF Space On-chip ROM Reserved CS0 space CS1 space CS2 space CS3 space Reserved On-chip RAM Memory On-chip ROM Reserved External space External space External space External space Reserved On-chip RAM On-chip peripheral module 32 kB 8 kB 32 bits 8, 16 bits 2 MB 4 MB 4 MB 4 MB 8, 16 bits* 8, 16 bits* 8, 16 bits* 8, 16 bits* 1 1 1 1 Size 512 kB Bus Width 32 bits H'FFFF C000 to H'FFFF FFFF On-chip peripheral module * On-chip ROM disabled mode Address H'0000 0000 to H'003F FFFF H'0040 0000 to H'007F FFFF H'0080 0000 to H'00BF FFFF H'00C0 0000 to H'00FF FFFF H'0100 0000 to H'FFFE FFFF H'FFFF 0000 to H'FFFF BFFF Space CS0 space CS1 space CS2 space CS3 space Reserved On-chip RAM Memory External space External space External space External space Reserved On-chip RAM On-chip peripheral module 32 kB 8 kB 32 bits 8, 16 bits Size 4 MB 4 MB 4 MB 4 MB Bus Width 8, 16 bits* 8, 16 bits* 8, 16 bits* 8, 16 bits* 2 1 1 1 H'FFFF C000 to H'FFFF FFFF On-chip peripheral module Notes: *1. Selected by on-chip register (BCR1) settings. *2. Selected by the mode pin. Do not access reserved spaces. Operation cannot be guaranteed if they are accessed. Rev.2.0, 07/03, page 139 of 960 9.2 9.2.1 Description of Registers Bus Control Register 1 (BCR1) Bit: 15 -- Initial value: R/W: Bit: 0 R 7 -- Initial value: R/W: 0 R 14 -- 0 R 6 -- 0 R 13 -- 0 R 5 -- 0 R 12 -- 0 R 4 -- 0 R 11 -- 0 R 3 A3SZ 1 R/W 10 -- 0 R 2 A2SZ 1 R/W 9 -- 0 R 1 A1SZ 1 R/W 8 -- 0 R 0 A0SZ 1 R/W BCR1 is a 16-bit readable/writable register that specifies the bus size of the CS spaces. Write bits 15-0 of BCR1 during the initialization stage after a power-on reset, and do not change the values thereafter. In on-chip ROM enabled mode, do not access any of the CS spaces until after completion of register initialization. In on-chip ROM disabled mode, do not access any CS space other than CS0 until after completion of register initialization. BCR1 is initialized to H'000F by a power-on reset and in hardware standby mode. It is not initialized by a manual reset or in software standby mode. * Bits 15-4--Reserved: The write value should always be 0. Operation cannot be guaranteed if 1 is written to these bits. * Bit 3--CS3 Space Size Specification (A3SZ): Specifies the CS3 space bus size. A 0 setting specifies byte (8-bit) size, and a 1 setting specifies word (16-bit) size. Bit 3: A3SZ 0 1 Description Byte (8-bit) size Word (16-bit) size (Initial value) * Bit 2--CS2 Space Size Specification (A2SZ): Specifies the CS2 space bus size. A 0 setting specifies byte (8-bit) size, and a 1 setting specifies word (16-bit) size. Bit 2: A2SZ 0 1 Description Byte (8-bit) size Word (16-bit) size (Initial value) Rev.2.0, 07/03, page 140 of 960 * Bit 1--CS1 Space Size Specification (A1SZ): Specifies the CS1 space bus size. A 0 setting specifies byte (8-bit) size, and a 1 setting specifies word (16-bit) size. Bit 1: A1SZ 0 1 Description Byte (8-bit) size Word (16-bit) size (Initial value) * Bit 0--CS0 Space Size Specification (A0SZ): Specifies the CS0 space bus size A 0 setting specifies byte (8-bit) size, and a 1 setting specifies word (16-bit) size. Bit 0: A0SZ 0 1 Description Byte (8-bit) size Word (16-bit) size (Initial value) Note: A0SZ is valid only in on-chip ROM enabled mode. In on-chip ROM disabled mode, the CS0 space bus size is specified by the mode pin. 9.2.2 Bus Control Register 2 (BCR2) Bit: 15 IW31 Initial value: R/W: Bit: 1 R/W 7 CW3 Initial value: R/W: 1 R/W 14 IW30 1 R/W 6 CW2 1 R/W 13 IW21 1 R/W 5 CW1 1 R/W 12 IW20 1 R/W 4 CW0 1 R/W 11 IW11 1 R/W 3 SW3 1 R/W 10 IW10 1 R/W 2 SW2 1 R/W 9 IW01 1 R/W 1 SW1 1 R/W 8 IW00 1 R/W 0 SW0 1 R/W BCR2 is a 16-bit readable/writable register that specifies the number of idle cycles and CS signal assert extension of each CS space. BCR2 is initialized to H'FFFF by a power-on reset and in hardware standby mode. It is not initialized by a manual reset or in software standby mode. * Bits 15-8--Idles between Cycles (IW31, IW30, IW21, IW20, IW11, IW10, IW01, IW00): These bits specify idle cycles inserted between consecutive accesses when the second one is to a different CS area after a read. Idles are used to prevent data conflict between ROM (and other memories, which are slow to turn the read data buffer off), fast memories, and I/O interfaces. Even when access is to the same area, idle cycles must be inserted when a read access is followed immediately by a write access. The idle cycles to be inserted comply with Rev.2.0, 07/03, page 141 of 960 the area specification of the previous access. Refer to section 9.4, Waits between Access Cycles, for details. IW31, IW30 specify the idle between cycles for CS3 space; IW21, IW20 specify the idle between cycles for CS2 space; IW11, IW10 specify the idle between cycles for CS1 space and IW01, IW00 specify the idle between cycles for CS0 space. Bit 15: IW31 0 Bit 14: IW30 0 1 1 0 1 Description No CS3 space idle cycle Inserts one idle cycle Inserts two idle cycles Inserts three idle cycles (Initial value) Bit 13: IW21 0 Bit 12: IW20 0 1 Description No CS2 space idle cycle Inserts one idle cycle Inserts two idle cycles Inserts three idle cycles (Initial value) 1 0 1 Bit 11: IW11 0 Bit 10: IW10 0 1 Description No CS1 space idle cycle Inserts one idle cycle Inserts two idle cycles Inserts three idle cycles (Initial value) 1 0 1 Bit 9: IW01 0 Bit 8: IW00 0 1 Description No CS0 space idle cycle Inserts one idle cycle Inserts two idle cycles Inserts three idle cycles (Initial value) 1 0 1 * Bits 7-4--Idle Specification for Continuous Access (CW3, CW2, CW1, CW0): The continuous access idle specification makes insertions to clearly delineate the bus intervals by once negating the CSn signal when performing consecutive accesses to the same CS space. When a write immediately follows a read, the number of idle cycles inserted is the larger of the two values specified by IW and CW. Refer to section 9.4, Waits between Access Cycles, for details. Rev.2.0, 07/03, page 142 of 960 CW3 specifies the continuous access idles for CS3 space; CW2 specifies the continuous access idles for CS2 space; CW1 specifies the continuous access idles for CS1 space and CW0 specifies the continuous access idles for CS0 space. Bit 7: CW3 0 1 Description No CS3 space continuous access idle cycles One CS3 space continuous access idle cycle (Initial value) Bit 6: CW2 0 1 Description No CS2 space continuous access idle cycles One CS2 space continuous access idle cycle (Initial value) Bit 5: CW1 0 1 Description No CS1 space continuous access idle cycles One CS1 space continuous access idle cycle (Initial value) Bit 4: CW0 0 1 Description No CS0 space continuous access idle cycles One CS0 space continuous access idle cycle (Initial value) * Bits 3-0--CS Assert Extension Specification (SW3, SW2, SW1, SW0): The CS assert cycle extension specification is for making insertions to prevent extension of the RD signal, WRH signal, or WRL signal assert period beyond the length of the CSn signal assert period. Extended cycles insert one cycle before and after each bus cycle, which simplifies interfaces with external devices and also has the effect of extending the write data hold time. Refer to section 9.3.3, CS Assert Period Extension, for details. SW3 specifies the CS assert extension for CS3 space access; SW2 specifies the CS assert extension for CS2 space access; SW1 specifies the CS assert extension for CS1 space access and SW0 specifies the CS assert extension for CS0 space access. Bit 3: SW3 0 1 Description No CS3 space CS assert extension CS3 space CS assert extension Description No CS2 space CS assert extension CS2 space CS assert extension (Initial value) (Initial value) Bit 2: SW2 0 1 Rev.2.0, 07/03, page 143 of 960 Bit 1: SW1 0 1 Description No CS1 space CS assert extension CS1 space CS assert extension (Initial value) Bit 0: SW0 0 1 Description No CS0 space CS assert extension CS0 space CS assert extension (Initial value) Rev.2.0, 07/03, page 144 of 960 9.2.3 Wait Control Register (WCR) Bit: 15 W33 Initial value: R/W: Bit: 1 R/W 7 W13 Initial value: R/W: 1 R/W 14 W32 1 R/W 6 W12 1 R/W 13 W31 1 R/W 5 W11 1 R/W 12 W30 1 R/W 4 W10 1 R/W 11 W23 1 R/W 3 W03 1 R/W 10 W22 1 R/W 2 W02 1 R/W 9 W21 1 R/W 1 W01 1 R/W 8 W20 1 R/W 0 W00 1 R/W WCR is a 16-bit readable/writable register that specifies the number of wait cycles for each CS space. WCR is initialized to H'FFFF by a power-on reset and in hardware standby mode. It is not initialized by a manual reset or in software standby mode. * Bits 15-12--CS3 Space Wait Specification (W33, W32, W31, W30): These bits specify the number of waits for CS3 space access. Bit 15: W33 0 0 1 1 1 1 15 wait external wait input enabled (Initial value) Bit 14: W32 0 0 Bit 13: W31 0 0 Bit 12: W30 0 1 Description No wait (external wait input disabled) 1 wait external wait input enabled * Bits 11-8--CS2 Space Wait Specification (W23, W22, W21, W20): These bits specify the number of waits for CS2 space access. Bit 11: W23 0 0 1 1 1 1 15 wait external wait input enabled (Initial value) Bit 10: W22 0 0 Bit 9: W21 0 0 Bit 8: W20 0 1 Description No wait (external wait input disabled) 1 wait external wait input enabled * Bits 7-4--CS1 Space Wait Specification (W13, W12, W11, W10): These bits specify the number of waits for CS1 space access. Rev.2.0, 07/03, page 145 of 960 Bit 7: W13 0 0 1 Bit 6: W12 0 0 Bit 5: W11 0 0 Bit 4: W10 0 1 Description No wait (external wait input disabled) 1 wait external wait input enabled 1 1 1 15 wait external wait input enabled (Initial value) * Bits 3-0--CS0 Space Wait Specification (W03, W02, W01, W00): These bits specify the number of waits for CS0 space access. Bit 3: W03 0 0 1 1 1 1 15 wait external wait input enabled (Initial value) Bit 2: W02 0 0 Bit 1: W01 0 0 Bit 0: W00 0 1 Description No wait (external wait input disabled) 1 wait external wait input enabled 9.2.4 RAM Emulation Register (RAMER) Bit: 15 -- Initial value: R/W: Bit: 0 R 7 -- Initial value: R/W: 0 R 14 -- 0 R 6 -- 0 R 13 -- 0 R 5 -- 0 R 12 -- 0 R 4 -- 0 R 11 -- 0 R 3 RAMS 0 R/W 10 -- 0 R 2 RAM2 0 R/W 9 -- 0 R 1 RAM1 0 R/W 8 -- 0 R 0 RAM0 0 R/W The RAM emulation register (RAMER) is a 16-bit readable/writable register that selects the RAM area to be used when emulating realtime programming of flash memory. RAMER is initialized to H'0000 by a power-on reset and in hardware standby mode. It is not initialized by a manual reset or in software standby mode. Rev.2.0, 07/03, page 146 of 960 Note: To ensure correct operation of the RAM emulation function, the ROM for which RAM emulation is performed should not be accessed immediately after this register has been modified. Operation cannot be guaranteed if such an access is made. * Bits 15 to 4--Reserved: Only 0 should be written to these bits. Operation cannot be guaranteed if 1 is written. * Bit 3--RAM Select (RAMS): Used together with bits 2 to 0 to select or deselect flash memory emulation by RAM (table 9.4). When 1 is written to this bit, all flash memory blocks are write/erase-protected. This bit is ignored in modes with on-chip ROM disabled. * Bits 2 to 0--RAM Area Specification (RAM2 to RAM0): These bits are used together with the RAMS bit to designate the flash memory area to be overlapped onto RAM (table 9.4). Table 9.4 RAM Area H'FFFF6000 to H'FFFF6FFF H'00000000 to H'00000FFF H'00001000 to H'00001FFF H'00002000 to H'00002FFF H'00003000 to H'00003FFF H'00004000 to H'00004FFF H'00005000 to H'00005FFF H'00006000 to H'00006FFF H'00007000 to H'00007FFF *: Don't care RAM Area Setting Method Bit 3: RAMS Bit 2: RAM2 0 1 1 1 1 1 1 1 1 * 0 0 0 0 1 1 1 1 Bit 1: RAM1 * 0 0 1 1 0 0 1 1 Bit 0: RAM0 * 0 1 0 1 0 1 0 1 Rev.2.0, 07/03, page 147 of 960 9.3 Accessing External Space A strobe signal is output in external space accesses to provide primarily for SRAM or ROM direct connections. 9.3.1 Basic Timing Figure 9.3 shows the basic timing of external space access. External access bus cycles are performed in 2 states. T1 CK T2 Address CSn RD Read Data , Write Data Figure 9.3 Basic Timing of External Space Access Rev.2.0, 07/03, page 148 of 960 9.3.2 Wait State Control The number of wait states inserted into external space access states can be controlled using the WCR settings (figure 9.4). The specified number of TW cycles are inserted as software cycles at the timing shown in figure 9.4. T1 CK TW T2 Address Read Data , Write Data Figure 9.4 Wait State Timing of External Space Access (Software Wait Only) Rev.2.0, 07/03, page 149 of 960 When the wait is specified by software using WCR, the wait input WAIT signal from outside is sampled. Figure 9.5 shows the WAIT signal sampling. The WAIT signal is sampled at the clock rise one cycle before the clock rise when the Tw state shifts to the T2 state. When using external waits, use a WCR setting of 1 state or more when extending CS assertion, and 2 states or more otherwise. T1 CK Address TW TW TW0 T2 Read Data , Write Data Figure 9.5 Wait State Timing of External Space Access (Two Software Wait States + WAIT Signal Wait State) Rev.2.0, 07/03, page 150 of 960 9.3.3 CS Assert Period Extension Idle cycles can be inserted to prevent extension of the RD, WRH, or WRL signal assert period beyond the length of the CSn signal assert period by setting the SW3-SW0 bits of BCR2. This allows for flexible interfaces with external circuitry. The timing is shown in figure 9.6. Th and Tf cycles are added respectively before and after the ordinary cycle. Only CSn is asserted in these cycles; RD, WRH, and WRL signals are not. Further, data is extended up to the Tf cycle, which is effective for gate arrays and the like, which have slower write operations. Th CK T1 T2 Tf Address Read Data , Write Data Figure 9.6 CS Assert Period Extension Function Rev.2.0, 07/03, page 151 of 960 9.4 Waits between Access Cycles When a read from a slow device is completed, data buffers may not go off in time to prevent data conflicts with the next access. If there is a data conflict during memory access, the problem can be solved by inserting a wait in the access cycle. To enable detection of bus cycle starts, waits can be inserted between access cycles during continuous accesses of the same CS space by negating the CSn signal once. 9.4.1 Prevention of Data Bus Conflicts For the two cases of write cycles after read cycles, and read cycles for a different area after read cycles, waits are inserted so that the number of idle cycles specified by the IW31 to IW00 bits of BCR2 occur. When idle cycles already exist between access cycles, only the number of empty cycles remaining beyond the specified number of idle cycles are inserted. Figure 9.7 shows an example of idles between cycles. In this example, one idle between CSn space cycles has been specified, so when a CSm space write immediately follows a CSn space read cycle, one idle cycle is inserted. T1 CK Address T2 Tidle T1 T2 , Data CSn space read Idle cycle CSm space write Figure 9.7 Idle Cycle Insertion Example Rev.2.0, 07/03, page 152 of 960 IW31 and IW30 specify the number of idle cycles required after a CS3 space read either to read other external spaces, or for this chip, to perform write accesses. In the same manner, IW21 and IW20 specify the number of idle cycles after a CS2 space read, IW11 and IW10, the number after a CS1 space read, and IW01 and IW00, the number after a CS0 space read. 0 to 3 idle cycles can be specified. 9.4.2 Simplification of Bus Cycle Start Detection For consecutive accesses to the same CS space, waits are inserted to provide the number of idle cycles designated by bits CW3 to CW0 in BCR2. However, in the case of a write cycle after a read, the number of idle cycles inserted will be the larger of the two values designated by the IW and CW bits. When idle cycles already exist between access cycles, waits are not inserted. Figure 9.8 shows an example. A continuous access idle is specified for CSn space, and CSn space is consecutively write-accessed. T1 CK Address T2 Tidle T1 T2 , Data CSn space access Idle cycle CSn space access Figure 9.8 Same Space Consecutive Access Idle Cycle Insertion Example Rev.2.0, 07/03, page 153 of 960 9.5 Bus Arbitration The SH7058 has a bus arbitration function that, when a bus release request is received from an external device, releases the bus to that device. It also has three internal bus masters, the CPU, DMAC, and AUD. The priority ranking for determining bus right transfer between these bus masters is: Bus right request from external device > AUD > DMAC > CPU Therefore, an external device that generates a bus request is given priority even if the request is made during a DMAC burst transfer. The AUD does not acquire the bus during DMAC burst transfer, but at the end of the transfer. When the CPU has possession of the bus, the AUD has higher priority than the DMAC for bus acquisition. A bus request by an external device should be input at the BREQ pin. The signal indicating that the bus has been released is output from the BACK pin. Figure 9.9 shows the bus right release procedure. SH7055SF accepted Strobe pin: high-level output Address, data, strobe pin: high impedance Bus right release response Bus right release status = Low = Low External device Bus right request confirmation Bus right acquisition Figure 9.9 Bus Right Release Procedure Rev.2.0, 07/03, page 154 of 960 9.6 Memory Connection Examples Figures 9.10-9.13 show examples of the memory connections. 32 k x 8-bit ROM SH7055SF A0-A14 D0-D7 A0-A14 I/O0-I/O7 Figure 9.10 Example of 8-Bit Data Bus Width ROM Connection 256 k x 16-bit ROM SH7055SF A0 A1-A18 D0-D15 A0-A17 I/O0-I/O15 Figure 9.11 Example of 16-Bit Data Bus Width ROM Connection 128 k x 8-bit SRAM SH7055SF A0-A16 A0-A16 D0-D7 I/O0-I/O7 Figure 9.12 Example of 8-Bit Data Bus Width SRAM Connection Rev.2.0, 07/03, page 155 of 960 SH7055SF 128 k x 8-bit SRAM A0 A1-A17 D8-D15 A0-A16 I/O0-I/O7 D0-D7 A0-A16 I/O0-I/O7 Figure 9.13 Example of 16-Bit Data Bus Width SRAM Connection Rev.2.0, 07/03, page 156 of 960 Section 10 Direct Memory Access Controller (DMAC) 10.1 Overview The SH7055SF includes an on-chip four-channel direct memory access controller (DMAC). The DMAC can be used in place of the CPU to perform high-speed data transfers among external memories, memory-mapped external devices, and on-chip peripheral modules (except for the DMAC, BSC, and UBC). Using the DMAC reduces the burden on the CPU and increases the operating efficiency of the chip as a whole. 10.1.1 Features The DMAC has the following features: * Four channels * 4-Gbyte address space in the architecture * 8-, 16-, or 32-bit selectable data transfer length * Maximum of 16 M (6,777,216) transfers * Address modes Both the transfer source and transfer destination are accessed by address. There are two transfer modes: direct address and indirect address. Direct address transfer mode: Values set in a DMAC internal register indicate the accessed address for both the transfer source and transfer destination. Two bus cycles are required for one data transfer. Indirect address transfer mode: The value stored at the location pointed to by the address set in the DMAC internal transfer source register is used as the address. Operation is otherwise the same as for direct access. This function can only be set for channel 3. Four bus cycles are required for one data transfer. * Channel function: Dual address mode is supported on all channels. Channel 2 has a source address reload function that reloads the source address every fourth transfer. Direct address transfer mode or indirect address transfer mode can be specified for channel 3. * Reload function Enables automatic reloading of the value set in the first source address register every fourth DMA transfer. This function can be executed on channel 2 only. * Transfer requests There are two DMAC transfer activation requests, as indicated below. Requests from on-chip peripheral modules: Transfer requests from on-chip modules such as the SCI or A/D. These can be received by all channels. Auto-request: The transfer request is generated automatically within the DMAC. Rev.2.0, 07/03, page 157 of 960 * Selectable bus modes: Cycle-steal mode or burst mode * Fixed DMAC channel priority ranking * CPU can be interrupted when the specified number of data transfers are complete. 10.1.2 Block Diagram Figure 10.1 is a block diagram of the DMAC. DMAC module On-chip ROM Circuit control Register control Peripheral bus Internal bus SARn On-chip RAM On-chip peripheral module DARn DMATCRn Activation control CHCRn DMAOR HCAN0 ATU-II SCI0-SCI4 A/D converter 0-2 DEIn Request priority control External ROM External RAM External I/O (memory mapped) External bus Bus interface Bus state controller SARn: DARn: DMATCRn: CHCRn: DMAOR: n: DMA source address register DMA destination address register DMA transfer count register DMA channel control register DMA operation register 0, 1, 2, 3 Figure 10.1 DMAC Block Diagram Rev.2.0, 07/03, page 158 of 960 10.1.3 Register Configuration Table 10.1 summarizes the DMAC registers. The DMAC has a total of 17 registers. Each channel has four registers, and one overall DMAC control register is shared by all channels. Table 10.1 DMAC Registers Channel Name 0 DMA source address register 0 DMA destination address register 0 DMA transfer count register 0 DMA channel control register 0 1 DMA source address register 1 DMA destination address register 1 DMA transfer count register 1 DMA channel control register 1 2 DMA source address register 2 DMA destination address register 2 DMA transfer count register 2 DMA channel control register 2 Abbr. SAR0 DAR0 R/W R/W R/W Initial Value Undefined Undefined Undefined 1 Address Register Access Size Size 16, 32* 16, 32* 16, 32* 16, 32* 16, 32* 16, 32* 16, 32* 16, 32* 16, 32* 16, 32* 16, 32* 16, 32* 2 H'FFFFECC0 32 bits H'FFFFECC4 32 bits H'FFFFECC8 32 bits 2 DMATCR0 R/W CHCR0 SAR1 DAR1 R/W* R/W R/W 2 H'00000000 H'FFFFECCC 32 bits Undefined Undefined Undefined H'FFFFECD0 32 bits H'FFFFECD4 32 bits H'FFFFECD8 32 bits 2 2 2 DMATCR1 R/W CHCR1 SAR2 DAR2 R/W* R/W R/W 1 3 H'00000000 H'FFFFECDC 32 bits Undefined Undefined Undefined H'FFFFECE0 32 bits H'FFFFECE4 32 bits H'FFFFECE8 32 bits 2 2 2 DMATCR2 R/W CHCR2 R/W* 1 3 H'00000000 H'FFFFECEC 32 bits 2 Rev.2.0, 07/03, page 159 of 960 Table 10.1 DMAC Registers (cont) Channel Name 3 DMA source address register 3 DMA destination address register 3 DMA transfer count register 3 DMA channel control register 3 Shared DMA operation register Abbr. SAR3 DAR3 R/W R/W R/W Initial Value Undefined Undefined Undefined 1 Address Register Access Size Size 16, 32* 16, 32* 16, 32* 16, 32* 16* 4 2 H'FFFFECF0 32 bits H'FFFFECF4 32 bits H'FFFFECF8 32 bits 2 DMATCR3 R/W CHCR3 DMAOR R/W* R/W* 3 H'00000000 H'FFFFECFC 32 bits H'0000 H'FFFFECB0 16 bits 2 1 Notes: Word access to a register takes 3 cycles, and longword access 6 cycles. Do not attempt to access an empty address, as operation canot be guaranteed if this is done. *1 Write 0 after reading 1 in bit 1 of CHCR0-CHCR3 and in bits 1 and 2 of DMAOR to clear flags. No other writes are allowed. *2 For 16-bit access of SAR0-SAR3, DAR0-DAR3, and CHCR0-CHCR3, the 16-bit value on the side not accessed is held. *3 DMATCR has a 24-bit configuration: bits 0-23. Writing to the upper 8 bits (bits 24-31) is invalid, and these bits always read 0. *4 Do not use 32-bit access on DMAOR. 10.2 10.2.1 Register Descriptions DMA Source Address Registers 0-3 (SAR0-SAR3) DMA source address registers 0-3 (SAR0-SAR3) are 32-bit readable/writable registers that specify the source address of a DMA transfer. These registers have a count function, and during a DMA transfer, they indicate the next source address. Specify a 16-bit boundary when performing 16-bit data transfers, and a 32-bit boundary when performing 32-bit data transfers. Operation cannot be guaranteed if any other addresses are set. The initial value after a power-on reset and in standby mode is undefined. Rev.2.0, 07/03, page 160 of 960 Bit: 31 30 29 28 27 26 25 24 Initial value: R/W: Bit: -- R/W 23 -- R/W 22 -- R/W 21 -- R/W ... ... ... ... -- R/W ... ... ... ... -- R/W 2 -- R/W 1 -- R/W 0 Initial value: R/W: -- R/W -- R/W -- R/W -- R/W -- R/W -- R/W 10.2.2 DMA Destination Address Registers 0-3 (DAR0-DAR3) DMA destination address registers 0-3 (DAR0-DAR3) are 32-bit readable/writable registers that specify the destination address of a DMA transfer. These registers have a count function, and during a DMA transfer, they indicate the next destination address. Specify a 16-bit boundary when performing 16-bit data transfers, and a 32-bit boundary when performing 32-bit data transfers. Operation cannot be guaranteed if any other addresses are set. The value after a power-on reset and in standby mode is undefined. Bit: 31 30 29 28 27 26 25 24 Initial value: R/W: Bit: -- R/W 23 -- R/W 22 -- R/W 21 -- R/W ... ... ... ... -- R/W ... ... ... ... -- R/W 2 -- R/W 1 -- R/W 0 Initial value: R/W: -- R/W -- R/W -- R/W -- R/W -- R/W -- R/W 10.2.3 DMA Transfer Count Registers 0-3 (DMATCR0-DMATCR3) DMA transfer count registers 0-3 (DMATCR0-DMATCR3) are 24-bit read/write registers that specify the transfer count for the channel (byte count, word count, or longword count) in bits 23 to 0. Specifying H'000001 gives a transfer count of 1, while H'000000 gives the maximum setting, 16,777,216 transfers. During DMAC operation, these registers indicate the remaining number of transfers. The upper 8 bits of DMATCR always read 0. The write value, also, should always be 0. Rev.2.0, 07/03, page 161 of 960 The value after a power-on reset and in standby mode is undefined. Bit: 31 -- Initial value: R/W: Bit: 0 R 23 30 -- 0 R 22 29 -- 0 R 21 28 -- 0 R 20 27 -- 0 R 19 26 -- 0 R 18 25 -- 0 R 17 24 -- 0 R 16 Initial value: R/W: Bit: -- R/W 15 -- R/W 14 -- R/W 13 -- R/W 12 -- R/W 11 -- R/W 10 -- R/W 9 -- R/W 8 Initial value: R/W: Bit: -- R/W 7 -- R/W 6 -- R/W 5 -- R/W 4 -- R/W 3 -- R/W 2 -- R/W 1 -- R/W 0 Initial value: R/W: -- R/W -- R/W -- R/W -- R/W -- R/W -- R/W -- R/W -- R/W 10.2.4 DMA Channel Control Registers 0-3 (CHCR0-CHCR3) DMA channel control registers 0-3 (CHCR0-CHCR3) are 32-bit readable/writable registers that designate the operation and transmission of each channel. CHCR register bits are initialized to H'00000000 by a power-on reset and in standby mode. Bit: 31 -- Initial value: R/W: Bit: 0 R 23 -- Initial value: R/W: 0 R 30 -- 0 R 22 -- 0 R 29 -- 0 R 21 -- 0 R 28 DI 0 R/W* 20 RS4 0 R/W 2 27 -- 0 R 19 RS3 0 R/W 26 -- 0 R 18 RS2 0 R/W 25 -- 0 R 17 RS1 0 R/W* 1 24 RO 0 R/W* 16 RS0 0 R/W 2 Rev.2.0, 07/03, page 162 of 960 Bit: 15 -- 14 -- 0 R 6 -- 0 R 13 SM1 0 R/W 5 TS1 0 R/W 12 SM0 0 R/W 4 TS0 0 R/W 11 -- 0 R 3 TM 0 R/W 10 -- 0 R 2 IE 0 R/W 9 DM1 0 R/W 1 TE 0 R/(W)* 1 8 DM0 0 R/W 0 DE 0 R/W Initial value: R/W: Bit: 0 R 7 -- Initial value: R/W: 0 R Notes: *1. TE bit: Allows only a 0 write after reading 1. *2. The DI and RO bits may be absent, depending on the channel. * Bits 31-29, 27-25, 23-21, 15, 14, 11, 10, 7, 6--Reserved: These bits are always read as 0, and should only be written with 0. * Bit 28--Direct/Indirect Select (DI): Specifies either direct address mode operation or indirect address mode operation for the channel 3 source address. This bit is valid only in CHCR3. It always reads 0 in CHCR0-CHCR2, and should always be written with 0. Bit 28: DI 0 1 Description Direct access mode operation for channel 3 Indirect access mode operation for channel 3 (Initial value) * Bit 24--Source Address Reload (RO): Selects whether to reload the source address initial value during channel 2 transfer. This bit is valid only for channel 2. It always reads 0 in CHCR0, CHCR1, and CHCR3, and should always be written with 0. Bit 24: RO 0 1 Description Does not reload source address Reloads source address (Initial value) Rev.2.0, 07/03, page 163 of 960 * Bits 20-16--Resource Select 4-0 (RS4-RS0): These bits specify the transfer request source. Bit 20: RS4 0 Bit 19: RS3 0 Bit 18: RS2 0 Bit 17: RS1 0 Bit 16: RS0 0 1 1 0 1 1 0 0 1 1 0 1 1 0 0 0 1 1 0 1 1 0 0 1 1 0 1 1 0 0 0 0 1 1 0 1 1 0 0 1 1 0 1 1 0 0 0 1 1 0 1 1 0 0 1 1 0 1 Description No request* (Initial value) SCI0 transmission SCI0 reception SCI1 transmission SCI1 reception SCI2 transmission SCI2 reception SCI3 transmission SCI3 reception SCI4 transmission SCI4 reception On-chip A/D0 On-chip A/D1 On-chip A/D2 No request* HCAN0 (RM0) No request* ATU-II (ICI0A) ATU-II (ICI0B) ATU-II (ICI0C) ATU-II (ICI0D) ATU-II (CMI6A) ATU-II (CMI6B) ATU-II (CMI6C) ATU-II (CMI6D) ATU-II (CMI7A) ATU-II (CMI7B) ATU-II (CMI7C) ATU-II (CMI7D) No request* No request* Auto-request Note: * Setting prohibited. For details, see No.12 in section 10.5, Usage Notes. Rev.2.0, 07/03, page 164 of 960 * Bits 13 and 12--Source Address Mode 1, 0 (SM1, SM0): These bits specify increment/decrement of the DMA transfer source address. Bit 13: SM1 0 0 1 1 Bit 12: SM0 0 1 0 1 Description Source address fixed (Initial value) Source address incremented (+1 during 8-bit transfer, +2 during 16-bit transfer, +4 during 32-bit transfer) Source address decremented (-1 during 8-bit transfer, -2 during 16-bit transfer, -4 during 32-bit transfer) Setting prohibited When the transfer source is specified at an indirect address, specify in source address register 3 (SAR3) the actual storage address of the data to be transferred as the data storage address (indirect address). During indirect address mode, SAR3 obeys the SM1/SM0 setting for increment/decrement. In this case, SAR3's increment/decrement is fixed at +4/-4 or 0, irrespective of the transfer data size specified by TS1 and TS0. * Bits 9 and 8--Destination Address Mode 1, 0 (DM1, DM0): These bits specify increment/decrement of the DMA transfer source address. Bit 9: DM1 0 0 1 1 Bit 8: DM0 0 1 0 1 Description Destination address fixed (Initial value) Destination address incremented (+1 during 8-bit transfer, +2 during 16-bit transfer, +4 during 32-bit transfer) Destination address decremented (-1 during 8-bit transfer, -2 during 16-bit transfer, -4 during 32-bit transfer) Setting prohibited * Bits 5 and 4--Transfer Size 1, 0 (TS1, TS0): These bits specify the size of the data for transfer. Bit 5: TS1 0 0 1 1 Bit 4: TS0 0 1 0 1 Description Specifies byte size (8 bits) Specifies word size (16 bits) Specifies longword size (32 bits) Setting prohibited (Initial value) Rev.2.0, 07/03, page 165 of 960 * Bit 3--Transfer Mode (TM): Specifies the bus mode for data transfer. Bit 3: TM 0 1 Description Cycle-steal mode Burst mode (Initial value) * Bit 2--Interrupt Enable (IE): When this bit is set to 1, interrupt requests are generated after the number of data transfers specified in DMATCR (when TE = 1). Bit 2: IE 0 1 Description Interrupt request not generated on completion of DMATCR-specified number of transfers (Initial value) Interrupt request enabled on completion of DMATCR-specified number of transfers * Bit 1--Transfer End (TE): This bit is set to 1 after the number of data transfers specified by DMATCR. At this time, if the IE bit is set to 1, an interrupt request is generated. If data transfer ends before TE is set to 1 (for example, due to an NMI or address error, or clearing of the DE bit or DME bit of DMAOR) TE is not set to 1. With this bit set to 1, data transfer is disabled even if the DE bit is set to 1. Bit 1: TE 0 Description DMATCR-specified number of transfers not completed [Clearing condition] 0 write after TE = 1 read, power-on reset, standby mode 1 DMATCR-specified number of transfers completed (Initial value) * Bit 0--DMAC Enable (DE): DE enables operation in the corresponding channel. Bit 0: DE 0 1 Description Operation of the corresponding channel disabled Operation of the corresponding channel enabled (Initial value) Transfer is initiated if this bit is set to 1 when auto-request is specified (RS4-RS0 settings). With an on-chip module request, when a transfer request occurs after this bit is set to 1, transfer is initiated. If this bit is cleared during a data transfer, transfer is suspended. If the DE bit has been set, but TE = 1, then if the DME bit of DMAOR is 0, and the NMIF or AE bit of DMAOR is 1, the transfer enable state is not entered. Rev.2.0, 07/03, page 166 of 960 10.2.5 DMAC Operation Register (DMAOR) DMAOR is a 16-bit readable/writable register that controls the overall operation of the DMAC. Register values are initialized to H'0000 by a power-on reset and in standby mode. Bit: 15 -- Initial value: R/W: Bit: 0 R 7 -- Initial value: R/W: 0 R 14 -- 0 R 6 -- 0 R 13 -- 0 R 5 -- 0 R 12 -- 0 R 4 -- 0 R 11 -- 0 R 3 -- 0 R 10 -- 0 R 2 AE 0 R/(W)* 9 -- 0 R 1 NMIF 0 R/(W)* 8 -- 0 R 0 DME 0 R/W Note: * 0 write only is valid after 1 is read at the AE and NMIF bits. * Bits 15-3--Reserved: These bits are always read 0 and should always be written with 0. * Bit 2--Address Error Flag (AE): Indicates that an address error has occurred during DMA transfer. If this bit is set during a data transfer, transfers on all channels are suspended. The CPU cannot write a 1 to the AE bit. Clearing is effected by a 0 write after a 1 read. Bit 2: AE 0 Description No address error, DMA transfer enabled [Clearing condition] Write AE = 0 after reading AE = 1 1 Address error, DMA transfer disabled [Setting condition] Address error due to DMAC (Initial value) Rev.2.0, 07/03, page 167 of 960 * Bit 1--NMI Flag (NMIF): Indicates input of an NMI. This bit is set irrespective of whether the DMAC is operating or suspended. If this bit is set during a data transfer, transfers on all channels are suspended. The CPU is unable to write a 1 to the NMIF. Clearing is effected by a 0 write after a 1 read. Bit 1: NMIF 0 Description No NMI interrupt, DMA transfer enabled [Clearing condition] Write NMIF = 0 after reading NMIF = 1 1 NMI has occurred, DMC transfer disabled [Setting condition] NMI interrupt occurrence (Initial value) * Bit 0--DMAC Master Enable (DME): This bit enables activation of the entire DMAC. When the DME bit and DE bit of the CHCR register for the corresponding channel are set to 1, that channel is transfer-enabled. If this bit is cleared during a data transfer, transfers on all channels are suspended. Even when the DME bit is set, when the TE bit of CHCR is 1, or its DE bit is 0, transfer is disabled if the NMIF or AE bit in DMAOR is set to 1. Bit 0: DME 0 1 Description Operation disabled on all channels Operation enabled on all channels (Initial value) Rev.2.0, 07/03, page 168 of 960 10.3 Operation When there is a DMA transfer request, the DMAC starts the transfer according to the channel priority order; when the transfer end conditions are satisfied, it ends the transfer. Transfers can be requested in two modes: auto-request and on-chip peripheral module request. Transfer is performed only in dual address mode, and either direct or indirect address transfer mode can be used. The bus mode can be either burst or cycle-steal. 10.3.1 DMA Transfer Flow After the DMA source address registers (SAR), DMA destination address registers (DAR), DMA transfer count register (DMATCR), DMA channel control registers (CHCR), and DMA operation register (DMAOR) are set to the desired transfer conditions, the DMAC transfers data according to the following procedure: 1. The DMAC checks to see if transfer is enabled (DE = 1, DME = 1, TE = 0, NMIF = 0, AE = 0). 2. When a transfer request comes and transfer has been enabled, the DMAC transfers 1 transfer unit of data (determined by the TS0 and TS1 setting). For an auto-request, the transfer begins automatically when the DE bit and DME bit are set to 1. The DMATCR value will be decremented by 1 upon each transfer. The actual transfer flows vary by address mode and bus mode. 3. When the specified number of transfers have been completed (when DMATCR reaches 0), the transfer ends normally. If the IE bit of CHCR is set to 1 at this time, a DEI interrupt is sent to the CPU. 4. When an address error occurs in the DMAC or an NMI interrupt is generated, the transfer is aborted. Transfer is also aborted when the DE bit of CHCR or the DME bit of DMAOR is cleared to 0. Rev.2.0, 07/03, page 169 of 960 Figure 10.2 is a flowchart of this procedure. Start Initial settings (SAR, DAR, DMATCR, CHCR, DMAOR) DE, DME = 1 and NMIF, AE, TE = 0? Yes Transfer request occurs?*1 Yes No No *2 *3 Bus mode Transfer (1 transfer unit); DMATCR -M 1 DMATCR, SAR and DAR updated Does NMIF = 1, AE = 1, DE = 0, or DME = 0? Yes Transfer aborted DMATCR = 0? Yes No No DEI interrupt request (when IE = 1) Does NMIF = 1, AE = 1, DE = 0, or DME = 0? Yes Transfer ends No Normal end Notes: *1 In auto-request mode, transfer begins when NMIF, AE, and TE are all 0, and the DE and DME bits are set to 1. *2 Cycle-steal mode *3 Burst mode Figure 10.2 DMAC Transfer Flowchart Rev.2.0, 07/03, page 170 of 960 10.3.2 DMA Transfer Requests DMA transfer requests are generated in either the data transfer source or destination. Transfers can be requested in two modes: auto-request and on-chip peripheral module request. The request mode is selected in the RS4-RS0 bits of DMA channel control registers 0-3 (CHCR0-CHCR3). Auto-Request Mode: When there is no transfer request signal from an external source, as in a memory-to-memory transfer or a transfer between memory and an on-chip peripheral module unable to request a transfer, the auto-request mode allows the DMAC to automatically generate a transfer request signal internally. When the DE bits of CHCR0-CHCR3 and the DME bit of DMAOR are set to 1, the transfer begins (so long as the TE bits of CHCR0-CHCR3 and the NMIF and AE bits of DMAOR are all 0). On-Chip Peripheral Module Request Mode: In this mode a transfer is performed at the transfer request signal (interrupt request signal) of an on-chip peripheral module. As indicated in table 10.2, there are 26 transfer request signals: 12 from the advanced timer unit (ATU-II), which are compare match or input capture interrupts; the receive data full interrupts (RXI) and transmit data empty interrupts (TXI) of the five serial communication interfaces (SCI); the receive interrupt of HCAN0; and the A/D conversion end interrupts (ADI) of the three A/D converters. When DMA transfers are enabled (DE = 1, DME = 1, TE = 0, NMIF = 0, AE = 0), a transfer is performed upon the input of a transfer request signal. When the transfer request is set to RXI (transfer request because the SCI's receive data register is full), the transfer source must be the SCI's receive data register (RDR). When the transfer request is set to TXI (transfer request because the SCI's transmit data register is empty), the transfer destination must be the SCI's transmit data register (TDR). If the transfer request is set to the A/D converter, the data transfer source must be the A/D converter register; if set to HCAN0, the transfer source must be HCAN0 message data. Rev.2.0, 07/03, page 171 of 960 Table 10.2 Selecting On-Chip Peripheral Module Request Modes with the RS Bits DMAC Transfer Request Source SCI0 transmit block SCI0 receive block SCI1 transmit block SCI1 receive block SCI2 transmit block SCI2 receive block SCI3 transmit block SCI3 receive block SCI4 transmit block SCI4 receive block A/D0 RS4 0 RS3 0 RS2 0 RS1 0 RS0 1 DMAC Transfer Request Signal TXI0 (SCI0 transmitdata-empty transfer request) RXI0 (SCI0 receivedata-full transfer request) TXI1 (SCI1 transmitdata-empty transfer request) RXI1 (SCI1 receivedata-full transfer request) TXI2 (SCI2 transmitdata-empty transfer request) RXI2 (SCI2 receivedata-full transfer request) TXI3 (SCI3 transmitdata-empty transfer request) RXI3 (SCI3 receivedata-full transfer request) TXI4 (SCI4 transmitdata-empty transfer request) RXI4 (SCI4 receivedata-full transfer request) ADI0 (A/D0 conversion end interrupt) ADI1 (A/D1 conversion end interrupt) ADI2 (A/D2 conversion end interrupt) RM0 (HCAN0 receive interrupt) Transfer Source Donit care* Transfer Destination TDR0 Bus Mode Burst/cyclesteal Burst/cyclesteal Burst/cyclesteal Burst/cyclesteal Burst/cyclesteal Burst/cyclesteal Burst/cyclesteal Burst/cyclesteal Burst/cyclesteal Burst/cyclesteal Burst/cyclesteal Burst/cyclesteal Burst/cyclesteal Burst/cyclesteal 1 0 RDR0 Donit care* 1 Donit care* TDR1 1 0 0 RDR1 Donit care* 1 Donit care* TDR2 1 0 RDR2 Donit care* 1 Donit care* TDR3 1 0 0 0 RDR3 Donit care* 1 Donit care* TDR4 1 0 RDR4 Donit care* 1 ADDR0- ADDR11 ADDR12- ADDR23 ADDR24- ADDR31 Donit care* 1 0 0 A/D1 Donit care* 1 A/D2 Donit care* 1 1 HCAN0 MD0-MD15 Donit care* Rev.2.0, 07/03, page 172 of 960 Table 10.2 Selecting On-Chip Peripheral Module Request Modes with the RS Bits (cont) DMAC Transfer Request Source ATU-II ATU-II ATU-II ATU-II ATU-II RS4 1 RS3 0 RS2 0 RS1 0 1 RS0 1 0 1 DMAC Transfer Request Signal ICI0A (ICR0A input capture generation) ICI0B (ICR0B input capture generation) ICI0C (ICR0C input capture generation) ICI0D (ICR0D input capture generation) CMI6A (CYLR6A compare-match generation) CMI6B (CYLR6B compare-match generation) CMI6C (CYLR6C compare-match generation) CMI6D (CYLR6D compare-match generation) CMI7A (CYLR7A compare-match generation) CMI7B (CYLR7B compare-match generation) CMI7C (CYLR7C compare-match generation) CMI7D (CYLR7D compare-match generation) Transfer Source Donit care* Donit care* Donit care* Donit care* Donit care* Transfer Destination Donit care* Donit care* Donit care* Donit care* Donit care* Bus Mode Burst/cyclesteal Burst/cyclesteal Burst/cyclesteal Burst/cyclesteal Burst/cyclesteal Burst/cyclesteal Burst/cyclesteal Burst/cyclesteal Burst/cyclesteal Burst/cyclesteal Burst/cyclesteal Burst/cyclesteal 1 0 0 1 1 0 ATU-II Donit care* Donit care* 1 ATU-II Donit care* Donit care* 1 0 0 0 ATU-II Donit care* Donit care* 1 ATU-II Donit care* Donit care* 1 0 ATU-II Donit care* Donit care* 1 ATU-II Donit care* Donit care* 1 0 0 ATU-II Donit care* Donit care* SCI0, SCI1, SCI2, SCI3, SCI4: Serial communication interface channels 0-4 A/D0, A/D1, A/D2: A/D converter channels 0-2 HCAN0: Controller area network channel 0 ATU-II: Advanced timer unit TDR0, TDR1, TDR2, TDR3, TDR4: SCI0-SCI4 transmit data registers RDR0, RDR1, RDR2, RDR3, RDR4: SCI0-SCI4 receive data registers ADDR0-ADDR11: A/D0 data registers ADDR12-ADDR23: A/D1 data registers ADDR24-ADDR31: A/D2 data registers Rev.2.0, 07/03, page 173 of 960 MD0-MD15: HCAN0 message data Note: * External memory, memory-mapped external device, on-chip memory, on-chip peripheral module (excluding DMAC, BSC, and UBC) 10.3.3 Channel Priority When the DMAC receives simultaneous transfer requests on two or more channels, it selects a channel according to the following priority order: * CH0 > CH1 > CH2 > CH3 10.3.4 DMA Transfer Types The DMAC supports the transfers shown in table 10.3. It operates in dual address mode, in which both the transfer source and destination addresses are output. The dual address mode consists of a direct address mode, in which the output address value is the object of a direct data transfer, and an indirect address mode, in which the output address value is not the object of the data transfer, but the value stored at the output address becomes the transfer object address. The actual transfer operation timing varies with the bus mode. The DMAC has two bus modes: cycle-steal mode and burst mode. Table 10.3 Supported DMA Transfers Transfer Destination Transfer Source External memory Memory-mapped external device On-chip memory On-chip peripheral module External Memory Supported Supported Supported Supported Memory-Mapped External Device Supported Supported Supported Supported On-Chip Memory Supported Supported Supported Supported On-Chip Peripheral Module Supported Supported Supported Supported 10.3.5 Dual Address Mode Dual address mode is used for access of both the transfer source and destination by address. Transfer source and destination can be accessed either internally or externally. Dual address mode is subdivided into two other modes: direct address transfer mode and indirect address transfer mode. Rev.2.0, 07/03, page 174 of 960 Direct Address Transfer Mode: Data is read from the transfer source during the data read cycle, and written to the transfer destination during the write cycle, so transfer is conducted in two bus cycles. At this time, the transfer data is temporarily stored in the DMAC. With the kind of external memory transfer shown in figure 10.3, data is read from one of the memories by the DMAC during a read cycle, then written to the other external memory during the subsequent write cycle. Figure 10.4 shows the timing for this operation. 1st bus cycle DMAC SAR Address bus Memory Data bus DAR Transfer source module Transfer destination module Data buffer The SAR value is taken as the address, and data is read from the transfer source module and stored temporarily in the DMAC. 2nd bus cycle DMAC SAR Address bus Memory Data bus DAR Transfer source module Transfer destination module Data buffer The DAR value is taken as the address, and data stored in the DMAC's data buffer is written to the transfer destination module. Figure 10.3 Direct Address Operation in Dual Address Mode Rev.2.0, 07/03, page 175 of 960 CK Transfer source address Transfer destination address A21-A0 CSn D15-D0 RD WRH, WRL Figure 10.4 Direct Address Transfer Timing in Dual Address Mode Indirect Address Transfer Mode: In this mode the memory address storing the data actually to be transferred is specified in the DMAC internal transfer source address register (SAR3). Therefore, in indirect address transfer mode, the DMAC internal transfer source address register value is read first. This value is first stored in the DMAC. Next, the read value is output as the address, and the value stored at that address is again stored in the DMAC. Finally, the subsequent read value is written to the address specified by the transfer destination address register, ending one cycle of DMAC transfer. In indirect address mode (figure 10.5), the transfer destination, transfer source, and indirect address storage destination are all 16-bit external memory locations, and transfer in this example is conducted in 16-bit or 8-bit units. Timing for this transfer example is shown in figure 10.6. In indirect address mode, one NOP cycle (figure 10.6) is required until the data read as the indirect address is output to the address bus. When transfer data is 32-bit, the third and fourth bus cycles each need to be doubled, giving a required total of six bus cycles and one NOP cycle for the whole operation. Rev.2.0, 07/03, page 176 of 960 1st and 2nd bus cycles DMAC SAR3 Memory Data bus DAR3 Temporary buffer Data buffer Address bus Transfer source module Transfer destination module The SAR3 value is taken as the address, memory data is read, and the value is stored in the temporary buffer. Since the value read at this time is used as the address, it must be 32 bits. If data bus is 16 bits wide when accessed to an external memory space, two bus cycles are necessary. 3rd bus cycle DMAC SAR3 DAR3 Temporary buffer Data buffer Memory Address bus Data bus Transfer source module Transfer destination module The value in the temporary buffer is taken as the address, and data is read from the transfer source module to the data buffer. 4th bus cycle DMAC SAR3 DAR3 Temporary buffer Data buffer Memory Address bus Data bus Transfer source module Transfer destination module The DAR3 value is taken as the address, and the value in the data buffer is written to the transfer destination module. Note: Memory, transfer source, and transfer destination modules are shown here. In practice, any connection can be made as long as it is within the address space. Figure 10.5 Dual Address Mode and Indirect Address Operation (16-Bit-Width External Memory Space) Rev.2.0, 07/03, page 177 of 960 CK A21-A0 Transfer source address (H) Transfer source address (L) Indirect address Transfer destination address NOP D15-D0 Internal address bus Internal data bus DMAC indirect address buffer DMAC data buffer Indirect address (H) Indirect address (L) Transfer data Indirect address Transfer data Transfer data Transfer source address 1 NOP Indirect address 2 Transfer data Indirect address Transfer data , NOP cycle Data read cycle (3rd) Data write cycle (4th) Address read cycle (1st) (2nd) Notes: 1 The internal address bus is controlled by the port and does not change. 2 The DMAC does not latch the value until 32-bit data is read from the internal data bus. Figure 10.6 Dual Address Mode and Indirect Address Transfer Timing Example 1 External Memory Space External Memory Space (External memory space has 16-bit width) Rev.2.0, 07/03, page 178 of 960 Figure 10.7 shows an example of timing in indirect address mode when transfer source and indirect address storage locations are in internal memory, the transfer destination is an on-chip peripheral module with 2-cycle access space, and transfer data is 8-bit. Since the indirect address storage destination and the transfer source are in internal memory, these can be accessed in one cycle. The transfer destination is 2-cycle access space, so two data write cycles are required. One NOP cycle is required until the data read as the indirect address is output to the address bus. CK Internal address bus Transfer source address NOP Indirect address Transfer destination address Internal data bus DMAC indirect address buffer DMAC data buffer Indirect address NOP Transfer data Transfer data Indirect address Transfer data Address read cycle (1st) NOP cycle (2nd) Data read cycle (3rd) Data write cycle (4th) Figure 10.7 Dual Address Mode and Indirect Address Transfer Timing Example 2 Internal Memory Space Internal Memory Space Rev.2.0, 07/03, page 179 of 960 10.3.6 Bus Modes Select the appropriate bus mode in the TM bits of CHCR0-CHCR3. There are two bus modes: cycle-steal and burst. Cycle-Steal Mode: In cycle-steal mode, the bus right is given to another bus master after each one-transfer-unit (8-bit, 16-bit, or 32-bit) DMAC transfer. When the next transfer request occurs, the bus right is obtained from the other bus master and a transfer is performed for one transfer unit. When that transfer ends, the bus right is passed to the other bus master. This is repeated until the transfer end conditions are satisfied. Cycle-steal mode can be used with all categories of transfer destination, transfer source and transfer request. Figure 10.8 shows an example of DMA transfer timing in cycle-steal mode. Bus control returned to CPU Bus cycle CPU CPU CPU DMAC DMAC Read/Write CPU DMAC DMAC CPU Read/Write CPU Figure 10.8 DMA Transfer Timing Example in Cycle-Steal Mode Burst Mode: Once the bus right is obtained, transfer is performed continuously until the transfer end condition is satisfied. Figure 10.9 shows an example of DMA transfer timing in burst mode. Bus cycle CPU CPU CPU DMAC DMAC DMAC DMAC DMAC DMAC Read/Write Read/Write Read/Write CPU Figure 10.9 DMA Transfer Timing Example in Burst Mode Rev.2.0, 07/03, page 180 of 960 10.3.7 Relationship between Request Modes and Bus Modes by DMA Transfer Category Table 10.4 shows the relationship between request modes and bus modes by DMA transfer category. Table 10.4 Relationship between Request Modes and Bus Modes by DMA Transfer Category Address Mode Transfer Category Dual Request Mode 1 1 Bus* Mode B/C B/C B/C B/C B/C* B/C B/C* B/C B/C* B/C* 3 3 3 5 Transfer Usable Size (Bits) Channels 8/16/32 8/16/32 8/16/32 8/16/32 8/16/32* 8/16/32 8/16/32* 8/16/32 8/16/32* 8/16/32* 4 4 4 External memory and external memory Any* External memory and memory-mapped Any* external device Memory-mapped external device and memory-mapped external device External memory and on-chip memory External memory and on-chip peripheral module Memory-mapped external device and on-chip memory Memory-mapped external device and on-chip peripheral module On-chip memory and on-chip memory On-chip memory and on-chip peripheral module On-chip peripheral module and onchipperipheral module Any* Any* Any* Any* Any* Any* Any* Any* 0-3 0-3 0-3 0-3 0-3 0-3 0-3 0-3 0-3 0-3 1 1 2 1 2 1 2 2 3 4 B: Burst, C: Cycle-steal Notes: *1 Auto-request or on-chip peripheral module request enabled. However, in the case of an on-chip peripheral module request, it is not possible to specify the SCI, HCAN0, or A/D converter for the transfer request source. *2 Auto-request or on-chip peripheral module request possible. However, if the transfer request source is also the SCI, HCAN0, or A/D converter, the transfer source or transfer destination must be same as the transfer source. *3 When the transfer request source is the SCI, only cycle-steal mode is possible. *4 Access size permitted by the on-chip peripheral module register that is the transfer source or transfer destination. Rev.2.0, 07/03, page 181 of 960 10.3.8 Bus Mode and Channel Priorities If, for example, a transfer request is issued for channel 0 while transfer is in progress on lowerpriority channel 1 in burst mode, transfer is started immediately on channel 0. In this case, if channel 0 is set to burst mode, channel 1 transfer is continued after completion of all transfers on channel 0. If channel 0 is set to cycle-steal mode, channel 1 transfer is continued only if a channel 0 transfer request has not been issued; if a transfer request is issued, channel 0 transfer is started immediately. 10.3.9 Source Address Reload Function Channel 2 has a source address reload function. This returns to the first value set in the source address register (SAR2) every four transfers by setting the RO bit of CHCR2 to 1. Figure 10.10 illustrates this operation. Figure 10.11 is a timing chart for use of channel 2 only with the following transfer conditions set: burst mode, auto-request, 16-bit transfer data size, SAR2 incremented, DAR2 fixed, reload function on. DMAC DMAC control block RO bit = 1 CHCR2 Reload control Reload signal SAR2 (initial value) Reload signal 4th count SAR2 Figure 10.10 Source Address Reload Function Rev.2.0, 07/03, page 182 of 960 Address bus Transfer request Count signal DMATCR2 CK Internal address bus Internal data bus SAR2 DAR2 SAR2+2 DAR2 SAR2+4 DAR2 SAR2+6 DAR2 SAR2 DAR2 SAR2 data SAR2+2 data SAR2+4 data SAR2+6 data SAR2 data 1st channel 2 transfer SAR2 output DAR2 output 2nd channel 2 transfer SAR2+2 output DAR2 output 3rd channel 2 transfer SAR2+4 output DAR2 output 4th channel 2 transfer SAR2+6 output DAR2 output 5th channel 2 transfer SAR2 output DAR2 output After SAR2+6 output, SAR2 is reloaded Bus right is returned one time in four Figure 10.11 Source Address Reload Function Timing Chart The reload function can be executed whether the transfer data size is 8, 16, or 32 bits. DMATCR2, which specifies the number of transfers, is decremented by 1 at the end of every single-transfer-unit transfer, regardless of whether the reload function is on or off. Therefore, when using the reload function in the on state, a multiple of 4 must be specified in DMATCR2. Operation will not be guaranteed if any other value is set. Also, the counter which counts the occurrence of four transfers for address reloading is reset by clearing of the DME bit in DMAOR or the DE bit in CHCR2, setting of the transfer end flag (the TE bit in CHCR2), NMI input, and setting of the AE flag (address error generation in DMAC transfer), as well as by a reset and in software standby mode, but SAR2, DAR2, DMATCR2, and other registers are not reset. Consequently, when one of these sources occurs, there is a mixture of initialized counters and uninitialized registers in the DMAC, and incorrect operation may result if a restart is executed in this state. Therefore, when one of the above sources, other than TE setting, occurs during use of the address reload function, SAR, DAR2, and DMATCR2 settings must be carried out before reexecution. 10.3.10 DMA Transfer Ending Conditions The DMA transfer ending conditions vary for individual channels ending and for all channels ending together. Individual Channel Ending Conditions: There are two ending conditions. A transfer ends when the value of the channel's DMA transfer count register (DMATCR) is 0, or when the DE bit of the channel's CHCR is cleared to 0. Rev.2.0, 07/03, page 183 of 960 * When DMATCR is 0: When the DMATCR value becomes 0 and the corresponding channel's DMA transfer ends, the transfer end flag bit (TE) is set in CHCR. If the IE (interrupt enable) bit has been set, a DMAC interrupt (DEI) request is sent to the CPU. * When DE of CHCR is 0: Software can halt a DMA transfer by clearing the DE bit in the channel's CHCR. The TE bit is not set when this happens. Conditions for Ending on All Channels Simultaneously: Transfers on all channels end when the NMIF (NMI flag) bit or AE (address error flag) bit is set to 1 in DMAOR, or when the DME bit in DMAOR is cleared to 0. * When the NMIF or AE bit is set to 1 in DMAOR: When an NMI interrupt or DMAC address error occurs, the NMIF or AE bit is set to 1 in DMAOR and all channels stop their transfers. The DMAC obtains the bus right, and if these flags are set to 1 during execution of a transfer, DMAC halts operation when the transfer processing currently being executed ends, and transfers the bus right to the other bus master. Consequently, even if the NMIF or AE bit is set to 1 during a transfer, the DMA source address register (SAR), designation address register (DAR), and transfer count register (DMATCR) are all updated. The TE bit is not set. To resume the transfers after NMI interrupt or address error processing, the NMIF or AE flag must be cleared. To avoid restarting a transfer on a particular channel, clear its DE bit to 0 in CHCR. When the processing of a one-unit transfer is complete: In a dual address mode direct address transfer, even if an address error occurs or the NMI flag is set during read processing, the transfer will not be halted until after completion of the following write processing. In such a case, SAR, DAR, and DMATCR values are updated. In the same manner, the transfer is not halted in indirect address transfers until after the final write processing has ended. * When DME is cleared to 0 in DMAOR: Clearing the DME bit to 0 in DMAOR aborts the transfers on all channels. The TE bit is not set. 10.3.11 DMAC Access from CPU The space addressed by the DMAC is 3-cycle space. Therefore, when the CPU becomes the bus master and accesses the DMAC, a minimum of three basic clock cycles are required for one bus cycle. Also, since the DMAC is located in word space, while a word-size access to the DMAC is completed in one bus cycle, a longword-size access is automatically divided into two word accesses, requiring two bus cycles (six basic clock cycles). These two bus cycles are executed consecutively; a different bus cycle is never inserted between the two word accesses. This applies to both write accesses and read accesses. Rev.2.0, 07/03, page 184 of 960 10.4 10.4.1 Examples of Use Example of DMA Transfer between On-Chip SCI and External Memory In this example, on-chip serial communication interface channel 0 (SCI0) receive data is transferred to external memory using DMAC channel 0. Table 10.5 indicates the transfer conditions and the set values of each of the registers. Table 10.5 Transfer Conditions and Register Set Values for Transfer between On-chip SCI and External Memory Transfer Conditions Transfer source: RDR0 of on-chip SCI0 Transfer destination: external memory Transfer count: 64 times Transfer source address: fixed Transfer destination address: incremented Transfer request source: SCI0 (RDR0) Bus mode: cycle-steal Transfer unit: byte Interrupt request generation at end of transfer DMAC master enable on DMAOR H'0001 Register SAR0 DAR0 DMATCR0 CHCR0 Value H'FFFFF005 H'00400000 H'00000040 H'00020105 10.4.2 Example of DMA Transfer between A/D Converter and On-Chip Memory (Address Reload On) In this example, on-chip A/D converter channel 0 is the transfer source and on-chip memory is the transfer destination, and the address reload function is on. Table 10.6 indicates the transfer conditions and the set values of each of the registers. Rev.2.0, 07/03, page 185 of 960 Table 10.6 Transfer Conditions and Register Set Values for Transfer between A/D Converter and On-Chip Memory Transfer Conditions Transfer source: on-chip A/D converter ch1 (A/D1) Transfer destination: on-chip memory Transfer count: 128 times (reload count 32 times) Transfer source address: incremented Transfer destination address: incremented Transfer request source: A/D converter ch1 (A/D1) Bus mode: burst Transfer unit: byte Interrupt request generation at end of transfer DMAC master enable on DMAOR H'0001 Register SAR2 DAR2 DMATCR2 CHCR2 Value H'FFFFF820 H'FFFF6000 H'00000080 H'010C110D When address reload is on, the SAR2 value returns to its initially set value every four transfers. In the above example, when a transfer request is input from the A/D1, the byte-size data is first read in from the H'FFFFF820 register of on-chip A/D1 and that data is written to internal address H'FFFF6000. Because a byte-size transfer was performed, the SAR2 and DAR2 values at this point are H'FFFFF821 and H'FFFF6001, respectively. Also, because this is a burst transfer, the bus right remains secured, so continuous data transfer is possible. When four transfers are completed, if address reload is off, execution continues with the fifth and sixth transfers and the SAR2 value continues to increment from H'FFFFF824 to H'FFFFF825 to H'FFFFF826 and so on. However, when address reload is on, DMAC transfer is halted upon completion of the fourth transfer and the bus right request signal to the CPU is cleared. At this time, the value stored in SAR2 is not H'FFFFF823 H'FFFFF824, but H'FFFFF823 H'FFFFF820, a return to the initially set address. The DAR2 value always continues to be decremented regardless of whether address reload is on or off. The DMAC internal status, due to the above operation after completion of the fourth transfer, is indicated in table 10.7 for both address reload on and off. Rev.2.0, 07/03, page 186 of 960 Table 10.7 DMAC Internal Status Item SAR2 DAR2 DMATCR2 Bus right DMAC operation Interrupts Transfer request source flag clear Address Reload On H'FFFFF820 H'FFFF6004 H'0000007C Released Halted Not issued Executed Address Reload Off H'FFFFF824 H'FFFF6004 H'0000007C Retained Processing continues Not issued Not executed Notes: 1. Interrupts are executed until the DMATCR2 value becomes 0, and if the IE bit of CHCR2 is set to 1, are issued regardless of whether address reload is on or off. 2. If transfer request source flag clears are executed until the DMATCR2 value becomes 0, they are executed regardless of whether address reload is on or off. 3. Designate burst mode when using the address reload function. There are cases where abnormal operation will result if it is used in cycle-steal mode. 4. Designate a multiple of four for the DMATCR2 value when using the address reload function. There are cases where abnormal operation will result if anything else is designated. To execute transfers after the fifth transfer when address reload is on, have the transfer request source issue another transfer request signal. 10.4.3 Example of DMA Transfer between External Memory and SCI1 Transmitting Side (Indirect Address on) In this example, DMAC channel 3 is used, indirect address designated external memory is the transfer source, and the SCI1 transmitting side is the transfer destination. Table 10.8 indicates the transfer conditions and the set values of each of the registers. Rev.2.0, 07/03, page 187 of 960 Table 10.8 Transfer Conditions and Register Set Values for Transfer between External Memory and SCI1 Transmitting Side Transfer Conditions Transfer source: external memory Value stored in address H'00400000 Value stored in address H'00450000 Transfer destination: on-chip SCI TDR1 Transfer count: 10 times Transfer source address: incremented Transfer destination address: fixed Transfer request source: SCI1 (TDR1) Bus mode: cycle-steal Transfer unit: byte Interrupt request not generated at end of transfer DMAC master enable on DMAOR H'0001 Register SAR3 -- -- DAR3 DMATCR3 CHCR3 Value H'00400000 H'00450000 H'55 H'FFFFF00B H'0000000A H'10031001 When indirect address mode is on, the data stored in the address set in SAR is not used as the transfer source data. In the case of indirect addressing, the value stored in the SAR address is read, then that value is used as the address and the data read from that address is used as the transfer source data, then that data is stored in the address designated by DAR. In the table 10.8 example, when a transfer request from TDR1 of SCI1 is generated, a read of the address located at H'00400000, which is the value set in SAR3, is performed first. The data H'00450000 is stored at this H'00400000 address, and the DMAC first reads this H'00450000 value. It then uses this read value of H'00450000 as an address and reads the value of H'55 that is stored in the H'00450000 address. It then writes the value H'55 to address H'FFFFF00B designated by DAR3 to complete one indirect address transfer. With indirect addressing, the first executed data read from the address set in SAR3 always results in a longword size transfer regardless of the TS0 and TS1 bit designations for transfer data size. However, the transfer source address fixed and increment or decrement designations are according to the SM0 and SM1 bits. Consequently, despite the fact that the transfer data size designation is byte in this example, the SAR3 value at the end of one transfer is H'00400004. The write operation is exactly the same as an ordinary dual address transfer write operation. Rev.2.0, 07/03, page 188 of 960 10.5 Usage Notes 1. Only word (16-bit) access can be used on the DMA operation register (DMAOR). All other registers can be accessed in word (16-bit) or longword (32-bit) units. 2. When rewriting the RS0-RS4 bits of CHCR0-CHCR3, first clear the DE bit to 0 (clear the DE bit to 0 before modifying CHCR). 3. When an NMI interrupt is input, the NMIF bit of DMAOR is set even when the DMAC is not operating. 4. Clear the DME bit of DMAOR to 0 and make certain that any transfer request processing accepted by the DMAC has been completed before entering standby mode. 5. Do not access the DMAC, BSC, or UBC on-chip peripheral modules from the DMAC. 6. When activating the DMAC, make the CHCR settings as the final step. Abnormal operation may result if any other registers are set last. 7. After the DMATCR count becomes 0 and the DMA transfer ends normally, always write 0 to DMATCR, even when executing the maximum number of transfers on the same channel. Abnormal operation may result if this is not done. 8. Designate burst mode as the transfer mode when using the address reload function. Abnormal operation may result in cycle-steal mode. 9. Designate a multiple of four for the DMATCR value when using the address reload function, otherwise abnormal operation may result. 10. Do not access empty DMAC register addresses. Operation cannot be guaranteed when empty addresses are accessed. 11. If DMAC transfer is aborted by NMIF or AE setting, or DME or DE clearing, during DMAC execution with address reload on, the SAR2, DAR2, and DMATCR2 settings should be made before re-executing the transfer. The DMAC may not operate correctly if this is not done. 12. Do not set the DE bit to 1 while bits RS0 to RS4 in CHCR0 to CHCR3 are still set to "no request." Rev.2.0, 07/03, page 189 of 960 Rev.2.0, 07/03, page 190 of 960 Section 11 Advanced Timer Unit-II (ATU-II) 11.1 Overview The SH7055SF has an on-chip advanced timer unit-II (ATU-II) with one 32-bit timer channel and eleven 16-bit timer channels. 11.1.1 Features ATU-II features are summarized below. * Capability to process up to 65 pulse inputs and outputs * Prescaler Input clock to channels 0 and 10 scaled in 1 stage, input clock to channels 1 to 8 and 11 scaled in 2 stages 1/1 to 1/32 clock scaling possible in initial stage for channels 0 to 8, 10, and 11 1/1, 1/2, 1/4, 1/8, 1/16, or 1/32 scaling possible in second stage for channels 1 to 8 and 11 External clock TCLKA, TCLKB selection also possible for channels 1 to 5 and 11 Channels 1 to 5 enable TI10 pin input, multiple the TI10 pin input (correction), and select AGCK and AGCKM. * Channel 0 has four 32-bit input capture lines, allowing the following operations: Rising-edge, falling-edge, or both-edge detection selectable DMAC can be activated at capture timing Channel 10 compare-match signal can be captured as a trigger Interval interrupt generation function generates three interval interrupts as selected. CPU interruption or A/D converter (AD0, 1, 2) activation possible Capture interrupt and counter overflow interrupt can be generated * Channel 1 has one 16-bit output compare register, eight general registers, and one dedicated input capture register. The output compare register can also be selected for one-shot pulse offset in combination with the channel 8 down-counter. General registers (GR1A-H) can be used as input capture or output compare registers Waveform output by means of compare-match: Selection of 0 output, 1 output, or toggle output Input capture function: Rising-edge, falling-edge, or both-edge detection Channel 0 input signal (TI0A) can be captured as trigger Provision for forcible cutoff of channel 8 down-counters (DCNT8A-H) Compare-match interrupts/capture interrupts and counter overflow interrupts can be generated Rev.2.0, 07/03, page 191 of 960 * Channel 2 has eight 16-bit output compare registers, eight general registers, and one dedicated input capture register. The output compare registers can also be selected for one-shot pulse offset in combination with the channel 8 down-counter. General registers (GR2A-H) can be used as input capture or output compare registers Waveform output by means of compare-match: Selection of 0 output, 1 output, or toggle output Input capture function: Rising-edge, falling-edge, or both-edge detection Channel 0 input signal (TI0A) can be captured as trigger Provision for forcible cutoff of channel 8 down-counters (DCNT8I to P) Compare-match interrupts/capture interrupts and counter overflow interrupts can be generated * Channels 3 to 5 each have four general registers, allowing the following operations: Selection of input capture, output compare, PWM mode Waveform output by means of compare-match: Selection of 0 output, 1 output, or toggle output Input capture function: Rising-edge, falling-edge, or both-edge detection Channel 9 compare-match signal can be captured as trigger (channel 3 only) Compare-match interrupts/capture interrupts can be generated * Channels 6 and 7 have four 16-bit duty registers, four cycle registers, and four buffer registers, allowing the following operations: Any cycle and duty from 0 to 100% can be set Duty buffer register value transferred to duty register every cycle Interrupts can be generated every cycle Complementary PWM output can be set (channel 6 only) * Channel 8 has sixteen 16-bit down-counters for one-shot pulse output, allowing the following operations: One-shot pulse generation by down-counter Down-counter can be rewritten during count Interrupt can be generated at end of down-count Offset one-shot pulse function available Can be linked to channel 1 and 2 output compare functions Reload function can be set to eight 16-bit down counters (DCNT8I to DCNT8P) * Channel 9 has six event counters and six general registers, allowing the following operations: Event counters can be cleared by compare-match Rising-edge, falling-edge, or both-edge detection available for external input Compare-match signal can be input to channel 3 Rev.2.0, 07/03, page 192 of 960 * Channel 10 has a 32-bit output compare and input capture register, free-running counter, 16-bit free-running counter, output compare/input capture register, reload register, 8-bit event counter, and output compare register, and one 16-bit reload counter, allowing the following operations: Capture on external input pin edge input Reload count possible with 1/32, 1/64, 1/128, or 1/256 times the captured value Internal clock generated by reload counter underflow can be used as 16-bit free-running counter input Channels 1 and 2 free-running counter clearing capability * Channel 11 has one 16-bit free-running counter and two 16-bit general registers, allowing the following operations: Two general registers can be used for input capture/output compare Waveform output at compare match: 0 output, 1 output, and toggle output selectable Input capture function: Detection at rising edge, falling edge, and both edges Compare-match signal can be output at the APC by using a general register as a output compare register * High-speed access to internal 16-bit bus High-speed access to 16-bit bus for 16-bit registers: timer counters, compare registers, and capture registers * 75 interrupt sources Four input capture interrupt requests, one overflow interrupt request, and one interval interrupt request for channel 0 Sixteen dual input capture/compare-match interrupt requests and two counter overflow interrupt requests for channels 1 and 2 Twelve dual input capture/compare-match interrupt requests and three overflow interrupt requests for channels 3 to 5 Eight compare-match interrupts for channels 6 and 7 Sixteen one-shot end interrupt requests for channel 8 Six compare-match interrupts for channel 9 Two compare-match interrupts and one dual-function input capture/compare-match interrupt for channel 10 Two dual input capture/compare-match interrupt requests and one overflow interrupt request for channel 11 * Direct memory access controller (DMAC) activation The DMAC can be activated by a channel 0 input capture interrupt (ICI0A-D) The DMAC can be activated by a channel 6 cycle register 6 compare-match interrupt (CMI6A-D) The DMAC can be activated by a channel 7 cycle register 7 compare-match interrupt (CMI7A-D) Rev.2.0, 07/03, page 193 of 960 * A/D converter activation The A/D converter can be activated by detection of 1 in bits ITVA6-13 of the channel 0 interval interrupt request registers (ITVRR1, ITVRR2A, ITVRR2B) Table 11.1 lists the functions of the ATU-II. Rev.2.0, 07/03, page 194 of 960 Table 11.1 ATU-II Functions Item Counter configuration Clock sources Channel 0 -/32 Channel 1 (-/32) x (1/2n) (n = 0-5) TCLKA, TCLKB, AGCK, AGCKM Counters General registers Dedicated input capture Dedicated output compare PWM output TCNT0H, TCNT0L -- ICR0AH, ICR0AL, ICR0BH, ICR0BL, ICR0CH, ICR0CL, ICR0DH, ICR0DL -- TCNT1A, TCNT1B GR1A-H OSBR1 Channel 2 (-/32) x (1/2n) (n = 0-5) TCLKA, TCLKB, AGCK, AGCKM TCNT2A, TCNT2B GR2A-H OSBR2 Channels 3-5 (-/32) x (1/2n) (n = 0-5) TCLKA, TCLKB, AGCK, AGCKM TCNT3-5 GR3A-D, GR4A-D, GR5A-D -- OCR1 OCR2A-2H -- -- -- -- Duty: GR3A-C, GR4A-C, GR5A-C Cycle: GR3D, GR4D, GR5D Input pins I/O pins Output pins Counter clearing function Interrupt sources TI0A-D -- -- -- 6 sources Interval x 1, input capture x 4, overflow x 1 -- TIO1A-H -- -- 9 sources -- TIO2A-H -- -- 9 sources -- TIO3A-D, TIO4A-D, TIO5A-D -- O 15 sources Dual input capture/ Dual input capture/ Dual input capture/ compare-match x 8, compare-match x 8, compare-match x 12, overflow x 3 overflow x 1* overflow x 1 (* Same vector) Inter-channel and inter-module connection signals A/D converter activation by interval interrupt request, DMAC activation by input capture interrupt, channel 10 compare-match signal capture trigger input Compare-match signal trigger output to channel 8 one-shot pulse output down-counter Compare-match signal trigger output to channel 8 one-shot pulse output down-counter Channel 9 comparematch signal input to capture trigger (Channel 3 only) Channel 10 compare- Channel 10 comparematch signal counter match signal counter clear input clear input Rev.2.0, 07/03, page 195 of 960 Table 11.1 ATU-II Functions (cont) Item Counter configuration Clock sources Channels 6, 7 (-/32) x (1/2n) (n = 0-5) Counters TCNT6A-D, TCNT7A-D -- -- Channel 8 (-/32) x (1/2n) (n = 0-5) DCNT8A-P ECNT9A-F TCNT10AH, TCNT10AL, TCNT10B-H -- ICR10AH, ICR10AL GR10G OCR10AH, OCR10AL, OCR10B, NCR10, TCCLR10 CYLR6A-D, CYLR7A-D, DTR6A-D, DTR7A-D, BFR6A-D, BFR7A-D -- -- TO6A-D, TO7A-D O 8 sources -- -- -- -- Channel 9 -- Channel 10 (-/32) Channel 11 (-/32) x (1/2n) (n = 0-5) TCLKA, TCLKB TCNT11 General registers Dedicated input capture Dedicated output compare -- -- -- -- GR11A, GR11B -- -- -- GR9A-F -- PWM output Input pins I/O pins Output pins Counter clearing function Interrupt sources -- -- TO8A-P -- 16 sources TI9A-F -- -- O 6 sources TI10 -- -- O 3 sources -- TIO11A, TIO11B -- -- 3 sources Compare-match Underflow x 16 x8 Compare-match Compare-match Dual input x6 x 2, dual input capture/comparecapture/compare-match x 2, match x 1 overflow x 1 Compare-match signal channel 3 capture trigger output Compare-match Compare-match signal channel 0 signal output to capture trigger APC output Channel 1 and 2 counter clear output Inter-channel and inter-module connection signals DMAC activation Channel 1 and 2 compare-match compare-match signal output signal trigger input to one-shot pulse output down-counter O: Available --: Not available Rev.2.0, 07/03, page 196 of 960 11.1.2 Pin Configuration Table 11.2 shows the pin configuration of the ATU-II. When these external pin functions are used, the pin function controller (PFC) should also be set in accordance with the ATU-II settings. If there are a number of pins with the same function, make settings so that only one of the pins is used. For details, see section 20, Pin Function Controller (PFC). Table 11.2 ATU-II Pins Channel Common Name Clock input A Clock input B 0 Input capture 0A Input capture 0B Input capture 0C Input capture 0D 1 Input capture/output compare 1A Input capture/output compare 1B Input capture/output compare 1C Input capture/output compare 1D Input capture/output compare 1E Input capture/output compare 1F Input capture/output compare 1G Input capture/output compare 1H Abbreviation TCLKA TCLKB TI0A TI0B TI0C TI0D TIO1A TIO1B TIO1C TIO1D TIO1E TIO1F TIO1G TIO1H I/O Input Input Input Input Input Input Input/ output Input/ output Input/ output Input/ output Input/ output Input/ output Input/ output Input/ output Function External clock A input pin External clock B input pin ICR0AH, ICR0AL input capture input pin ICR0BH, ICR0BL input capture input pin ICR0CH, ICR0CL input capture input pin ICR0DH, ICR0DL input capture input pin GR1A output compare output/input capture input GR1B output compare output/input capture input GR1C output compare output/input capture input GR1D output compare output/input capture input GR1E output compare output/input capture input GR1F output compare output/input capture input GR1G output compare output/input capture input GR1H output compare output/input capture input Rev.2.0, 07/03, page 197 of 960 Table 11.2 ATU-II Pins (cont) Channel 2 Name Input capture/output compare 2A Input capture/output compare 2B Input capture/output compare 2C Input capture/output compare 2D Input capture/output compare 2E Input capture/output compare 2F Input capture/output compare 2G Input capture/output compare 2H 3 Input capture/output compare 3A Input capture/output compare 3B Input capture/output compare 3C Input capture/output compare 3D 4 Input capture/output compare 4A Input capture/output compare 4B Input capture/output compare 4C Input capture/output compare 4D Abbreviation TIO2A TIO2B TIO2C TIO2D TIO2E TIO2F TIO2G TIO2H TIO3A I/O Input/ output Input/ output Input/ output Input/ output Input/ output Input/ output Input/ output Input/ output Input/ output Input/ output Input/ output Input/ output Input/ output Input/ output Input/ output Input/ output Function GR2A output compare output/input capture input GR2B output compare output/input capture input GR2C output compare output/input capture input GR2D output compare output/input capture input GR2E output compare output/input capture input GR2F output compare output/input capture input GR2G output compare output/input capture input GR2H output compare output/input capture input GR3A output compare output/input capture input/PWM output pin (PWM mode) GR3B output compare output/input capture input/PWM output pin (PWM mode) GR3C output compare output/input capture input/PWM output pin (PWM mode) GR3D output compare output/input capture input GR4A output compare output/input capture input/PWM output pin (PWM mode) GR4B output compare output/input capture input/PWM output pin (PWM mode) GR4C output compare output/input capture input/PWM output pin (PWM mode) GR4D output compare output/input capture input TIO3B TIO3C TIO3D TIO4A TIO4B TIO4C TIO4D Rev.2.0, 07/03, page 198 of 960 Table 11.2 ATU-II Pins (cont) Channel 5 Name Input capture/output compare 5A Input capture/output compare 5B Input capture/output compare 5C Input capture/output compare 5D 6 Output compare 6A Output compare 6B Output compare 6C Output compare 6D 7 Output compare 7A Output compare 7B Output compare 7C Output compare 7D 8 One-shot pulse 8A One-shot pulse 8B One-shot pulse 8C One-shot pulse 8D One-shot pulse 8E One-shot pulse 8F One-shot pulse 8G One-shot pulse 8H One-shot pulse 8I One-shot pulse 8J One-shot pulse 8K One-shot pulse 8L One-shot pulse 8M One-shot pulse 8N Abbreviation TIO5A I/O Input/ output Input/ output Input/ output Input/ output Output Output Output Output Output Output Output Output Output Output Output Output Output Output Output Output Output Output Output Output Output Output Function GR5A output compare output/input capture input/PWM output pin (PWM mode) GR5B output compare output/input capture input/PWM output pin (PWM mode) GR5C output compare output/input capture input/PWM output pin (PWM mode) GR5D output compare output/input capture input PWM output pin PWM output pin PWM output pin PWM output pin PWM output pin PWM output pin PWM output pin PWM output pin One-shot pulse output pin One-shot pulse output pin One-shot pulse output pin One-shot pulse output pin One-shot pulse output pin One-shot pulse output pin One-shot pulse output pin One-shot pulse output pin One-shot pulse output pin One-shot pulse output pin One-shot pulse output pin One-shot pulse output pin One-shot pulse output pin One-shot pulse output pin TIO5B TIO5C TIO5D TO6A TO6B TO6C TO6D TO7A TO7B TO7C TO7D TO8A TO8B TO8C TO8D TO8E TO8F TO8G TO8H TO8I TO8J TO8K TO8L TO8M TO8N Rev.2.0, 07/03, page 199 of 960 Table 11.2 ATU-II Pins (cont) Channel 8 Name One-shot pulse 8O One-shot pulse 8P 9 Event input 9A Event input 9B Event input 9C Event input 9D Event input 9E Event input 9F 10 11 Input capture Input capture/output compare 11A Input capture/output compare 11B Abbreviation TO8O TO8P TI9A TI9B TI9C TI9D TI9E TI9F TI10 TIO11A TIO11B I/O Output Output Input Input Input Input Input Input Input Input/ output Input/ output Function One-shot pulse output pin One-shot pulse output pin GR9A event input GR9B event input GR9C event input GR9D event input GR9E event input GR9F event input ICR10AH, ICR10AL input capture input GR11A output compare output/input capture input GR11B output compare output/input capture input Rev.2.0, 07/03, page 200 of 960 11.1.3 Register Configuration Table 11.3 summarizes the ATU-II registers. Table 11.3 ATU-II Registers Channel Name Common Timer start register 1 Timer start register 2 Timer start register 3 Prescaler register 1 Prescaler register 2 Prescaler register 3 Prescaler register 4 0 Free-running counter 0H Free-running counter 0L Input capture register 0AH Input capture register 0AL Input capture register 0BH Input capture register 0BL Input capture register 0CH Input capture register 0CL Input capture register 0DH Input capture register 0DL Abbreviation R/W TSTR1 TSTR2 TSTR3 PSCR1 PSCR2 PSCR3 PSCR4 TCNT0H TCNT0L ICR0AH ICR0AL ICR0BH ICR0BL ICR0CH ICR0CL ICR0DH ICR0DL R/W R/W R/W R/W R/W R/W R/W R/W R/W R R R R R R R R R/W R/W Initial Value H'00 H'00 H'00 H'00 H'00 H'00 H'00 Address H'FFFFF401 H'FFFFF400 H'FFFFF402 H'FFFFF404 H'FFFFF406 H'FFFFF408 H'FFFFF40A 32 11.2.15 8 11.2.2 Access Section Size (Bits) No. 8, 16, 32 11.2.1 H'0000 H'FFFFF430 H'0000 H'0000 H'FFFFF434 H'0000 H'0000 H'FFFFF438 H'0000 H'0000 H'FFFFF43C H'0000 H'0000 H'FFFFF420 H'0000 H'00 H'00 H'FFFFF424 H'FFFFF426 11.2.19 Timer interval interrupt ITVRR1 request register 1 Timer interval interrupt ITVRR2A request register 2A 8 11.2.7 Rev.2.0, 07/03, page 201 of 960 Table 11.3 ATU-II Registers (cont) Channel Name 0 Abbreviation R/W R/W R/W Initial Value H'00 H'00 Address H'FFFFF428 H'FFFFF42A Access Section Size (Bits) No. 8 11.2.7 11.2.4 11.2.5 11.2.6 16 11.2.15 Timer interval interrupt ITVRR2B request register 2B Timer I/O control register TIOR0 Timer status register 0 TSR0 Timer interrupt enable register 0 1 Free-running counter 1A Free-running counter 1B General register 1A General register 1B General register 1C General register 1D General register 1E General register 1F General register 1G General register 1H Output compare register 1 Offset base register 1 Timer I/O control register 1A Timer I/O control register 1B Timer I/O control register 1C Timer I/O control register 1D Timer control register 1A Timer control register 1B TIER0 TCNT1A TCNT1B GR1A GR1B GR1C GR1D GR1E GR1F GR1G GR1H OCR1 OSBR1 TIOR1A TIOR1B TIOR1C TIOR1D TCR1A TCR1B R/(W)* H'0000 H'FFFFF42C 16 R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R R/W R/W R/W R/W R/W R/W H'0000 H'FFFFF42E H'0000 H'FFFFF440 H'0000 H'FFFFF442 H'FFFF H'FFFFF444 H'FFFF H'FFFFF446 H'FFFF H'FFFFF448 H'FFFF H'FFFFF44A H'FFFF H'FFFFF44C H'FFFF H'FFFFF44E H'FFFF H'FFFFF450 H'FFFF H'FFFFF452 H'FFFF H'FFFFF454 H'0000 H'FFFFF456 H'00 H'00 H'00 H'00 H'00 H'00 H'FFFFF459 H'FFFFF458 H'FFFFF45B H'FFFFF45A H'FFFFF45D H'FFFFF45C 8, 16 11.2.20 11.2.18 11.2.21 11.2.4 11.2.3 Rev.2.0, 07/03, page 202 of 960 Table 11.3 ATU-II Registers (cont) Channel Name 1 Timer status register 1A Timer status register 1B Timer interrupt enable register 1A Timer interrupt enable register 1B Trigger mode register 2 Free-running counter 2A Free-running counter 2B General register 2A General register 2B General register 2C General register 2D General register 2E General register 2F General register 2G General register 2H Output compare register 2A Output compare register 2B Output compare register 2C Output compare register 2D Output compare register 2E Output compare register 2F Abbreviation R/W TSR1A TSR1B TIER1A TIER1B TRGMDR TCNT2A TCNT2B GR2A GR2B GR2C GR2D GR2E GR2F GR2G GR2H OCR2A OCR2B OCR2C OCR2D OCR2E OCR2F Initial Value Address Access Section Size (Bits) No. 11.2.5 R/(W)* H'0000 H'FFFFF45E 16 R/(W)* H'0000 H'FFFFF460 R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W H'0000 H'FFFFF462 H'0000 H'FFFFF464 H'00 H'FFFFF466 8 16 11.2.6 11.2.8 11.2.15 H'0000 H'FFFFF600 H'0000 H'FFFFF602 H'FFFF H'FFFFF604 H'FFFF H'FFFFF606 H'FFFF H'FFFFF608 H'FFFF H'FFFFF60A H'FFFF H'FFFFF60C H'FFFF H'FFFFF60E H'FFFF H'FFFFF610 H'FFFF H'FFFFF612 H'FFFF H'FFFFF614 H'FFFF H'FFFFF616 H'FFFF H'FFFFF618 H'FFFF H'FFFFF61A H'FFFF H'FFFFF61C H'FFFF H'FFFFF61E 11.2.20 11.2.18 Rev.2.0, 07/03, page 203 of 960 Table 11.3 ATU-II Registers (cont) Channel Name 2 Output compare register 2G Output compare register 2H Offset base register 2 Timer I/O control register 2A Timer I/O control register 2B Timer I/O control register 2C Timer I/O control register 2D Timer control register 2A Timer control register 2B Timer status register 2A Timer status register 2B Timer interrupt enable register 2A Timer interrupt enable register 2B 3-5 Abbreviation R/W OCR2G OCR2H OSBR2 TIOR2A TIOR2B TIOR2C TIOR2D TCR2A TCR2B TSR2A TSR2B TIER2A TIER2B R/W R/W R R/W R/W R/W R/W R/W R/W Initial Value Address Access Section Size (Bits) No. 16 11.2.18 H'FFFF H'FFFFF620 H'FFFF H'FFFFF622 H'0000 H'FFFFF624 H'00 H'00 H'00 H'00 H'00 H'00 H'FFFFF627 H'FFFFF626 H'FFFFF629 H'FFFFF628 H'FFFFF62B H'FFFFF62A 11.2.21 8, 16 11.2.4 11.2.3 R/(W)* H'0000 H'FFFFF62C 16 R/(W)* H'0000 H'FFFFF62E R/W R/W H'0000 H'FFFFF630 H'0000 H'FFFFF632 16 11.2.5 11.2.6 Timer status register 3 TSR3 Timer interrupt enable register 3 Timer mode register TIER3 TMDR R/(W)* H'0000 H'FFFFF480 R/W R/W R/W R/W R/W R/W R/W H'0000 H'FFFFF482 H'00 H'FFFFF484 11.2.5 11.2.6 8 11.2.9 11.2.15 11.2.20 3 Free-running counter 3 TCNT3 General register 3A General register 3B General register 3C General register 3D GR3A GR3B GR3C GR3D H'0000 H'FFFFF4A0 16 H'FFFF H'FFFFF4A2 H'FFFF H'FFFFF4A4 H'FFFF H'FFFFF4A6 H'FFFF H'FFFFF4A8 Rev.2.0, 07/03, page 204 of 960 Table 11.3 ATU-II Registers (cont) Channel Name 3 Timer I/O control register 3A Timer I/O control register 3B Abbreviation R/W TIOR3A TIOR3B R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Initial Value H'00 H'00 H'00 Address Access Section Size (Bits) No. 11.2.4 H'FFFFF4AB 8, 16 H'FFFFF4AA H'FFFFF4AC 8 Timer control register 3 TCR3 4 Free-running counter 4 TCNT4 General register 4A General register 4B General register 4C General register 4D Timer I/O control register 4A Timer I/O control register 4B GR4A GR4B GR4C GR4D TIOR4A TIOR4B 11.2.3 11.2.15 11.2.20 H'0000 H'FFFFF4C0 16 H'FFFF H'FFFFF4C2 H'FFFF H'FFFFF4C4 H'FFFF H'FFFFF4C6 H'FFFF H'FFFFF4C8 H'00 H'00 H'00 H'FFFFF4CB 8, 16 H'FFFFF4CA H'FFFFF4CC 8 11.2.4 Timer control register 4 TCR4 5 Free-running counter 5 TCNT5 General register 5A General register 5B General register 5C General register 5D Timer I/O control register 5A Timer I/O control register 5B GR5A GR5B GR5C GR5D TIOR5A TIOR5B 11.2.3 11.2.15 11.2.20 H'0000 H'FFFFF4E0 16 H'FFFF H'FFFFF4E2 H'FFFF H'FFFFF4E4 H'FFFF H'FFFFF4E6 H'FFFF H'FFFFF4E8 H'00 H'00 H'00 H'FFFFF4EB 8, 16 H'FFFFF4EA H'FFFFF4EC 8 16 11.2.4 Timer control register 5 TCR5 6 Free-running counter 6A Free-running counter 6B Free-running counter 6C Free-running counter 6D TCNT6A TCNT6B TCNT6C TCNT6D 11.2.3 11.2.15 H'0001 H'FFFFF500 H'0001 H'FFFFF502 H'0001 H'FFFFF504 H'0001 H'FFFFF506 Rev.2.0, 07/03, page 205 of 960 Table 11.3 ATU-II Registers (cont) Channel Name 6 Cycle register 6A Cycle register 6B Cycle register 6C Cycle register 6D Buffer register 6A Buffer register 6B Buffer register 6C Buffer register 6D Duty register 6A Duty register 6B Duty register 6C Duty register 6D Timer control register 6A Timer control register 6B Abbreviation R/W CYLR6A CYLR6B CYLR6C CYLR6D BFR6A BFR6B BFR6C BFR6D DTR6A DTR6B DTR6C DTR6D TCR6A TCR6B R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Initial Value Address Access Section Size (Bits) No. 16 11.2.22 H'FFFF H'FFFFF508 H'FFFF H'FFFFF50A H'FFFF H'FFFFF50C H'FFFF H'FFFFF50E H'FFFF H'FFFFF510 H'FFFF H'FFFFF512 H'FFFF H'FFFFF514 H'FFFF H'FFFFF516 H'FFFF H'FFFFF518 H'FFFF H'FFFFF51A H'FFFF H'FFFFF51C H'FFFF H'FFFFF51E H'00 H'00 H'FFFFF521 H'FFFFF520 11.2.23 11.2.24 8, 16 11.2.3 Timer status register 6 TSR6 Timer interrupt enable register 6 PWM mode register 7 Free-running counter 7A Free-running counter 7B Free-running counter 7C Free-running counter 7D Cycle register 7A Cycle register 7B Cycle register 7C Cycle register 7D TIER6 PMDR TCNT7A TCNT7B TCNT7C TCNT7D CYLR7A CYLR7B CYLR7C CYLR7D R/(W)* H'0000 H'FFFFF522 R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W H'0000 H'FFFFF524 H'00 H'FFFFF526 16 11.2.5 11.2.6 8 16 11.2.10 11.2.15 H'0001 H'FFFFF580 H'0001 H'FFFFF582 H'0001 H'FFFFF584 H'0001 H'FFFFF586 H'FFFF H'FFFFF588 H'FFFF H'FFFFF58A H'FFFF H'FFFFF58C H'FFFF H'FFFFF58E 11.2.22 Rev.2.0, 07/03, page 206 of 960 Table 11.3 ATU-II Registers (cont) Channel Name 7 Buffer register 7A Buffer register 7B Buffer register 7C Buffer register 7D Duty register 7A Duty register 7B Duty register 7C Duty register 7D Timer control register 7A Timer control register 7B Timer status register 7 Timer interrupt enable register 7 8 Down-counter 8A Down-counter 8B Down-counter 8C Down-counter 8D Down-counter 8E Down-counter 8F Down-counter 8G Down-counter 8H Down-counter 8I Down-counter 8J Down-counter 8K Down-counter 8L Down-counter 8M Down-counter 8N Down-counter 8O Down-counter 8P Abbreviation R/W BFR7A BFR7B BFR7C BFR7D DTR7A DTR7B DTR7C DTR7D TCR7A TCR7B TSR7 TIER7 DCNT8A DCNT8B DCNT8C DCNT8D DCNT8E DCNT8F DCNT8G DCNT8H DCNT8I DCNT8J DCNT8K DCNT8L DCNT8M DCNT8N DCNT8O DCNT8P R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Initial Value Address Access Section Size (Bits) No. 16 11.2.23 H'FFFF H'FFFFF590 H'FFFF H'FFFFF592 H'FFFF H'FFFFF594 H'FFFF H'FFFFF596 H'FFFF H'FFFFF598 H'FFFF H'FFFFF59A H'FFFF H'FFFFF59C H'FFFF H'FFFFF59E H'00 H'00 11.2.24 H'FFFFF5A1 8, 16 H'FFFFF5A0 11.2.3 R/(W)* H'0000 H'FFFFF5A2 16 R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W H'0000 H'FFFFF5A4 H'0000 H'FFFFF640 H'0000 H'FFFFF642 H'0000 H'FFFFF644 H'0000 H'FFFFF646 H'0000 H'FFFFF648 H'0000 H'FFFFF64A H'0000 H'FFFFF64C H'0000 H'FFFFF64E H'0000 H'FFFFF650 H'0000 H'FFFFF652 H'0000 H'FFFFF654 H'0000 H'FFFFF656 H'0000 H'FFFFF658 H'0000 H'FFFFF65A H'0000 H'FFFFF65C H'0000 H'FFFFF65E 16 11.2.5 11.2.6 11.2.16 Rev.2.0, 07/03, page 207 of 960 Table 11.3 ATU-II Registers (cont) Channel Name 8 Reload register 8 Timer connection register One-shot pulse terminate register Down-count start register Abbreviation R/W RLDR8 TCNR OTR DSTR R/W R/W R/W R/W R/W Initial Value Address Access Section Size (Bits) No. 16 11.2.25 11.2.12 11.2.13 11.2.11 8 11.2.3 11.2.5 11.2.6 11.2.14 11.2.17 H'0000 H'FFFFF660 H'0000 H'FFFFF662 H'0000 H'FFFFF664 H'0000 H'FFFFF666 H'00 H'FFFFF668 Timer control register 8 TCR8 Timer status register 8 TSR8 Timer interrupt enable register 8 TIER8 R/(W)* H'0000 H'FFFFF66A 16 R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W H'0000 H'FFFFF66C H'00 H'00 H'00 H'00 H'00 H'00 H'00 H'FF H'FF H'FF H'FF H'FF H'FF H'00 H'00 H'00 H'FFFFF66E 8 H'FFFFF680 H'FFFFF682 H'FFFFF684 H'FFFFF686 H'FFFFF688 H'FFFFF68A H'FFFFF68C H'FFFFF68E H'FFFFF690 H'FFFFF692 H'FFFFF694 H'FFFFF696 H'FFFFF698 H'FFFFF69A H'FFFFF69C 8 Reload enable register RLDENR 9 Event counter 9A Event counter 9B Event counter 9C Event counter 9D Event counter 9E Event counter 9F General register 9A General register 9B General register 9C General register 9D General register 9E General register 9F Timer control register 9A Timer control register 9B Timer control register 9C ECNT9A ECNT9B ECNT9C ECNT9D ECNT9E ECNT9F GR9A GR9B GR9C GR9D GR9E GR9F TCR9A TCR9B TCR9C 11.2.20 11.2.3 Timer status register 9 TSR9 Timer interrupt enable register 9 TIER9 R/(W)* H'0000 H'FFFFF69E 16 R/W H'0000 H'FFFFF6A0 11.2.5 11.2.6 Rev.2.0, 07/03, page 208 of 960 Table 11.3 ATU-II Registers (cont) Channel Name 10 Free-running counter 10AH Free-running counter 10AL Event counter 10B Reload counter 10C Correction counter 10D Correction angle counter 10E Correction angle counter 10F Free-running counter 10G Input capture register 10AH Input capture register 10AL Output compare register 10AH Output compare register 10AL Output compare register 10B Reload register 10C General register 10G Noise canceler counter 10H Noise canceler register 10 Timer I/O control register 10 Timer control register 10 Abbreviation R/W TCNT10AH R/W TCNT10AL R/W TCNT10B TCNT10C TCNT10D TCNT10E TCNT10F R/W R/W R/W R/W R/W Initial Value Address Access Section Size (Bits) No. 11.2.26 H'0000 H'FFFFF6C0 32 H'0001 H'00 H'FFFFF6C4 8 H'0001 H'FFFFF6C6 16 H'00 H'FFFFF6C8 8 H'0000 H'FFFFF6CA 16 H'0001 H'FFFFF6CC H'0000 H'FFFFF6CE H'0000 H'FFFFF6D0 32 H'0000 H'FFFF H'FFFFF6D4 H'FFFF H'FF H'FFFFF6D8 8 TCNT10G R/W ICR10AH ICR10AL R R OCR10AH R/W OCR10AL OCR10B RLD10C GR10G TCNT10H NCR10 TIOR10 TCR10 R/W R/W R/W R/W R/W R/W R/W R/W H'0000 H'FFFFF6DA 16 H'FFFF H'FFFFF6DC H'00 H'FF H'00 H'00 H'FFFFF6DE 8 H'FFFFF6E0 H'FFFFF6E2 H'FFFFF6E4 Rev.2.0, 07/03, page 209 of 960 Table 11.3 ATU-II Registers (cont) Channel Name 10 Correction counter clear register 10 Timer status register 10 Timer interrupt enable register 10 11 Free-running counter 11 General register 11A General register 11B Timer I/O control register 11 Timer control register 11 Timer status register 11 Timer interrupt enable register 11 Note: * 0 write after a read Abbreviation R/W TCCLR10 TSR10 TIER10 TCNT11 GR11A GR11B TIOR11 TCR11 TSR11 TIER11 R/W Initial Value Address Access Section Size (Bits) No. 11.2.26 H'0000 H'FFFFF6E6 16 R/(W)* H'0000 H'FFFFF6E8 R/W R/W R/W R/W R/W R/W H'0000 H'FFFFF6EA H'0000 H'FFFFF5C0 16 H'FFFF H'FFFFF5C2 H'FFFF H'FFFFF5C4 H'00 H'00 H'FFFFF5C6 8 H'FFFFF5C8 11.2.4 11.2.3 11.2.5 11.2.6 11.2.15 11.2.20 R/(W)* H'0000 H'FFFFF5CA 16 R/W H'0000 H'FFFFF5CC Rev.2.0, 07/03, page 210 of 960 11.1.4 Block Diagrams Overall Block Diagram of ATU-II: Figure 11.1 shows an overall block diagram of the ATU-II. Clock selection TCLKA TCLKB Interrupts IC/OC control I/O interrupt control Inter-module connection signals External pins Inter-module address bus Counter and register control, and comparator 16-bit timer channel 11 32-bit timer channel 0 16-bit timer channel 1 Channel 10 Prescaler TSTR1 TSTR2 TSTR3 ........ P Bus interface Module data bus Inter-module data bus Legend: TSTR1, 2, 3: Timer start registers (8 bits) Interrupts: ITV0-ITV2, OVI0, OVI1A, OVI1B, OVI2A, OVI2B, OVI3-OVI5, OVI11, ICI0A-ICI0D, IMI1A-IMI1H, CMI1, IMI2A-IMI2H, CMI2A-CMI2H, IMI3A-IMI3D, IMI4A-IMI4D, IMI5A-IMI5D, CMI6A-CMI6D, CMI7A-CMI7D, OSI8A-OSI8P, CMI9A-CMI9F, CMI10A, CMI10B, ICI10A, CMI10G, IMI11A, IMI11B External pins: TI0A-TI0D, TIO1A-TIO1H, TIO2A-TIO2H, TIO3A-TIO3D, TIO4A-TIO4D, TIO5A-TIO5D, TO6A-TO6D, TO7A-TO7D, TO8A-TO8P, TI9A-TI9F, TI10, TIO11A-TIO11B Inter-module connection signals: Signals to A/D converter, signals to direct memory access controller (DMAC), signals to advanced pulse controller (APC) Figure 11.1 Overall Block Diagram of ATU-II Rev.2.0, 07/03, page 211 of 960 Block Diagram of Channel 0: Figure 11.2 shows a block diagram of ATU-II channel 0. STR0 Prescaler 1 ICR0AH ICR0BH ICR0CH ICR0DH TCNT0H ICR0AL ICR0BL ICR0CL ICR0DL TCNT0L TRGOD (OCR10B compare-match signal) TIOR0 TIER0 ITVRR1 ITVRR2A ITVRR2B TSR0 TI0A TI0B TI0C TI0D Control logic A/D converter trigger Overflow interrupt signal Interval interrupt I/O control OSBR (ch1, ch2) Internal data bus and address bus Figure 11.2 Block Diagram of Channel 0 Rev.2.0, 07/03, page 212 of 960 Block Diagram of Channel 1: Figure 11.3 shows a block diagram of ATU-II channel 1. STR1A/1B, 2B Prescaler 1 TCLKA TCLKB TI10 (AGCK) TI10 multiplication (AGCKM) Clock selection logic (2 systems: A, B) GR1A GR1B GR1C GR1D GR1E GR1F GR1G GR1H OSBR1 TCNT1A OCR1 TCNT1B TIOR1A TIOR1B TIOR1C TIOR1D TCR1A TCR1B TSR1A TSR1B TIER1A TIER1B TRGMDR TIO1A TIO1B TIO1C TIO1D TIO1E TIO1F TIO1G TIO1H One-shot start trigger (CH8) One-shot terminate trigger (CH8) I/O control Overflow interrupt x 1 Input capture/output compare interrupts x 8 Comparator TI0A(capture signal from CH0) TRG1A (counter clear trigger from CH10) TRG1B (counter clear trigger from CH10) Control logic Internal data bus and address bus Figure 11.3 Block Diagram of Channel 1 Rev.2.0, 07/03, page 213 of 960 Block Diagram of Channel 2: Figure 11.4 shows a block diagram of ATU-II channel 2. STR2A/1B, 2B Prescaler 1 TCLKA TCLKB TI10 (AGCKM) TI10 multiplication (AGCK) Clock selection logic Comparator TI0A (couter clear trigger from CH0) GR2A GR2B GR2C GR2D GR2E GR2F GR2G GR2H OSBR2 TCNT2A OCR2A OCR2B OCR2C OCR2D OCR2E OCR2F OCR2G OCR2H TCNT2B TIOR2A TIOR2B TIOR2C TIOR2D TCR2A TCR2B TSR2A TSR2B TIER2A TIER2B TIO2A TIO2B TIO2C TIO2D TIO2E TIO2F TIO2G TIO2H One-shot start trigger (CH8) One-shot terminate trigger (CH8) Overflow interrupt x 1 Input capture/output compare interrupts x 8 Control logic TRG2A (counter clear trigger from CH10) TRG2B (counter clear trigger from CH10) I/O control Internal data bus and address bus Figure 11.4 Block Diagram of Channel 2 Rev.2.0, 07/03, page 214 of 960 Block Diagram of Channels 3 to 5: Figure 11.5 shows a block diagram of ATU-II channels 3, 4, and 5. STR3 to 5 Prescaler 1 TCLKA TCLKB TI10 (AGCK) TI10 multiplication (AGCKM) GR3A * * * Clock selection logic (3 systems: CH3, 4, 5) Comparator Channel 9 comparematch trigger GR3D TCNT3 TIOR3A TIOR3B TCR3 GR4A * * * GR4D TCNT4 TIOR4A TIOR4B TCR4 GR5A * * * Control logic GR5D TCNT5 TIOR5A TIOR5B TCR5 TMDR TIER3 TSR3 TIO3A TIO3B TIO3C TIO3D TIO4A TIO4B TIO4C TIO4D TIO5A TIO5B TIO5C TIO5D I/O control Overflow interrupts x 3 Input capture/output compare interrupts x 12 Internal data bus and address bus Figure 11.5 Block Diagram of Channels 3 to 5 Rev.2.0, 07/03, page 215 of 960 Block Diagram of Channels 6 and 7: Figure 11.6 shows a block diagram of ATU-II channels 6 and 7. STR6x, 7x Prescaler 2 Clock selection logic (A-D independent) BFR6A CYLR6A DTR6A TCNT6A BFR6B CYLR6B DTR6B TCNT6B BFR6C CYLR6C DTR6C TCNT6C BFR6D CYLR6D DTR6D TCNT6D TCR6A TCR6B TSR6 TIER6 PMDR TO6A TO6B TO6C TO6D Comparator Control logic I/O control Compare-match interrupts x 4 Internal data bus and address bus Note: Channel 7 has no PMDR7. Figure 11.6 Block Diagram of Channel 6 (Same Configuration for Channel 7) Rev.2.0, 07/03, page 216 of 960 Block Diagram of Channel 8: Figure 11.7 shows a block diagram of ATU-II channel 8. Prescaler 1 Clock selection (2 systems: A-H, I-P) DCNT8A DCNT8B DCNT8C DCNT8D * * * * Comparator One-shot start trigger (CH1, 2) One-shot terminate trigger (CH1, 2) DCNT8M DCNT8N DCNT8O DCNT8P RLDR8 TCNR OTR DSTR TCR8 TSR8 TIER8 RLDENR Control logic TO8A TO8B * * * * TO8O TO8P I/O control Down-count end interrupts x 16 (OSI) Internal data bus and address bus Figure 11.7 Block Diagram of Channel 8 Rev.2.0, 07/03, page 217 of 960 Block Diagram of Channel 9: Figure 11.8 shows a block diagram of ATU-II channel 9. GR9A ECNT9A GR9B ECNT9B GR9C ECNT9C GR9D ECNT9D GR9E ECNT9E GR9F ECNT9F TCR9A TCR9B TCR9C TSR9 TIER9 TI9A TI9B TI9C TI9D TI9E TI9F Control logic Comparator Channel 3 capture trigger x 4 I/O control Compare-match interrupts x 6 Internal data bus and address bus Figure 11.8 Block Diagram of Channel 9 Rev.2.0, 07/03, page 218 of 960 Block Diagram of Channel 10: Figure 11.9 shows a block diagram of ATU-II channel 10. STR10 Prescaler 4 ICR10AH OCR10AH TCNT10AH ICR10AL OCR10AL TCNT10AL OCR10B TCNT10B RLD10C TCNT10C TCNT10D TCNT10E TCNT10F GR10G TCNT10G NCR10 TCNT10H TCCLR10 TIOR10 TCR10 TIER10 TSR10 TI10 I/O control Internal data bus and address bus Control logic TRG1A, 1B, 2A, 2B (Counter clear trigger) TRG0D (OCR10B comparematch signal) Frequency multiplication clock Frequency multiplication correction clock Output compare interrupts x 2 Input capture / output compare interrupt x 1 Figure 11.9 Block Diagram of Channel 10 Rev.2.0, 07/03, page 219 of 960 Block Diagram of Channel 11: Figure 11.10 shows a block diagram of ATU-II channel 11. STR11 Prescaler 4 TCLKA TCLKB Clock selection logic Comparator GR11A GR11B TCNT11 TIOR11 TCR11 TSR11 TIER11 Control logic TIO11A TIO11B APC output compare-match timing signals x 2 I/O control Overflow interrupt x 1 Input capture/output compare interrupts x 2 Internal data bus and address bus Figure 11.10 Block Diagram of Channel 11 Rev.2.0, 07/03, page 220 of 960 11.1.5 Inter-Channel and Inter-Module Signal Communication Diagram Figure 11.11 shows the connections between channels and between modules in the ATU-II. Channel 0 TI0A ICR0A ICR0B ICR0C ICR0D ITVRR1 ITVRR2A ITVRR2B A/D converter activation DMAC activation Capture trigger OCR10B Channel 10 Channel 1 Capture trigger OSBR1 TCNT1A TCNT1B GR1A GR1B * * * TCNT10F OCR1 GR1H TI10(AGCK) TI10 multiplication (AGCKM) Counter clear trigger Channel 2 OSBR2 OCR2A OCR2B * * * TCNT2A TCNT2B GR2A GR2B * * * OCR2H GR2H TI10(AGCK) TI10 multiplication (AGCKM) Channel 8 One-shot start One-shot terminate DCNT8A DCNT8B DCNT8C DCNT8D DCNT8E DCNT8F DCNT8G DCNT8H DCNT8I DCNT8J DCNT8K DCNT8L DCNT8M DCNT8N DCNT8O DCNT8P Channel 3 GR3A GR3B GR3C GR3D TI10(AGCK) TI10 multiplication (AGCKM) Channel 4 Capture trigger TI10(AGCK) TI10 multiplication (AGCKM) TI10(AKCK) TI10 multiplication (AGCKM) Channels 6, 7 GR9A GR9B GR9C GR9D GR9E GR9F CYLR6, 7x DTR6, 7x BFR6, 7x Channel 5 Channel 9 TCNT6, 7x DMAC activation (compare-match) X: A, B, C, D Channel 11 TCNT11 GR11A GR11B Compare-match signal transmission to advanced pulse controller (APC) Figure 11.11 Inter-Module Communication Signals Rev.2.0, 07/03, page 221 of 960 11.1.6 Prescaler Diagram Figure 11.12 shows a diagram of the ATU-II prescalers. Input clock /2 Prescaler 1 Channel 0 Channel 1 Channel 2 TCLKA TCLKB Channel 3 Edge detection Channel 4 Channel 5 Channel 8 Channel 10 TI10 Prescaler 2 Channel 6 Prescaler 3 TI9A TI9B TI9C TI9D TI9E TI9F Channel 7 Prescaler 4 Channel 11 Channel 9 Timer control register Figure 11.12 Prescaler Diagram Rev.2.0, 07/03, page 222 of 960 11.2 11.2.1 Register Descriptions Timer Start Registers (TSTR) The timer start registers (TSTR) are 8-bit registers. The ATU-II has three TSTR registers. Channel 0, 1, 2, 3, 4, 5, 10 6, 7 11 Abbreviation TSTR1 TSTR2 TSTR3 Function Free-running counter operation/stop setting Timer Start Register 1 (TSTR1) Bit: 7 STR10 Initial value: R/W: 0 R/W 6 STR5 0 R/W 5 STR4 0 R/W 4 STR3 0 R/W 3 STR1B, 2B 0 R/W 2 STR2A 0 R/W 1 STR1A 0 R/W 0 STR0 0 R/W TSTR1 is an 8-bit readable/writable register that starts and stops the free-running counter (TCNT) in channels 0 to 5 and 10. TSTR1 is initialized to H'00 by a power-on reset, and in hardware standby mode and software standby mode. * Bit 7--Counter Start 10 (STR10): Starts and stops channel 10 counters (TCNT10A, 10C, 10D, 10E, 10F, and 10G). TCNT10B and 10H are not stopped. Bit 7: STR10 0 1 Description TCNT10 is halted TCNT10 counts (Initial value) * Bit 6--Counter Start 5 (STR5): Starts and stops free-running counter 5 (TCNT5). Bit 6: STR5 0 1 Description TCNT5 is halted TCNT5 counts (Initial value) Rev.2.0, 07/03, page 223 of 960 * Bit 5--Counter Start 4 (STR4): Starts and stops free-running counter 4 (TCNT4). Bit 5: STR4 0 1 Description TCNT4 is halted TCNT4 counts (Initial value) * Bit 4--Counter Start 3 (STR3): Starts and stops free-running counter 3 (TCNT3). Bit 4: STR3 0 1 Description TCNT3 is halted TCNT3 counts (Initial value) * Bit 3--Counter Start 1B, 2B (STR1B, STR2B): Starts and stops free-running counters 1B and 2B (TCNT1B, TCNT2B). Bit 3: STR1B, STR2B 0 1 Description TCNT1B and TCNT2B are halted TCNT1B and TCNT2B count (Initial value) * Bit 2--Counter Start 2A (STR2A): Starts and stops free-running counter 2A (TCNT2A). Bit 2: STR2A 0 1 Description TCNT2A is halted TCNT2A counts (Initial value) * Bit 1--Counter Start 1A (STR1A): Starts and stops free-running counter 1A (TCNT1A). Bit 1: STR1A 0 1 Description TCNT1A is halted TCNT1A counts (Initial value) * Bit 0--Counter Start 0 (STR0): Starts and stops free-running counter 0 (TCNT0). Bit 0: STR0 0 1 Description TCNT0 is halted TCNT0 counts (Initial value) Rev.2.0, 07/03, page 224 of 960 Timer Start Register 2 (TSTR2) Bit: 7 STR7D Initial value: R/W: 0 R/W 6 STR7C 0 R/W 5 STR7B 0 R/W 4 STR7A 0 R/W 3 STR6D 0 R/W 2 STR6C 0 R/W 1 STR6B 0 R/W 0 STR6A 0 R/W TSTR2 is an 8-bit readable/writable register that starts and stops the free-running counter (TCNT) in channels 6 and 7. TSTR2 is initialized to H'00 by a power-on reset, and in hardware standby mode and software standby mode. * Bit 7--Counter Start 7D (STR7D): Starts and stops free-running counter 7D (TCNT7D). Bit 7: STR7D 0 1 Description TCNT7D is halted TCNT7D counts (Initial value) * Bit 6--Counter Start 7C (STR7C): Starts and stops free-running counter 7C (TCNT7C). Bit 6: STR7C 0 1 Description TCNT7C is halted TCNT7C counts (Initial value) * Bit 5--Counter Start 7B (STR7B): Starts and stops free-running counter 7B (TCNT7B). Bit 5: STR7B 0 1 Description TCNT7B is halted TCNT7B counts (Initial value) * Bit 4--Counter Start 7A (STR7A): Starts and stops free-running counter 7A (TCNT7A). Bit 4: STR7A 0 1 Description TCNT7A is halted TCNT7A counts (Initial value) Rev.2.0, 07/03, page 225 of 960 * Bit 3--Counter Start 6D (STR6D): Starts and stops free-running counter 6D (TCNT6D). Bit 3: STR6D 0 1 Description TCNT6D is halted TCNT6D counts (Initial value) * Bit 2--Counter Start 6C (STR6C): Starts and stops free-running counter 6C (TCNT6C). Bit 2: STR6C 0 1 Description TCNT6C is halted TCNT6C counts (Initial value) * Bit 1--Counter Start 6B (STR6B): Starts and stops free-running counter 6B (TCNT6B). Bit 1: STR6B 0 1 Description TCNT6B is halted TCNT6B counts (Initial value) * Bit 0--Counter Start 6A (STR6A): Starts and stops free-running counter 6A (TCNT6A). Bit 0: STR6A 0 1 Description TCNT6A is halted TCNT6A counts (Initial value) Timer Start Register 3 (TSTR3) Bit: 7 -- Initial value: R/W: 0 R 6 -- 0 R 5 -- 0 R 4 -- 0 R 3 -- 0 R 2 -- 0 R 1 -- 0 R 0 STR11 0 R/W TSTR3 is an 8-bit readable/writable register that starts and stops the free-running counter (TCNT11) in channel 11. TSTR3 is initialized to H'00 by a power-on reset, and in hardware standby mode and software standby mode. Rev.2.0, 07/03, page 226 of 960 * Bits 7 to 1--Reserved: These bits are always read as 0. The write value should always be 0. * Bit 0--Counter Start 11 (STR11): Starts and stops free-running counter 11 (TCNT11). Bit 0: STR11 0 1 Description TCNT11 is halted TCNT11 counts (Initial value) 11.2.2 Prescaler Registers (PSCR) The prescaler registers (PSCR) are 8-bit registers. The ATU-II has four PSCR registers. Channel 0, 1, 2, 3, 4, 5, 8, 11 6 7 10 Abbreviation PSCR1 PSCR2 PSCR3 PSCR4 Function Prescaler setting for respective channels PSCRx is an 8-bit writable register that enables the first-stage counter clock ' input to each channel to be set to any value from P/1 to P/32. Bit: 7 -- Initial value: R/W: x = 1 to 4 0 R 6 -- 0 R 5 -- 0 R 4 PSCxE 0 R/W 3 PSCxD 0 R/W 2 PSCxC 0 R/W 1 PSCxB 0 R/W 0 PSCxA 0 R/W Input counter clock ' is determined by setting PSCxA to PSCxE: ' is P/1 when the set value is H'00, and P/32 when H'1F. PSCRx is initialized to H'00 by a power-on reset, and in hardware standby mode and software standby mode. The internal clock ' set with this register can undergo further second-stage scaling to create clock " for channels 1 to 8 and 11, the setting being made in the timer control register (TCR). * Bits 7 to 5--Reserved: These bits cannot be modified. * Bits 4 to 0--Prescaler (PSCxE, PSCxD, PSCxC, PSCxB, PSCxA): These bits specify frequency division of first-stage counter clock o' input to the corresponding channel. Rev.2.0, 07/03, page 227 of 960 11.2.3 Timer Control Registers (TCR) The timer control registers (TCR) are 8-bit registers. The ATU-II has 16 TCR registers: two each for channels 1 and 2, one each for channels 3, 4, 5, 8, and 11, two each for channels 6 and 7, and three for channel 9. For details of channel 10, see section 11.2.26, Channel 10 Registers. Channel 1 2 3 4 5 6 7 8 9 11 Abbreviation TCR1A, TCR1B TCR2A, TCR2B TCR3 TCR4 TCR5 TCR6A, TCR6B TCR7A, TCR7B TCR8 TCR9A, TCR9B, TCR9C TCR11 External clock selection/setting of channel 3 trigger in event of compare-match Internal clock/external clock selection Internal clock selection Function Internal clock/external clock/TI10 input clock selection Each TCR is an 8-bit readable/writable register that selects whether an internal clock or external clock is used for channels 1 to 5 and 11. For channels 6 to 8, TCR selects an internal clock, and for channel 9, an external clock. When an internal clock is selected, TCR selects the value of " further scaled from clock ' scaled with prescaler register (PSCR). Scaled clock " can be selected, for channels 1 to 8 and 11 only, from ', '/2, '/4, '/8, '/16, and '/32 (only ' is available for channel 0). Edge detection is performed on the rising edge. When an external clock is selected, TCR selects whether TCLKA, TCLKB (channels 1 to 5 and 11 only), TI10 pin input (channels 1 to 5 only), or a TI10 pin input multiplied clock (channels 1 to 5 only) is used, and also performs edge selection. Each TCR is initialized to H'00 by a power-on reset, and in hardware standby mode and software standby mode. Rev.2.0, 07/03, page 228 of 960 Timer Control Registers 1A, 1B, 2A, 2B (TCR1A, TCR1B, TCR2A, TCR2B) TCR1A, TCR2A Bit: 7 -- Initial value: R/W: 0 R 6 -- 0 R 5 CKEGA1 4 3 2 1 0 CKEGA0 CKSELA3 CKSELA2 CKSELA1 CKSELA0 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W TCR1B, TCR2B Bit: 7 -- Initial value: R/W: 0 R 6 -- 0 R 5 CKEGB1 4 3 2 1 0 CKEGB0 CKSELB3 CKSELB2 CKSELB1 CKSELB0 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W * Bits 7 and 6--Reserved: These bits always read 0. The write value should always be 0. * Bits 5 and 4--Clock Edge 1 and 0 (CKEGx1, CKEGx0): These bits select the count edge(s) for external clock TCLKA and TCLKB input. Bit 5: CKEGx1 0 Bit 4: CKEGx0 0 1 1 x = A or B 0 1 Description Rising edges counted Falling edges counted Both rising and falling edges counted Count disabled (Initial value) * Bits 3 to 0--Clock Select A3 to A0, B3 to B0 (CKSELA3 to CKSELA0, CKSELB3 to CKSELB0): These bits select whether an internal clock or external clock is used. When an internal clock is selected, scaled clock " is selected from ', '/2, '/4, '/8, '/16, and '/32. When an external clock is selected, TCLKA, TCLKB, TI10 pin input, or a TI10 pin input multiplied clock is selected. When TI10 pin input and TI10 pin input clock multiplication are selected, set CKEG1 and CKEG0 in TCR10 so that TI10 input is possible. Rev.2.0, 07/03, page 229 of 960 Bit 3: CKSELx3 0 Bit 2: CKSELx2 0 Bit 1: CKSELx1 0 Bit 0: CKSELx0 0 1 Description Internal clock ": counting on ' Internal clock ": counting on '/2 Internal clock ": counting on '/4 Internal clock ": counting on '/8 Internal clock ": counting on '/16 Internal clock ": counting on '/32 External clock: counting on TCLKA pin input External clock: counting on TCLKB pin input Counting on TI10 pin input (AGCK) Counting on multiplied (corrected)(AGCKM) TI10 pin input clock Setting prohibited Setting prohibited (Initial value) 1 0 1 1 0 0 1 1 0 1 1 0 0 0 1 1 1 x = A or B *: Donit care * * * Timer Control Registers 3 to 5 (TCR3, TCR4, TCR5) Bit: 7 -- Initial value: R/W: 0 R 6 -- 0 R 5 CKEG1 0 R/W 4 3 2 1 0 CKEG0 CKSEL3 CKSEL2 CKSEL1 CKSEL0 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W * Bits 7 and 6--Reserved: These bits are always read as 0. The write value should always be 0. * Bits 5 and 4--Clock Edge 1 and 0 (CKEG1, CKEG0): These bits select the count edge(s) for external clock TCLKA and TCLKB input. Bit 5: CKEG1 0 Bit 4: CKEG0 0 1 1 0 1 Description Rising edges counted Falling edges counted Both rising and falling edges counted Count disabled (Initial value) Rev.2.0, 07/03, page 230 of 960 * Bits 3 to 0--Clock Select 3 to 0 (CKSEL3 to CKSEL0): These bits select whether an internal clock or external clock is used. When an internal clock is selected, scaled clock " is selected from ', '/2, '/4, '/8, '/16, and '/32. When an external clock is selected, TCLKA, TCLKB, TI10 pin input, or a TI10 pin input multiplied clock is selected. When TI10 pin input and TI10 pin input clock multiplication are selected, set CKEG1 and CKEG0 in TCR10 so that TI10 input is possible. Bit 3: CKSEL3 0 Bit 2: CKSEL2 0 Bit 1: CKSEL1 0 Bit 0: CKSEL0 0 1 1 0 1 1 0 0 1 1 0 1 1 0 0 0 1 1 1 *: Donit care * * * Description Internal clock ": counting on ' Internal clock ": counting on '/2 Internal clock ": counting on '/4 Internal clock ": counting on '/8 Internal clock ": counting on '/16 Internal clock ": counting on '/32 External clock: counting on TCLKA pin input External clock: counting on TCLKB pin input Counting on TI10 pin input (AGCK) Counting on multiplied (corrected)(AGCKM) TI10 pin input clock Setting prohibited Setting prohibited (Initial value) Rev.2.0, 07/03, page 231 of 960 Timer Control Registers 6A, 6B, 7A, 7B (TCR6A, TCR6B, TCR7A, TCR7B) TCR6A, TCR7A Bit: 7 -- Initial value: R/W: 0 R 6 5 4 3 -- 0 R 2 1 0 CKSELB2 CKSELB1 CKSELB0 CKSELA2 CKSELA1 CKSELA0 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W TCR6B, TCR7B Bit: 7 -- Initial value: R/W: 0 R 6 5 4 3 -- 0 R 2 1 0 CKSELD2 CKSELD1 CKSELD0 CKSELC2 CKSELC1 CKSELC0 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W * Bit 7--Reserved: This bit is always read as 0. The write value should always be 0. * Bits 6 to 4--Clock Select B2 to B0, D2 to D0 (CKSELB2 to CKSELB0, CKSELD2 to CKSELD0): These bits select clock ", scaled from the internal clock source, from ', '/2, '/4, '/8, '/16, and '/32. Bit 6: CKSELx2 0 Bit 5: CKSELx1 0 Bit 4: CKSELx0 0 1 1 0 1 1 0 0 1 1 x = B or D 0 1 Description Internal clock ": counting on ' Internal clock ": counting on '/2 Internal clock ": counting on '/4 Internal clock ": counting on '/8 Internal clock ": counting on '/16 Internal clock ": counting on '/32 Setting prohibited Setting prohibited (Initial value) Rev.2.0, 07/03, page 232 of 960 * Bit 3--Reserved: This bit is always read as 0. The write value should always be 0. * Bits 2 to 0--Clock Select A2 to A0, C2 to C0 (CKSELA2 to CKSELA0, CKSELC2 to CKSELC0): These bits select clock ", scaled from the internal clock source, from ', '/2, '/4, '/8, '/16, and '/32. Bit 2: CKSELx2 0 Bit 1 CKSELx1 0 Bit 0 CKSELx0 0 1 1 0 1 1 0 0 1 1 x = A or B 0 1 Description Internal clock ": counting on ' Internal clock ": counting on '/2 Internal clock ": counting on '/4 Internal clock ": counting on '/8 Internal clock ": counting on '/16 Internal clock ": counting on '/32 Setting prohibited Setting prohibited (Initial value) Timer Control Register 8 (TCR8) Bit: 7 -- Initial value: R/W: 0 R 6 5 4 3 -- 0 R 2 1 0 CKSELB2 CKSELB1 CKSELB0 CKSELA2 CKSELA1 CKSELA0 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W The CKSELAx bits relate to DCNT8A to DCNT8H, and the CKSELBx bits relate to DCNT8I to DCNT8P. Rev.2.0, 07/03, page 233 of 960 * Bit 7--Reserved: This bit is always read as 0. The write value should always be 0. * Bits 6 to 4--Clock Select B2 to B0 (CKSELB2 to CKSELB0): These bits, relating to counters DCNT8I to DCNT8P, select clock ", scaled from the internal clock source, from ', '/2, '/4, '/8, '/16, and '/32. Bit 6: CKSELB2 0 Bit 5: CKSELB1 0 Bit 4: CKSELB0 0 1 1 0 1 1 0 0 1 1 0 1 Description Internal clock ": counting on ' Internal clock ": counting on '/2 Internal clock ": counting on '/4 Internal clock ": counting on '/8 Internal clock ": counting on '/16 Internal clock ": counting on '/32 Setting prohibited Setting prohibited (Initial value) * Bit 3--Reserved: This bit is always read as 0. The write value should always be 0. * Bits 2 to 0--Clock Select A2 to A0 (CKSELA2 to CKSELA0): These bits, relating to counters DCNT8A to DCNT8H, select clock ", scaled from the internal clock source, from ', '/2, '/4, '/8, '/16, and '/32. Bit 2: CKSELA2 0 Bit 1: CKSELA1 0 Bit 0: CKSELA0 0 1 1 0 1 1 0 0 1 1 0 1 Description Internal clock ": counting on ' Internal clock ": counting on '/2 Internal clock ": counting on '/4 Internal clock ": counting on '/8 Internal clock ": counting on '/16 Internal clock ": counting on '/32 Setting prohibited Setting prohibited (Initial value) Rev.2.0, 07/03, page 234 of 960 Timer Control Registers 9A, 9B, 9C (TCR9A, TCR9B, TCR9C) TCR9A Bit: 7 -- Initial value: R/W: 0 R 6 5 4 3 -- 0 R 2 1 0 TRG3BEN EGSELB1 EGSELB0 TRG3AEN EGSELA1 EGSELA0 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W TCR9B Bit: 7 -- Initial value: R/W: 0 R 6 5 4 3 -- 0 R 2 1 0 TRG3DEN EGSELD1 EGSELD0 TRG3CEN EGSELC1 EGSELC0 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W TCR9C Bit: 7 -- Initial value: R/W: 0 R 6 -- 0 R 5 4 3 -- 0 R 2 -- 0 R 1 0 EGSELF1 EGSELF0 EGSELE1 EGSELE0 0 R/W 0 R/W 0 R/W 0 R/W * Bit 7--Reserved: This bit is always read as 0. The write value should always be 0. * Bit 6--Trigger Channel 3BEN, 3DEN (TRG3BEN, TRG3DEN): These bits select the channel 9 event counter compare-match signal channel 3 input capture trigger. Bit 6: TRG3xEN 0 1 x = B or D Description Channel 3 input capture trigger in event of channel 9 compare-match (ECNT9x = GR9x) is disabled (Initial value) Channel 3 input capture trigger in event of channel 9 compare-match (ECNT9x = GR9x) is enabled Rev.2.0, 07/03, page 235 of 960 * Bits 5 and 4--Edge Select B1, B0, D1, D0, F1, F0 (EGSELB1, EGSELB0, EGSELD1, EGSELD0, EGSELF1, EGSELF0): These bits select the event counter counted edge(s). Bit 5: EGSELx1 0 Bit 4: EGSELx0 0 1 1 x = B, D, or F 0 1 Description Count disabled Rising edges counted Falling edges counted Both rising and falling edges counted (Initial value) * Bit 3--Reserved: This bit is always read as 0. The write value should always be 0. * Bit 2--Trigger Channel 3AEN, 3CEN (TRG3AEN, TRG3CEN): These bits select the channel 9 event counter compare-match signal channel 3 input capture trigger. Bit 2: TRG3xEN 0 1 x = A or C Description Channel 3 input capture trigger in event of channel 9 compare-match (ECNT9x = GR9x) is disabled (Initial value) Channel 3 input capture trigger in event of channel 9 compare-match (ECNT9x = GR9x) is enabled * Bits 1 and 0--Edge Select A1, A0, C1, C0, E1, E0 (EGSELA1, EGSELA0, EGSELC1, EGSELC0, EGSELE1, EGSELE0): These bits select the event counter counted edge(s). Bit 1: EGSELx1 0 Bit 0: EGSELx0 0 1 1 x = A, C, or E 0 1 Description Count disabled Rising edges counted Falling edges counted Both rising and falling edges counted (Initial value) Rev.2.0, 07/03, page 236 of 960 Timer Control Register 11 (TCR11) Bit: 7 -- Initial value: R/W: 0 R 6 -- 0 R 5 CKEG1 4 CKEG0 3 -- 0 R 2 1 0 CKSELA2 CKSELA1 CKSELA0 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W * Bits 7, 6, and 3--Reserved: These bits are always read as 0. The write value should always be 0. * Bits 5 and 4--Edge Select: These bits select the event counter counted edge(s). Bit 5: CKEG1 0 Bit 4: CKEG0 0 1 1 0 1 Description Rising edges counted Falling edges counted Both rising and falling edges counted Count disabled (Initial value) * Bits 2 to 0--Clock Select A2 to A0 (CKSELA2 to CKSELA0): These bits select clock ", scaled from the internal clock source, from ', '/2, '/4, '/8, '/16, and '/32. Bit 2: CKSELA2 0 Bit 1: CKSELA1 0 Bit 0: CKSELA0 0 1 1 0 1 1 0 0 1 1 0 1 Description Internal clock ": counting on ' Internal clock ": counting on '/2 Internal clock ": counting on '/4 Internal clock ": counting on '/8 Internal clock ": counting on '/16 Internal clock ": counting on '/32 External clock: counting on TCLKA pin input External clock: counting on TCLKB pin input (Initial value) Rev.2.0, 07/03, page 237 of 960 11.2.4 Timer I/O Control Registers (TIOR) The timer I/O control registers (TIOR) are 8-bit registers. The ATU-II has 16 TIOR registers: one for channel 0, four each for channels 1 and 2, two each for channels 3 to 5, and one for channel 11. For details of channel 10, see section 11.2.26, Channel 10 Registers. Channel 0 1 2 3 4 5 11 Abbreviation TIOR0 TIOR1A-1D TIOR2A-2D TIOR3A, TIOR3B TIOR4A, TIOR4B TIOR5A, TIOR5B TIOR11 GR input capture/compare-match switching, edge detection/output value setting Function ICR0 edge detection setting GR input capture/compare-match switching, edge detection/ output value setting GR input capture/compare-match switching, edge detection/output value setting, TCNT3 to TCNT5 clear enable/disable setting Each TIOR is an 8-bit readable/writable register used to select the functions of dedicated input capture registers and general registers. For dedicated input capture registers (ICR), TIOR performs edge detection setting. For general registers (GR), TIOR selects use as an input capture register or output compare register, and performs edge detection setting. For channels 3 to 5, TIOR also selects enabling or disabling of free-running counter (TCNT) clearing in the event of a compare-match. Timer I/O Control Register 0 (TIOR0) Bit: 7 IO0D1 Initial value: R/W: 0 R/W 6 IO0D0 0 R/W 5 IO0C1 0 R/W 4 IO0C0 0 R/W 3 IO0B1 0 R/W 2 IO0B0 0 R/W 1 IO0A1 0 R/W 0 IO0A0 0 R/W TIOR0 specifies edge detection for input capture registers ICR0A to ICR0D. TIOR0 is initialized to H'00 by a power-on reset, and in hardware standby mode and software standby mode. Rev.2.0, 07/03, page 238 of 960 * Bits 7 and 6--I/O Control 0D1 and 0D0 (IO0D1, IO0D0): These bits select TI0D pin input capture signal edge detection. Bit 7: IO0D1 0 Bit 6: IO0D0 0 1 1 0 1 Description Input capture disabled (input capture possible in TCNT10B compare-match) (Initial value) Input capture in ICR0D on rising edge Input capture in ICR0D on falling edge Input capture in ICR0D on both rising and falling edges * Bits 5 and 4--I/O Control 0C1 and 0C0 (IO0C1, IO0C0): These bits select TI0C pin input capture signal edge detection. Bit 5: IO0C1 0 Bit 4: IO0C0 0 1 1 0 1 Description Input capture disabled Input capture in ICR0C on rising edge Input capture in ICR0C on falling edge Input capture in ICR0C on both rising and falling edges (Initial value) * Bits 3 and 2--I/O Control 0B1 and 0B0 (IO0B1, IO0B0): These bits select TI0B pin input capture signal edge detection. Bit 3: IO0B1 0 Bit 2: IO0B0 0 1 1 0 1 Description Input capture disabled Input capture in ICR0B on rising edge Input capture in ICR0B on falling edge Input capture in ICR0B on both rising and falling edges (Initial value) * Bits 1 and 0--I/O Control 0A1 and 0A0 (IO0A1, IO0A0): These bits select TI0A pin input capture signal edge detection. Bit 1: IO0A1 0 Bit 0: IO0A0 0 1 1 0 1 Description Input capture disabled Input capture in ICR0A on rising edge Input capture in ICR0A on falling edge Input capture in ICR0A on both rising and falling edges (Initial value) Rev.2.0, 07/03, page 239 of 960 Timer I/O Control Registers 1A to 1D (TIOR1A to TIOR1D) TIOR1A Bit: 7 -- 6 IO1B2 0 R/W 5 IO1B1 0 R/W 4 IO1B0 0 R/W 3 -- 0 R 2 IO1A2 0 R/W 1 IO1A1 0 R/W 0 IO1A0 0 R/W Initial value: R/W: 0 R TIOR1B Bit: 7 -- Initial value: R/W: 0 R 6 IO1D2 0 R/W 5 IO1D1 0 R/W 4 IO1D0 0 R/W 3 -- 0 R 2 IO1C2 0 R/W 1 IO1C1 0 R/W 0 IO1C0 0 R/W TIOR1C Bit: 7 -- Initial value: R/W: 0 R 6 IO1F2 0 R/W 5 IO1F1 0 R/W 4 IO1F0 0 R/W 3 -- 0 R 2 IO1E2 0 R/W 1 IO1E1 0 R/W 0 IO1E0 0 R/W TIOR1D Bit: 7 -- Initial value: R/W: 0 R 6 IO1H2 0 R/W 5 IO1H1 0 R/W 4 IO1H0 0 R/W 3 -- 0 R 2 IO1G2 0 R/W 1 IO1G1 0 R/W 0 IO1G0 0 R/W Registers TIOR1A to TIOR1D specify whether general registers GR1A to GR1H are used as input capture or compare-match registers, and also perform edge detection and output value setting. Each TIOR is initialized to H'00 by a power-on reset, and in hardware standby mode and software standby mode. Rev.2.0, 07/03, page 240 of 960 * Bit 7--Reserved: This bit is always read as 0. The write value should always be 0. * Bits 6 to 4--I/O Control 1B2 to 1B0, 1D2 to 1D0, 1F2 to 1F0, 1H2 to 1H0 (IO1B2 to IO1B0, IO1D2 to IO1D0, IOF12 to IO1F0, IO1H2 to IO1H0): These bits select the general register (GR) function. Bit 6: IO1x2 0 Bit 5: IO1x1 0 Bit 4: IO1x0 0 1 1 0 1 1 0 0 1 1 0 1 GR is an input capture register Description GR is an output compare register Compare-match disabled; pin output undefined (Initial value) 0 output on GR compare-match 1 output on GR compare-match Toggle output on GR compare-match Input capture disabled (GR cannot be written to) Input capture in GR on rising edge at TIO1x pin (GR cannot be written to) Input capture in GR on falling edge at TIO1x pin (GR cannot be written to) Input capture in GR on both rising and falling edges at TIO1x pin (GR cannot be written to) x = B, D, F, or H Rev.2.0, 07/03, page 241 of 960 * Bit 3--Reserved: This bit is always read as 0. The write value should always be 0. * Bits 2 to 0--I/O Control 1A2 to 1A0, 1C2 to 1C0, 1E2 to 1E0, 1G2 to 1G0 (IO1A2 to IO1A0, IO1C2 to IO1C0, IO1E2 to IO1E0, IO1G2 to IO1G0): These bits select the general register (GR) function. Bit 2: IO1x2 0 Bit 1: IO1x1 0 Bit 0: IO1x0 0 1 1 0 1 1 0 0 1 1 0 1 GR is an input capture register Description GR is an output compare register Compare-match disabled; pin output undefined (Initial value) 0 output on GR compare-match 1 output on GR compare-match Toggle output on GR compare-match Input capture disabled Input capture in GR on rising edge at TIO1x pin (GR cannot be written to) Input capture in GR on falling edge at TIO1x pin (GR cannot be written to) Input capture in GR on both rising and falling edges at TIO1x pin (GR cannot be written to) x = A, C, E, or G Rev.2.0, 07/03, page 242 of 960 Timer I/O Control Registers 2A to 2D (TIOR2A to TIOR2D) TIOR2A Bit: 7 -- Initial value: R/W: 0 R 6 IO2B2 0 R/W 5 IO2B1 0 R/W 4 IO2B0 0 R/W 3 -- 0 R 2 IO2A2 0 R/W 1 IO2A1 0 R/W 0 IO2A0 0 R/W TIOR2B Bit: 7 -- Initial value: R/W: 0 R 6 IO2D2 0 R/W 5 IO2D1 0 R/W 4 IO2D0 0 R/W 3 -- 0 R 2 IO2C2 0 R/W 1 IO2C1 0 R/W 0 IO2C0 0 R/W TIOR2C Bit: 7 -- Initial value: R/W: 0 R 6 IO2F2 0 R/W 5 IO2F1 0 R/W 4 IO2F0 0 R/W 3 -- 0 R 2 IO2E2 0 R/W 1 IO2E1 0 R/W 0 IO2E0 0 R/W TIOR2D Bit: 7 -- Initial value: R/W: 0 R 6 IO2H2 0 R/W 5 IO2H1 0 R/W 4 IO2H0 0 R/W 3 -- 0 R 2 IO2G2 0 R/W 1 IO2G1 0 R/W 0 IO2G0 0 R/W Registers TIOR2A to TIOR2D specify whether general registers GR2A to GR2H are used as input capture or compare-match registers, and also perform edge detection and output value setting. Each TIOR is initialized to H'00 by a power-on reset, and in hardware standby mode and software standby mode. Rev.2.0, 07/03, page 243 of 960 * Bit 7--Reserved: This bit is always read as 0. The write value should always be 0. * Bits 6 to 4--I/O Control 2B2 to 2B0, 2D2 to 2D0, 2F2 to 2F0, 2H2 to 2H0 (IO2B2 to IO2B0, IO2D2 to IO2D0, IO2F2 to IO2F0, IO2H2 to IO2H0): These bits select the general register (GR) function. Bit 6: IO2x2 0 Bit 5: IO2x1 0 Bit 4: IO2x0 0 1 1 0 1 1 0 0 1 1 0 1 GR is an input capture register Description GR is an output compare register Compare-match disabled; pin output undefined (Initial value) 0 output on GR compare-match 1 output on GR compare-match Toggle output on GR compare-match Input capture disabled Input capture in GR on rising edge at TIO2x pin (GR cannot be written to) Input capture in GR on falling edge at TIO2x pin (GR cannot be written to) Input capture in GR on both rising and falling edges at TIO2x pin (GR cannot be written to) x = B, D, F, or H Rev.2.0, 07/03, page 244 of 960 * Bit 3--Reserved: This bit is always read as 0. The write value should always be 0. * Bits 2 to 0--I/O Control 2A2 to 2A0, 2C2 to 2C0, 2E2 to 2E0, 2G2 to 2G0 (IO2A2 to IO2A0, IO2C2 to IO2C0, IO2E2 to IO2E0, IO2G2 to IO2G0): These bits select the general register (GR) function. Bit 2: IO2x2 0 Bit 1: IO2x1 0 Bit 0: IO2x0 0 1 1 0 1 1 0 0 1 1 0 1 GR is an input capture register Description GR is an output compare register Compare-match disabled; pin output undefined (Initial value) 0 output on GR compare-match 1 output on GR compare-match Toggle output on GR compare-match Input capture disabled Input capture in GR on rising edge at TIO2x pin (GR cannot be written to) Input capture in GR on falling edge at TIO2x pin (GR cannot be written to) Input capture in GR on both rising and falling edges at TIO2x pin (GR cannot be written to) x = A, C, E, or G Timer I/O Control Registers 3A, 3B, 4A, 4B, 5A, 5B (TIOR3A, TIOR3B, TIOR4A, TIOR4B, TIOR5A, TIOR5B) TIOR3A, TIOR4A, TIOR5A Bit: 7 CCIxB Initial value: R/W: x = 3 to 5 0 R/W 6 IOxB2 0 R/W 5 IOxB1 0 R/W 4 IOxB0 0 R/W 3 CCIxA 0 R/W 2 IOxA2 0 R/W 1 IOxA1 0 R/W 0 IOxA0 0 R/W TIOR3B, TIOR4B, TIOR5B Bit: 7 CCIxD Initial value: R/W: x = 3 to 5 0 R/W 6 IOxD2 0 R/W 5 IOxD1 0 R/W 4 IOxD0 0 R/W 3 CCIxC 0 R/W 2 IOxC2 0 R/W 1 IOxC1 0 R/W 0 IOxC0 0 R/W Rev.2.0, 07/03, page 245 of 960 TIOR3A, TIOR3B, TIOR4A, TIOR4B, TIOR5A, and TIOR5B specify whether general registers GR3A to GR3D, GR4A to GR4D, and GR5A to GR5D are used as input capture or comparematch registers, and also perform edge detection and output value setting. They also select enabling or disabling of free-running counter (TCNT3 to TCNT5) clearing. Each TIOR is initialized to H'00 by a power-on reset, and in hardware standby mode and software standby mode. * Bit 7--Clear Counter Enable Flag 3B, 4B, 5B, 3D, 4D, 5D (CCI3B, CCI4B, CCI5B, CCI3D, CCI4D, CCI5D): These bits select enabling or disabling of free-running counter (TCNT) clearing. Bit 7: CCIxx 0 1 Description TCNT clearing disabled TCNT cleared on GR compare-match (Initial value) xx = 3B, 4B, 5B, 3D, 4D, or 5D TCNT is cleared on compare-match only when GR is functioning as an output compare register. * Bits 6 to 4--I/O Control 3B2 to 3B0, 4B2 to 4B0, 5B2 to 5B0, 3D2 to 3D0, 4D2 to 4D0, 5D2 to 5D0 (IO3B2 to IO3B0, IO4B2 to IO4B0, IO5B2 to IO5B0, IO3D2 to IO3D0, IO4D2 to IO4D0, IO5D2 to IO5D0): These bits select the general register (GR) function. Bit 6: IOxx2 0 Bit 5: IOxx1 0 Bit 4: IOxx0 0 1 1 0 1 1 0 0 1 1 0 1 GR is an input capture register (input capture by channel 3 and 9 compare-match enabled) Description GR is an output compare register Compare-match disabled; pin output undefined (Initial value) 0 output on GR compare-match 1 output on GR compare-match Toggle output on GR compare-match Input capture disabled (In channel 3 only, GR cannot be written to) Input capture in GR on rising edge at TIOxx pin (GR cannot be written to) Input capture in GR on falling edge at TIOxx pin (GR cannot be written to) Input capture in GR on both rising and falling edges at TIOxx pin (GR cannot be written to) xx = 3B, 4B, 5B, 3D, 4D, or 5D Rev.2.0, 07/03, page 246 of 960 * Bit 3--Clear Counter Enable Flag 3A, 4A, 5A, 3C, 4C, 5C (CCI3A, CCI4A, CCI5A, CCI3C, CCI4C, CCI5C): These bits select enabling or disabling of free-running counter (TCNT) clearing. Bit 3: CCIxx 0 1 Description TCNT clearing disabled TCNT cleared on GR compare-match (Initial value) xx = 3A, 4A, 5A, 3C, 4C, or 5C TCNT is cleared on compare-match only when GR is functioning as an output compare register. * Bits 2 to 0--I/O Control 3A2 to 3A0, 4A2 to 4A0, 5A2 to 5A0, 3C2 to 3C0, 4C2 to 4C0, 5C2 to 5C0 (IO3A2 to IO3A0, IO4A2 to IO4A0, IO5A2 to IO5A0, IO3C2 to IO3C0, IO4C2 to IO4C0, IO5C2 to IO5C0): These bits select the general register (GR) function. Bit 2: IOxx2 0 Bit 1: IOxx1 0 Bit 0: IOxx0 0 1 1 0 1 1 0 0 1 1 0 1 GR is an input capture register (input capture by channel 3 and 9 compare-match enabled) Description GR is an output compare register Compare-match disabled; pin output undefined (Initial value) 0 output on GR compare-match 1 output on GR compare-match Toggle output on GR compare-match Input capture disabled (In channel 3 only, GR cannot be written to) Input capture in GR on rising edge at TIOxx pin (GR connot be written to) Input capture in GR on falling edge at TIOxx pin (GR connot be written to) Input capture in GR on both rising and falling edges at TIOxx pin (GR connot be written to) xx = 3A, 4A, 5A, 3C, 4C, or 5C Rev.2.0, 07/03, page 247 of 960 Timer I/O Control Register 11 (TIOR11) TIOR11 Bit: 7 -- Initial value: R/W: 0 R 6 IO11B2 0 R/W 5 IO11B1 0 R/W 4 IO11B0 0 R/W 3 -- 0 R 2 IO11A2 0 R/W 1 IO11A1 0 R/W 0 IO11A0 0 R/W TIOR11 specifies whether general registers GR11A and GR11B are used as input capture or compare-match registers, and also performs edge detection and output value setting. TIOR11 is initialized to H'00 by a power-on reset, and in hardware standby mode and software standby mode. * Bit 7--Reserved: This bit is always read as 0. The write value should always be 0. * Bits 6 to 4--I/O Control 11B2 to 11B0 (IO11B2 to IO11B0): These bits select the general register (GR) function. Bit 6: IO11B2 0 Bit 5: IO11B1 0 Bit 4: IO11B0 0 1 1 0 1 1 0 0 1 1 0 1 GR is an input capture register Description GR is an output compare register Compare-match disabled; pin output undefined (Initial value) 0 output on GR compare-match 1 output on GR compare-match Toggle output on GR compare-match Input capture disabled Input capture in GR on rising edge at TIO11B pin (GR cannot be written to) Input capture in GR on falling edge at TIO11B pin (GR cannot be written to) Input capture in GR on both rising and falling edges at TIO11B pin (GR cannot be written to) Rev.2.0, 07/03, page 248 of 960 * Bit 3--Reserved: This bit is always read as 0. The write value should always be 0. * Bits 2 to 0--I/O Control 11A2 to 11A0 (IO11A2 to IO11A0): These bits select the general register (GR) function. Bit 2: IO11A2 0 Bit 1: IO11A1 0 Bit 0: IO11A0 0 1 1 0 1 1 0 0 1 1 0 1 GR is an input capture register Description GR is an output compare register Compare-match disabled; pin output undefined (Initial value) 0 output on GR compare-match 1 output on GR compare-match Toggle output on GR compare-match Input capture disabled Input capture in GR on rising edge at TIO11A pin (GR cannot be written to) Input capture in GR on falling edge at TIO11A pin (GR cannot be written to) Input capture in GR on both rising and falling edges at TIO11A pin (GR cannot be written to) 11.2.5 Timer Status Registers (TSR) The timer status registers (TSR) are 16-bit registers. The ATU-II has 11 TSR registers: one each for channels 0, 6 to 9, and 11, two each for channels 1 and 2, and one for channels 3 to 5. For details of channel 10, see section 11.2.26, Channel 10 Registers. Channel 0 1 2 3 4 5 6 7 8 9 11 TSR6 TSR7 TSR8 TSR9 TSR11 Indicates down-counter output end (low) status Indicates event counter compare-match status Indicates input capture, compare-match, and overflow status Indicate cycle register compare-match status Abbreviation TSR0 TSR1A, TSR1B TSR2A, TSR2B TSR3 Indicates input capture, compare-match, and overflow status Function Indicates input capture, interval interrupt, and overflow status Indicate input capture, compare-match, and overflow status Rev.2.0, 07/03, page 249 of 960 The TSR registers are 16-bit readable/writable registers containing flags that indicate free-running counter (TCNT) overflow, channel 0 input capture or interval interrupt generation, channel 3, 4, 5, and 11 general register input capture or compare-match, channel 6 and 7 compare-matches, channel 8 down-counter output end, and channel 9 event counter compare-matches. Each flag is an interrupt source, and issues an interrupt request to the CPU if the interrupt is enabled by the corresponding bit in the timer interrupt enable register (TIER). Each TSR is initialized to H'0000 by a power-on reset, and in hardware standby mode and software standby mode. Timer Status Register 0 (TSR0) TSR0 indicates the status of channel 0 interval interrupts, input capture, and overflow. Bit: 15 -- Initial value: R/W: Bit: 0 R 7 IIF2B Initial value: R/W: 0 R/(W)* 14 -- 0 R 6 IIF2A 0 R/(W)* 13 -- 0 R 5 IIF1 0 R/(W)* 12 -- 0 R 4 OVF0 0 R/(W)* 11 -- 0 R 3 ICF0D 0 R/(W)* 10 -- 0 R 2 ICF0C 0 R/(W)* 9 -- 0 R 1 ICF0B 0 R/(W)* 8 -- 0 R 0 ICF0A 0 R/(W)* Note: * Only 0 can be written to clear the flag. * Bits 15 to 8--Reserved: These bits are always read as 0. The write value should always be 0. * Bit 7--Interval Interrupt Flag 2B (IIF2B): Status flag that indicates the generation of an interval interrupt. Bit 7: IIF2B 0 1 Description [Clearing condition] When IIF2B is read while set to 1, then 0 is written to IIF2B [Setting condition] When interval interrupt selected by ITVRR2B is generated (Initial value) Rev.2.0, 07/03, page 250 of 960 * Bit 6--Interval Interrupt Flag 2A (IIF2A): Status flag that indicates the generation of an interval interrupt. Bit 6: IIF2A 0 1 Description [Clearing condition] When IIF2A is read while set to 1, then 0 is written to IIF2A [Setting condition] When interval interrupt selected by ITVRR2A is generated (Initial value) * Bit 5--Interval Interrupt Flag 1 (IIF1): Status flag that indicates the generation of an interval interrupt. Bit 5: IIF1 0 1 Description [Clearing condition] When IIF1 is read while set to 1, then 0 is written to IIF1 [Setting condition] When interval interrupt selected by ITVRR1 is generated (Initial value) * Bit 4--Overflow Flag 0 (OVF0): Status flag that indicates TCNT0 overflow. Bit 4: OVF0 0 1 Description [Clearing condition] When OVF0 is read while set to 1, then 0 is written to OVF0 (Initial value) [Setting condition] When the TCNT0 value overflows (from H'FFFFFFFF to H'00000000) * Bit 3--Input Capture Flag 0D (ICF0D): Status flag that indicates ICR0D input capture. Bit 3: ICF0D 0 1 Description [Clearing condition] When ICF0D is read while set to 1, then 0 is written to ICF0D (Initial value) [Setting condition] When the TCNT0 value is transferred to the input capture register by an input capture signal. Also set by input capture with a channel 10 compare match as the trigger Rev.2.0, 07/03, page 251 of 960 * Bit 2--Input Capture Flag 0C (ICF0C): Status flag that indicates ICR0C input capture. Bit 2: ICF0C 0 1 Description [Clearing condition] When ICF0C is read while set to 1, then 0 is written to ICF0C (Initial value) [Setting condition] When the TCNT0 value is transferred to the input capture register by an input capture signal * Bit 1--Input Capture Flag 0B (ICF0B): Status flag that indicates ICR0B input capture. Bit 1: ICF0B 0 1 Description [Clearing condition] When ICF0B is read while set to 1, then 0 is written to ICF0B (Initial value) [Setting condition] When the TCNT0 value is transferred to the input capture register by an input capture signal * Bit 0--Input Capture Flag 0A (ICF0A): Status flag that indicates ICR0A input capture. Bit 0: ICF0A 0 1 Description [Clearing condition] When ICF0A is read while set to 1, then 0 is written to ICF0A (Initial value) [Setting condition] When the TCNT0 value is transferred to the input capture register by an input capture signal Rev.2.0, 07/03, page 252 of 960 Timer Status Registers 1A and 1B (TSR1A, TSR1B) TSR1A: TSR1A indicates the status of channel 1 input capture, compare-match, and overflow. Bit: 15 -- Initial value: R/W: Bit: 0 R 7 IMF1H Initial value: R/W: 0 R/(W)* 14 -- 0 R 6 IMF1G 0 R/(W)* 13 -- 0 R 5 IMF1F 0 R/(W)* 12 -- 0 R 4 IMF1E 0 R/(W)* 11 -- 0 R 3 IMF1D 0 R/(W)* 10 -- 0 R 2 IMF1C 0 R/(W)* 9 -- 0 R 1 IMF1B 0 R/(W)* 8 OVF1A 0 R/(W)* 0 IMF1A 0 R/(W)* Note: * Only 0 can be written, to clear the flag. * Bits 15 to 9--Reserved: These bits are always read as 0. The write value should always be 0. * Bit 8--Overflow Flag 1A (OVF1A): Status flag that indicates TCNT1A overflow. Bit 8: OVF1A 0 1 Description [Clearing condition] (Initial value) When OVF1A is read while set to 1, then 0 is written to OVF1A [Setting condition] When the TCNT1A value overflows (from H'FFFF to H'0000) * Bit 7--Input Capture/Compare-Match Flag 1H (IMF1H): Status flag that indicates GR1H input capture or compare-match. Bit 7: IMF1H 0 1 Description [Clearing condition] When IMF1H is read while set to 1, then 0 is written to IMF1H (Initial value) [Setting conditions] * When the TCNT1A value is transferred to GR1H by an input capture signal while GR1H is functioning as an input capture register * When TCNT1A = GR1H while GR1H is functioning as an output compare register Rev.2.0, 07/03, page 253 of 960 * Bit 6--Input Capture/Compare-Match Flag 1G (IMF1G): Status flag that indicates GR1G input capture or compare-match. Bit 6: IMF1G 0 1 Description [Clearing condition] (Initial value) When IMF1G is read while set to 1, then 0 is written to IMF1G [Setting conditions] * When the TCNT1A value is transferred to GR1G by an input capture signal while GR1G is functioning as an input capture register * When TCNT1A = GR1G while GR1G is functioning as an output compare register * Bit 5--Input Capture/Compare-Match Flag 1F (IMF1F): Status flag that indicates GR1F input capture or compare-match. Bit 5: IMF1F 0 1 Description [Clearing condition] When IMF1F is read while set to 1, then 0 is written to IMF1F (Initial value) [Setting conditions] * When the TCNT1A value is transferred to GR1F by an input capture signal while GR1F is functioning as an input capture register * When TCNT1A = GR1F while GR1F is functioning as an output compare register * Bit 4--Input Capture/Compare-Match Flag 1E (IMF1E): Status flag that indicates GR1E input capture or compare-match. Bit 4: IMF1E 0 1 Description [Clearing condition] When IMF1E is read while set to 1, then 0 is written to IMF1E (Initial value) [Setting conditions] * When the TCNT1A value is transferred to GR1E by an input capture signal while GR1E is functioning as an input capture register * When TCNT1A = GR1E while GR1E is functioning as an output compare register Rev.2.0, 07/03, page 254 of 960 * Bit 3--Input Capture/Compare-Match Flag 1D (IMF1D): Status flag that indicates GR1D input capture or compare-match. Bit 3: IMF1D 0 1 Description [Clearing condition] When IMF1D is read while set to 1, then 0 is written to IMF1D (Initial value) [Setting conditions] * When the TCNT1A value is transferred to GR1D by an input capture signal while GR1D is functioning as an input capture register * When TCNT1A = GR1D while GR1D is functioning as an output compare register * Bit 2--Input Capture/Compare-Match Flag 1C (IMF1C): Status flag that indicates GR1C input capture or compare-match. Bit 2: IMF1C 0 1 Description [Clearing condition] When IMF1C is read while set to 1, then 0 is written to IMF1C (Initial value) [Setting conditions] * When the TCNT1A value is transferred to GR1C by an input capture signal while GR1C is functioning as an input capture register * When TCNT1A = GR1C while GR1C is functioning as an output compare register * Bit 1--Input Capture/Compare-Match Flag 1B (IMF1B): Status flag that indicates GR1B input capture or compare-match. Bit 1: IMF1B 0 1 Description [Clearing condition] When IMF1B is read while set to 1, then 0 is written to IMF1B (Initial value) [Setting conditions] * When the TCNT1A value is transferred to GR1B by an input capture signal while GR1B is functioning as an input capture register * When TCNT1A = GR1B while GR1B is functioning as an output compare register Rev.2.0, 07/03, page 255 of 960 * Bit 0--Input Capture/Compare-Match Flag 1A (IMF1A): Status flag that indicates GR1A input capture or compare-match. Bit 0: IMF1A 0 1 Description [Clearing condition] When IMF1A is read while set to 1, then 0 is written to IMF1A (Initial value) [Setting conditions] * When the TCNT1A value is transferred to GR1A by an input capture signal while GR1A is functioning as an input capture register * When TCNT1A = GR1A while GR1A is functioning as an output compare register TSR1B: TSR1B indicates the status of channel 1 compare-match and overflow. Bit: 15 -- Initial value: R/W: Bit: 0 R 7 -- Initial value: R/W: 0 R 14 -- 0 R 6 -- 0 R 13 -- 0 R 5 -- 0 R 12 -- 0 R 4 -- 0 R 11 -- 0 R 3 -- 0 R 10 -- 0 R 2 -- 0 R 9 -- 0 R 1 -- 0 R 8 OVF1B 0 R/(W)* 0 CMF1 0 R/(W)* Note: * Only 0 can be written, to clear the flag. * Bits 15 to 9--Reserved: These bits are always read as 0. The write value should always be 0. * Bit 8--Overflow Flag 1B (OVF1B): Status flag that indicates TCNT1B overflow. Bit 8: OVF1B 0 1 Description [Clearing condition] (Initial value) When OVF1B is read while set to 1, then 0 is written to OVF1B [Setting condition] When the TCNT1B value overflows (from H'FFFF to H'0000) Rev.2.0, 07/03, page 256 of 960 * Bits 7 to 1--Reserved: These bits are always read as 0. The write value should always be 0. * Bit 0--Compare-Match Flag 1 (CMF1): Status flag that indicates OCR1 compare-match. Bit 0: CMF1 0 1 Description [Clearing condition] When CMF1 is read while set to 1, then 0 is written to CMF1 [Setting condition] When TCNT1B = OCR1 (Initial value) Timer Status Registers 2A and 2B (TSR2A, TSR2B) TSR2A: TSR2A indicates the status of channel 2 input capture, compare-match, and overflow. Bit: 15 -- Initial value: R/W: Bit: 0 R 7 IMF2H Initial value: R/W: 0 R/(W)* 14 -- 0 R 6 IMF2G 0 R/(W)* 13 -- 0 R 5 IMF2F 0 R/(W)* 12 -- 0 R 4 IMF2E 0 R/(W)* 11 -- 0 R 3 IMF2D 0 R/(W)* 10 -- 0 R 2 IMF2C 0 R/(W)* 9 -- 0 R 1 IMF2B 0 R/(W)* 8 OVF2A 0 R/(W)* 0 IMF2A 0 R/(W)* Note: * Only 0 can be written to clear the flag. * Bits 15 to 9--Reserved: These bits are always read as 0. The write value should always be 0. * Bit 8--Overflow Flag 2A (OVF2A): Status flag that indicates TCNT2A overflow. Bit 8: OVF2A 0 1 Description [Clearing condition] (Initial value) When OVF2A is read while set to 1, then 0 is written to OVF2A [Setting condition] When the TCNT2A value overflows (from H'FFFF to H'0000) Rev.2.0, 07/03, page 257 of 960 * Bit 7--Input Capture/Compare-Match Flag 2H (IMF2H): Status flag that indicates GR2H input capture or compare-match. Bit 7: IMF2H 0 1 Description [Clearing condition] When IMF2H is read while set to 1, then 0 is written to IMF2H (Initial value) [Setting conditions] * When the TCNT2A value is transferred to GR2H by an input capture signal while GR2H is functioning as an input capture register * When TCNT2A = GR2H while GR2H is functioning as an output compare register * Bit 6--Input Capture/Compare-Match Flag 2G (IMF2G): Status flag that indicates GR2G input capture or compare-match. Bit 6: IMF2G 0 1 Description [Clearing condition] (Initial value) When IMF2G is read while set to 1, then 0 is written to IMF2G [Setting conditions] * When the TCNT2A value is transferred to GR2G by an input capture signal while GR2G is functioning as an input capture register * When TCNT2A = GR2G while GR2G is functioning as an output compare register * Bit 5--Input Capture/Compare-Match Flag 2F (IMF2F): Status flag that indicates GR2F input capture or compare-match. Bit 5: IMF2F 0 1 Description [Clearing condition] When IMF2F is read while set to 1, then 0 is written to IMF2F (Initial value) [Setting conditions] * When the TCNT2A value is transferred to GR2F by an input capture signal while GR2F is functioning as an input capture register * When TCNT2A = GR2F while GR2F is functioning as an output compare register Rev.2.0, 07/03, page 258 of 960 * Bit 4--Input Capture/Compare-Match Flag 2E (IMF2E): Status flag that indicates GR2E input capture or compare-match. Bit 4: IMF2E 0 1 Description [Clearing condition] When IMF2E is read while set to 1, then 0 is written to IMF2E (Initial value) [Setting conditions] * When the TCNT2A value is transferred to GR2E by an input capture signal while GR2E is functioning as an input capture register * When TCNT2A = GR2E while GR2E is functioning as an output compare register * Bit 3--Input Capture/Compare-Match Flag 2D (IMF2D): Status flag that indicates GR2D input capture or compare-match. Bit 3: IMF2D 0 1 Description [Clearing condition] When IMF2D is read while set to 1, then 0 is written to IMF2D (Initial value) [Setting conditions] * When the TCNT2A value is transferred to GR2D by an input capture signal while GR2D is functioning as an input capture register * When TCNT2A = GR2D while GR2D is functioning as an output compare register * Bit 2--Input Capture/Compare-Match Flag 2C (IMF2C): Status flag that indicates GR2C input capture or compare-match. Bit 2: IMF2C 0 1 Description [Clearing condition] When IMF2C is read while set to 1, then 0 is written to IMF2C (Initial value) [Setting conditions] * When the TCNT2A value is transferred to GR2C by an input capture signal while GR2C is functioning as an input capture register * When TCNT2A = GR2C while GR2C is functioning as an output compare register Rev.2.0, 07/03, page 259 of 960 * Bit 1--Input Capture/Compare-Match Flag 2B (IMF2B): Status flag that indicates GR2B input capture or compare-match. Bit 1: IMF2B 0 1 Description [Clearing condition] When IMF2B is read while set to 1, then 0 is written to IMF2B [Setting conditions] * * When the TCNT2A value is transferred to GR2B by an input capture signal while GR2B is functioning as an input capture register When TCNT2A = GR2B while GR2B is functioning as an output compare register (Initial value) * Bit 0--Input Capture/Compare-Match Flag 2A (IMF2A): Status flag that indicates GR2A input capture or compare-match. Bit 0: IMF2A 0 1 Description [Clearing condition] When IMF2A is read while set to 1, then 0 is written to IMF2A (Initial value) [Setting conditions] * When the TCNT2A value is transferred to GR2A by an input capture signal while GR2A is functioning as an input capture register * When TCNT2A = GR2A while GR2A is functioning as an output compare register TSR2B: TSR2B indicates the status of channel 2 compare-match and overflow. Bit: 15 -- Initial value: R/W: Bit: 0 R 7 14 -- 0 R 6 13 -- 0 R 5 12 -- 0 R 4 11 -- 0 R 3 10 -- 0 R 2 9 -- 0 R 1 8 OVF2B 0 R/(W)* 0 CMF2A 0 R/(W)* CMF2H CMF2G CMF2F Initial value: R/W: 0 R/(W)* 0 R/(W)* 0 R/(W)* CMF2E CMF2D CMF2C CMF2B 0 R/(W)* 0 R/(W)* 0 R/(W)* 0 R/(W)* Note: * Only 0 can be written to clear the flag. Rev.2.0, 07/03, page 260 of 960 * Bits 15 to 9--Reserved: These bits are always read as 0. The write value should always be 0. * Bit 8--Overflow Flag 2B (OVF2B): Status flag that indicates TCNT2B overflow. Bit 8: OVF2B 0 1 Description [Clearing condition] (Initial value) When OVF2B is read while set to 1, then 0 is written to OVF2B [Setting condition] When the TCNT2B value overflows (from H'FFFF to H'0000) * Bit 7--Compare-Match Flag 2H (CMF2H): Status flag that indicates OCR2H compare-match. Bit 7: CMF2H 0 1 Description [Clearing condition] (Initial value) When CMF2H is read while set to 1, then 0 is written to CMF2H [Setting condition] When TCNT2B = OCR2H * Bit 6--Compare-Match Flag 2G (CMF2G): Status flag that indicates OCR2G compare-match. Bit 6: CMF2G 0 1 Description [Clearing condition] (Initial value) When CMF2G is read while set to 1, then 0 is written to CMF2G [Setting condition] When TCNT2B = OCR2G * Bit 5--Compare-Match Flag 2F (CMF2F): Status flag that indicates OCR2F compare-match. Bit 5: CMF2F 0 1 Description [Clearing condition] (Initial value) When CMF2F is read while set to 1, then 0 is written to CMF2F [Setting condition] When TCNT2B = OCR2F * Bit 4--Compare-Match Flag 2E (CMF2E): Status flag that indicates OCR2E compare-match. Bit 4: CMF2E 0 1 Description [Clearing condition] (Initial value) When CMF2E is read while set to 1, then 0 is written to CMF2E [Setting condition] When TCNT2B = OCR2E Rev.2.0, 07/03, page 261 of 960 * Bit 3--Compare-Match Flag 2D (CMF2D): Status flag that indicates OCR2D compare-match. Bit 3: CMF2D 0 1 Description [Clearing condition] (Initial value) When CMF2D is read while set to 1, then 0 is written to CMF2D [Setting condition] When TCNT2B = OCR2D * Bit 2--Compare-Match Flag 2C (CMF2C): Status flag that indicates OCR2C compare-match. Bit 2: CMF2C 0 1 Description [Clearing condition] (Initial value) When CMF2C is read while set to 1, then 0 is written to CMF2C [Setting condition] When TCNT2B = OCR2C * Bit 1--Compare-Match Flag 2B (CMF2B): Status flag that indicates OCR2B compare-match. Bit 1: CMF2B 0 1 Description [Clearing condition] (Initial value) When CMF2B is read while set to 1, then 0 is written to CMF2B [Setting condition] When TCNT2B = OCR2B * Bit 0--Compare-Match Flag 2A (CMF2A): Status flag that indicates OCR2A compare-match. Bit 0: CMF2A 0 1 Description [Clearing condition] (Initial value) When CMF2A is read while set to 1, then 0 is written to CMF2A [Setting condition] When TCNT2B = OCR2A Rev.2.0, 07/03, page 262 of 960 Timer Status Register 3 (TSR3) TSR3 indicates the status of channel 3 to 5 input capture, compare-match, and overflow. Bit: 15 -- Initial value: R/W: Bit: 0 R 7 IMF4C Initial value: R/W: 0 R/(W)* 14 OVF5 0 R/(W)* 6 IMF4B 0 R/(W)* 13 IMF5D 0 R/(W)* 5 IMF4A 0 R/(W)* 12 IMF5C 0 R/(W)* 4 OVF3 0 R/(W)* 11 IMF5B 0 R/(W)* 3 IMF3D 0 R/(W)* 10 IMF5A 0 R/(W)* 2 IMF3C 0 R/(W)* 9 OVF4 0 R/(W)* 1 IMF3B 0 R/(W)* 8 IMF4D 0 R/(W)* 0 IMF3A 0 R/(W)* Note: * Only 0 can be written to clear the flag. * Bit 15--Reserved: This bit is always read as 0. The write value should always be 0. * Bit 14--Overflow Flag 5 (OVF5): Status flag that indicates TCNT5 overflow. Bit 14: OVF5 0 1 Description [Clearing condition] When OVF5 is read while set to 1, then 0 is written to OVF5 [Setting condition] When the TCNT5 value overflows (from H'FFFF to H'0000) (Initial value) * Bit 13--Input Capture/Compare-Match Flag 5D (IMF5D): Status flag that indicates GR5D input capture or compare-match. Bit 13: IMF5D 0 1 Description [Clearing condition] When IMF5D is read while set to 1, then 0 is written to IMF5D (Initial value) [Setting conditions] * When the TCNT5 value is transferred to GR5D by an input capture signal while GR5D is functioning as an input capture register * * When TCNT5 = GR5D while GR5D is functioning as an output compare register When TCNT5 = GR5D while GR5D is functioning as a cycle register in PWM mode Rev.2.0, 07/03, page 263 of 960 * Bit 12--Input Capture/Compare-Match Flag 5C (IMF5C): Status flag that indicates GR5C input capture or compare-match. The flag is not set in PWM mode. Bit 12: IMF5C 0 1 Description [Clearing condition] When IMF5C is read while set to 1, then 0 is written to IMF5C (Initial value) [Setting conditions] * When the TCNT5 value is transferred to GR5C by an input capture signal while GR5C is functioning as an input capture register * When TCNT5 = GR5C while GR5C is functioning as an output compare register * Bit 11--Input Capture/Compare-Match Flag 5B (IMF5B): Status flag that indicates GR5B input capture or compare-match. The flag is not set in PWM mode. Bit 11: IMF5B 0 1 Description [Clearing condition] When IMF5B is read while set to 1, then 0 is written to IMF5B (Initial value) [Setting conditions] * When the TCNT5 value is transferred to GR5B by an input capture signal while GR5B is functioning as an input capture register * When TCNT5 = GR5B while GR5B is functioning as an output compare register * Bit 10--Input Capture/Compare-Match Flag 5A (IMF5A): Status flag that indicates GR5A input capture or compare-match. The flag is not set in PWM mode. Bit 10: IMF5A 0 1 Description [Clearing condition] When IMF5A is read while set to 1, then 0 is written to IMF5A (Initial value) [Setting conditions] * When the TCNT5 value is transferred to GR5A by an input capture signal while GR5A is functioning as an input capture register * When TCNT5 = GR5A while GR5A is functioning as an output compare register Rev.2.0, 07/03, page 264 of 960 * Bit 9--Overflow Flag 4 (OVF4): Status flag that indicates TCNT4 overflow. Bit 9: OVF4 0 1 Description [Clearing condition] When OVF4 is read while set to 1, then 0 is written to OVF4 [Setting condition] When the TCNT4 value overflows (from H'FFFF to H'0000) (Initial value) * Bit 8--Input Capture/Compare-Match Flag 4D (IMF4D): Status flag that indicates GR4D input capture or compare-match. Bit 8: IMF4D 0 1 Description [Clearing condition] When IMF4D is read while set to 1, then 0 is written to IMF4D (Initial value) [Setting conditions] * When the TCNT4 value is transferred to GR4D by an input capture signal while GR4D is functioning as an input capture register * * When TCNT4 = GR4D while GR4D is functioning as an output compare register When TCNT4 = GR4D while GR4D is functioning as a PWM mode synchronous register * Bit 7--Input Capture/Compare-Match Flag 4C (IMF4C): Status flag that indicates GR4C input capture or compare-match. The flag is not set in PWM mode. Bit 7: IMF4C 0 1 Description [Clearing condition] When IMF4C is read while set to 1, then 0 is written to IMF4C (Initial value) [Setting conditions] * When the TCNT4 value is transferred to GR4C by an input capture signal while GR4C is functioning as an input capture register * When TCNT4 = GR4C while GR4C is functioning as an output compare register Rev.2.0, 07/03, page 265 of 960 * Bit 6--Input Capture/Compare-Match Flag 4B (IMF4B): Status flag that indicates GR4B input capture or compare-match. The flag is not set in PWM mode. Bit 6: IMF4B 0 1 Description [Clearing condition] When IMF4B is read while set to 1, then 0 is written to IMF4B (Initial value) [Setting conditions] * When the TCNT4 value is transferred to GR4B by an input capture signal while GR4B is functioning as an input capture register * When TCNT4 = GR4B while GR4B is functioning as an output compare register * Bit 5--Input Capture/Compare-Match Flag 4A (IMF4A): Status flag that indicates GR4A input capture or compare-match. The flag is not set in PWM mode. Bit 5: IMF4A 0 1 Description [Clearing condition] When IMF4A is read while set to 1, then 0 is written to IMF4A (Initial value) [Setting conditions] * When the TCNT4 value is transferred to GR4A by an input capture signal while GR4A is functioning as an input capture register * When TCNT4 = GR4A while GR4A is functioning as an output compare register * Bit 4--Overflow Flag 3 (OVF3): Status flag that indicates TCNT3 input capture or comparematch. Bit 4: OVF3 0 1 Description [Clearing condition] When OVF3 is read while set to 1, then 0 is written to OVF3 [Setting condition] When the TCNT3 value overflows (from H'FFFF to H'0000) (Initial value) Rev.2.0, 07/03, page 266 of 960 * Bit 3--Input Capture/Compare-Match Flag 3D (IMF3D): Status flag that indicates GR5D input capture or compare-match. Bit 3: IMF3D 0 1 Description [Clearing condition] When IMF3D is read while set to 1, then 0 is written to IMF3D (Initial value) [Setting conditions] * When the TCNT3 value is transferred to GR3D by an input capture signal while GR3D is functioning as an input capture register. However, IMF3D is not set by input capture with a channel 9 compare match as the trigger * * When TCNT3 = GR3D while GR3D is functioning as an output compare register When TCNT3 = GR3D while GR3D is functioning as a synchronous register in PWM mode * Bit 2--Input Capture/Compare-Match Flag 3C (IMF3C): Status flag that indicates GR3C input capture or compare-match. The flag is not set in PWM mode. Bit 2: IMF3C 0 1 Description [Clearing condition] When IMF3C is read while set to 1, then 0 is written to IMF3C (Initial value) [Setting conditions] * When the TCNT3 value is transferred to GR3C by an input capture signal while GR3C is functioning as an input capture register. However, IMF3C is not set by input capture with a channel 9 compare match as the trigger * When TCNT3 = GR3C while GR3C is functioning as an output compare register * Bit 1--Input Capture/Compare-Match Flag 3B (IMF3B): Status flag that indicates GR3B input capture or compare-match. The flag is not set in PWM mode. Bit 1: IMF3B 0 1 Description [Clearing condition] When IMF3B is read while set to 1, then 0 is written to IMF3B (Initial value) [Setting conditions] * When the TCNT3 value is transferred to GR3B by an input capture signal while GR3B is functioning as an input capture register. However, IMF3B is not set by input capture with a channel 9 compare match as the trigger * When TCNT3 = GR3B while GR3B is functioning as an output compare register Rev.2.0, 07/03, page 267 of 960 * Bit 0--Input Capture/Compare-Match Flag 3A (IMF3A): Status flag that indicates GR3A input capture or compare-match. The flag is not set in PWM mode. Bit 0: IMF3A 0 1 Description [Clearing condition] When IMF3A is read while set to 1, then 0 is written to IMF3A (Initial value) [Setting conditions] * When the TCNT3 value is transferred to GR3A by an input capture signal while GR3A is functioning as an input capture register. However, IMF3A is not set by input capture with a channel 9 compare match as the trigger * When TCNT3 = GR3A while GR3A is functioning as an output compare register Timer Status Registers 6 and 7 (TSR6, TSR7) TSR6 and TRS7 indicate the channel 6 and 7 free-running counter up-count and down-count status, and cycle register compare status. Bit: 15 -- Initial value: R/W: Bit: 0 R 7 UDxD Initial value: R/W: 0 R 14 -- 0 R 6 UDxC 0 R 13 -- 0 R 5 UDxB 0 R 12 -- 0 R 4 UDxA 0 R 11 -- 0 R 3 CMFxD 0 R/(W)* 10 -- 0 R 2 CMFxC 0 R/(W)* 9 -- 0 R 1 CMFxB 0 R/(W)* 8 -- 0 R 0 CMFxA 0 R/(W)* Note: * Only 0 can be written to clear the flag. x = 6 or 7 UDxA to UDxD relate to TSR6 only. Bits relating to TSR7 always read 0. * Bits 15 to 8--Reserved: These bits are always read as 0. The write value should always be 0. * Bit 7--Count-Up/Count-Down Flag 6D (UD6D): Status flag that indicates the TCNT6D count operation. Bit 7: UD6D 0 1 Description Free-running counter TCNT6D operates as an up-counter Free-running counter TCNT6D operates as a down-counter Rev.2.0, 07/03, page 268 of 960 * Bit 6--Count-Up/Count-Down Flag 6C (UD6C): Status flag that indicates the TCNT6C count operation. Bit 6: UD6C 0 1 Description Free-running counter TCNT6C operates as an up-counter Free-running counter TCNT6C operates as a down-counter * Bit 5--Count-Up/Count-Down Flag 6B (UD6B): Status flag that indicates the TCNT6B count operation. Bit 5: UD6B 0 1 Description Free-running counter TCNT6B operates as an up-counter Free-running counter TCNT6B operates as a down-counter * Bit 4--Count-Up/Count-Down Flag 6A (UD6A): Status flag that indicates the TCNT6A count operation. Bit 4: UD6A 0 1 Description Free-running counter TCNT6A operates as an up-counter Free-running counter TCNT6A operates as a down-counter * Bit 3--Cycle Register Compare-Match Flag 6D/7D (CMF6D/CMF7D): Status flag that indicates CYLRxD compare-match. Bit 3: CMFxD 0 1 Description [Clearing condition] (Initial value) When CMFxD is read while set to 1, then 0 is written to CMFxD [Setting conditions] * When TCNTxD = CYLRxD (in non-complementary PWM mode) * x = 6 or 7 When TCNT6D = H'0000 in a down-count (in complementary PWM mode) Rev.2.0, 07/03, page 269 of 960 * Bit 2--Cycle Register Compare-Match Flag 6C/7C (CMF6C/CMF7C): Status flag that indicates CYLRxC compare-match. Bit 2: CMFxC 0 1 Description [Clearing condition] (Initial value) When CMFxC is read while set to 1, then 0 is written to CMFxC [Setting conditions] * When TCNTxC = CYLRxC (in non-complementary PWM mode) * x = 6 or 7 When TCNT6C = H'0000 in a down-count (in complementary PWM mode) * Bit 1--Cycle Register Compare-Match Flag 6B/7B (CMF6B/CMF7B): Status flag that indicates CYLRxB compare-match. Bit 1: CMFxB 0 1 Description [Clearing condition] (Initial value) When CMFxB is read while set to 1, then 0 is written to CMFxB [Setting conditions] * When TCNTxB = CYLRxB (in non-complementary PWM mode) * x = 6 or 7 When TCNT6B = H'0000 in a down-count (in complementary PWM mode) * Bit 0--Cycle Register Compare-Match Flag 6A/7A (CMF6A/CMF7A): Status flag that indicates CYLRxA compare-match. Bit 0: CMFxA 0 1 Description [Clearing condition] (Initial value) When CMFxA is read while set to 1, then 0 is written to CMFxA [Setting conditions] * When TCNTxA = CYLRxA (in non-complementary PWM mode) * x = 6 or 7 When TCNT6A = H'0000 in a down-count (in complementary PWM mode) Rev.2.0, 07/03, page 270 of 960 Timer Status Register 8 (TSR8) TSR8 indicates the channel 8 one-shot pulse status. Bit: 15 OSF8P Initial value: R/W: Bit: 0 R/(W)* 7 OSF8H Initial value: R/W: 0 R/(W)* 14 OSF8O 0 R/(W)* 6 OSF8G 0 R/(W)* 13 OSF8N 0 R/(W)* 5 OSF8F 0 R/(W)* 12 OSF8M 0 R/(W)* 4 OSF8E 0 R/(W)* 11 OSF8L 0 R/(W)* 3 OSF8D 0 R/(W)* 10 OSF8K 0 R/(W)* 2 OSF8C 0 R/(W)* 9 OSF8J 0 R/(W)* 1 OSF8B 0 R/(W)* 8 OSF8I 0 R/(W)* 0 OSF8A 0 R/(W)* Note: * Only 0 can be written to clear the flag. * Bit 15--One-Shot Pulse Flag 8P (OSF8P): Status flag that indicates a DCNT8P one-shot pulse. Bit 15: OSF8P 0 1 Description [Clearing condition] (Initial value) When OSF8P is read while set to 1, then 0 is written to OSF8P [Setting condition] When DCNT8P underflows * Bit 14--One-Shot Pulse Flag 8O (OSF8O): Status flag that indicates a DCNT8O one-shot pulse. Bit 14: OSF8O 0 1 Description [Clearing condition] (Initial value) When OSF8O is read while set to 1, then 0 is written to OSF8O [Setting condition] When DCNT8O underflows Rev.2.0, 07/03, page 271 of 960 * Bit 13--One-Shot Pulse Flag 8N (OSF8N): Status flag that indicates a DCNT8N one-shot pulse. Bit 13: OSF8N 0 1 Description [Clearing condition] (Initial value) When OSF8N is read while set to 1, then 0 is written to OSF8N [Setting condition] When DCNT8N underflows * Bit 12--One-Shot Pulse Flag 8M (OSF8M): Status flag that indicates a DCNT8M one-shot pulse. Bit 12: OSF8M 0 1 Description [Clearing condition] (Initial value) When OSF8M is read while set to 1, then 0 is written to OSF8M [Setting condition] When DCNT8M underflows * Bit 11--One-Shot Pulse Flag 8L (OSF8L): Status flag that indicates a DCNT8L one-shot pulse. Bit 11: OSF8L 0 1 Description [Clearing condition] (Initial value) When OSF8L is read while set to 1, then 0 is written to OSF8L [Setting condition] When DCNT8L underflows * Bit 10--One-Shot Pulse Flag 8K (OSF8K): Status flag that indicates a DCNT8K one-shot pulse. Bit 10: OSF8K 0 1 Description [Clearing condition] (Initial value) When OSF8K is read while set to 1, then 0 is written to OSF8K [Setting condition] When DCNT8K underflows Rev.2.0, 07/03, page 272 of 960 * Bit 9--One-Shot Pulse Flag 8J (OSF8J): Status flag that indicates a DCNT8J one-shot pulse. Bit 9: OSF8J 0 1 Description [Clearing condition] (Initial value) When OSF8J is read while set to 1, then 0 is written to OSF8J [Setting condition] When DCNT8J underflows * Bit 8--One-Shot Pulse Flag 8I (OSF8I): Status flag that indicates a DCNT8I one-shot pulse. Bit 8: OSF8I 0 1 Description [Clearing condition] When OSF8I is read while set to 1, then 0 is written to OSF8I [Setting condition] When DCNT8I underflows (Initial value) * Bit 7--One-Shot Pulse Flag 8H (OSF8H): Status flag that indicates a DCNT8H one-shot pulse. Bit 7: OSF8H 0 1 Description [Clearing condition] (Initial value) When OSF8H is read while set to 1, then 0 is written to OSF8H [Setting condition] When DCNT8H underflows * Bit 6--One-Shot Pulse Flag 8G (OSF8G): Status flag that indicates a DCNT8G one-shot pulse. Bit 6: OSF8G 0 1 Description [Clearing condition] (Initial value) When OSF8G is read while set to 1, then 0 is written to OSF8G [Setting condition] When DCNT8G underflows Rev.2.0, 07/03, page 273 of 960 * Bit 5--One-Shot Pulse Flag 8F (OSF8F): Status flag that indicates a DCNT8F one-shot pulse. Bit 5: OSF8F 0 1 Description [Clearing condition] (Initial value) When OSF8F is read while set to 1, then 0 is written to OSF8F [Setting condition] When DCNT8F underflows * Bit 4--One-Shot Pulse Flag 8E (OSF8E): Status flag that indicates a DCNT8E one-shot pulse. Bit 4: OSF8E 0 1 Description [Clearing condition] (Initial value) When OSF8E is read while set to 1, then 0 is written to OSF8E [Setting condition] When DCNT8E underflows * Bit 3--One-Shot Pulse Flag 8D (OSF8D): Status flag that indicates a DCNT8D one-shot pulse. Bit 3: OSF8D 0 1 Description [Clearing condition] (Initial value) When OSF8D is read while set to 1, then 0 is written to OSF8D [Setting condition] When DCNT8D underflows * Bit 2--One-Shot Pulse Flag 8C (OSF8C): Status flag that indicates a DCNT8C one-shot pulse. Bit 2: OSF8C 0 1 Description [Clearing condition] (Initial value) When OSF8C is read while set to 1, then 0 is written to OSF8C [Setting condition] When DCNT8C underflows * Bit 1--One-Shot Pulse Flag 8B (OSF8B): Status flag that indicates a DCNT8B one-shot pulse. Bit 1: OSF8B 0 1 Description [Clearing condition] (Initial value) When OSF8B is read while set to 1, then 0 is written to OSF8B [Setting condition] When DCNT8B underflows Rev.2.0, 07/03, page 274 of 960 * Bit 0--One-Shot Pulse Flag 8A (OSF8A): Status flag that indicates a DCNT8A one-shot pulse. Bit 0: OSF8A 0 1 Description [Clearing condition] (Initial value) When OSF8A is read while set to 1, then 0 is written to OSF8A [Setting condition] When DCNT8A underflows Timer Status Register 9 (TSR9) TSR9 indicates the channel 9 event counter compare-match status. Bit: 15 -- Initial value: R/W: Bit: 0 R 7 -- Initial value: R/W: 0 R 14 -- 0 R 6 -- 0 R 13 -- 0 R 5 CMF9F 0 R/(W)* 12 -- 0 R 4 11 -- 0 R 3 10 -- 0 R 2 9 -- 0 R 1 8 -- 0 R 0 CMF9A 0 R/(W)* CMF9E CMF9D CMF9C CMF9B 0 R/(W)* 0 R/(W)* 0 R/(W)* 0 R/(W)* Note: * Only 0 can be written to clear the flag. * Bits 15 to 6--Reserved: These bits are always read as 0. The write value should always be 0. * Bit 5--Compare-Match Flag 9F (CMF9F): Status flag that indicates GR9F compare-match. Bit 5: CMF9F 0 1 Description [Clearing condition] (Initial value) When CMF9F is read while set to 1, then 0 is written to CMF9F [Setting condition] When the next edge is input while ECNT9F = GR9F Rev.2.0, 07/03, page 275 of 960 * Bit 4--Compare-Match Flag 9E (CMF9E): Status flag that indicates GR9E compare-match. Bit 4: CMF9E 0 1 Description [Clearing condition] (Initial value) When CMF9E is read while set to 1, then 0 is written to CMF9E [Setting condition] When the next edge is input while ECNT9E = GR9E * Bit 3--Compare-Match Flag 9D (CMF9D): Status flag that indicates GR9D compare-match. Bit 3: CMF9D 0 1 Description [Clearing condition] (Initial value) When CMF9D is read while set to 1, then 0 is written to CMF9D [Setting condition] When the next edge is input while ECNT9D = GR9D * Bit 2--Compare-Match Flag 9C (CMF9C): Status flag that indicates GR9C compare-match. Bit 2: CMF9C 0 1 Description [Clearing condition] (Initial value) When CMF9C is read while set to 1, then 0 is written to CMF9C [Setting condition] When the next edge is input while ECNT9C = GR9C * Bit 1--Compare-Match Flag 9B (CMF9B): Status flag that indicates GR9B compare-match. Bit 1: CMF9B 0 1 Description [Clearing condition] (Initial value) When CMF9B is read while set to 1, then 0 is written to CMF9B [Setting condition] When the next edge is input while ECNT9B = GR9B * Bit 0--Compare-Match Flag 9A (CMF9A): Status flag that indicates GR9A compare-match. Bit 0: CMF9A 0 1 Description [Clearing condition] (Initial value) When CMF9A is read while set to 1, then 0 is written to CMF9A [Setting condition] When the next edge is input while ECNT9A = GR9A Rev.2.0, 07/03, page 276 of 960 Timer Status Register 11 (TSR11) TSR11 indicates the status of channel 11 input capture, compare-match, and overflow. Bit: 15 -- Initial value: R/W: Bit: 0 R 7 -- Initial value: R/W: 0 R 14 -- 0 R 6 -- 0 R 13 -- 0 R 5 -- 0 R 12 -- 0 R 4 -- 0 R 11 -- 0 R 3 -- 0 R 10 -- 0 R 2 -- 0 R 9 -- 0 R 1 8 OVF11 0 R/(W)* 0 IMF11B IMF11A 0 R/(W)* 0 R/(W)* Note: * Only 0 can be written to clear the flag. * Bits 15 to 9--Reserved: These bits are always read as 0. The write value should always be 0. * Bit 8--Overflow Flag 11 (OVF11): Status flag that indicates TCNT11 overflow. Bit 8: OVF11 0 1 Description [Clearing condition] (Initial value) When OVF11 is read while set to 1, then 0 is written to OVF11 [Setting condition] When the TCNT11 value overflows (from H'FFFF to H'0000) * Bits 7 to 2--Reserved: These bits are always read as 0. The write value should always be 0. * Bit 1--Input Capture/Compare-Match Flag 11B (IMF11B): Status flag that indicates GR11B input capture or compare-match. Bit 1: IMF11B 0 1 Description [Clearing condition] (Initial value) When IMF11B is read while set to 1, then 0 is written to IMF11B [Setting conditions] * When the TCNT11 value is transferred to GR11B by an input capture signal while GR11B is functioning as an input capture register * When TCNT11 = GR11B while GR11B is functioning as an output compare register Rev.2.0, 07/03, page 277 of 960 * Bit 0--Input Capture/Compare-Match Flag 11A (IMF11A): Status flag that indicates GR11A input capture or compare-match. Bit 0: IMF11A 0 1 Description [Clearing condition] (Initial value) When IMF11A is read while set to 1, then 0 is written to IMF11A [Setting conditions] * When the TCNT11 value is transferred to GR11A by an input capture signal while GR11A is functioning as an input capture register * When TCNT11 = GR11A while GR11A is functioning as an output compare register 11.2.6 Timer Interrupt Enable Registers (TIER) The timer interrupt enable registers (TIER) are 16-bit registers. The ATU-II has 11 TIER registers: one each for channels 0, 6 to 9, and 11, two each for channels 1 and 2, and one for channels 3 to 5. For details of channel 10, see section 11.2.26, Channel 10 Registers. Channel 0 1 2 3 4 5 6 7 8 9 11 TIER6 TIER7 TIER8 TIER9 TIER11 Control cycle register compare-match interrupt request enabling/disabling. Controls down-counter output end (low) interrupt request enabling/disabling. Controls event counter compare-match interrupt request enabling/disabling. Controls input capture, compare-match, and overflow interrupt request enabling/disabling. Abbreviation TIER0 TIER1A, TIER1B TIER2A, TIER2B TIER3 Function Controls input capture, and overflow interrupt request enabling/disabling. Control input capture, compare-match, and overflow interrupt request enabling/disabling. Controls input capture, compare-match, and overflow interrupt request enabling/disabling. The TIER registers are 16-bit readable/writable registers that control enabling/disabling of freerunning counter (TCNT) overflow interrupt requests, channel 0 input capture interrupt requests, channel 1 to 5 and 11 general register input capture/compare-match interrupt requests, channel 6 and 7 compare-match interrupt requests, channel 8 down-counter output end interrupt requests, and channel 9 event counter compare-match interrupt requests. Rev.2.0, 07/03, page 278 of 960 Each TIER is initialized to H'0000 by a power-on reset, and in hardware standby mode and software standby mode. Timer Interrupt Enable Register 0 (TIER0) TIER0 controls enabling/disabling of channel 0 input capture and overflow interrupt requests. Bit: 15 -- Initial value: R/W: Bit: 0 R 7 -- Initial value: R/W: 0 R 14 -- 0 R 6 -- 0 R 13 -- 0 R 5 -- 0 R 12 -- 0 R 4 OVE0 0 R/W 11 -- 0 R 3 ICE0D 0 R/W 10 -- 0 R 2 ICE0C 0 R/W 9 -- 0 R 1 ICE0B 0 R/W 8 -- 0 R 0 ICE0A 0 R/W * Bits 15 to 5--Reserved: These bits are always read as 0. The write value should always be 0. * Bit 4--Overflow Interrupt Enable 0 (OVE0): Enables or disables interrupt requests by the overflow flag (OVF0) in TSR0 when OVF0 is set to 1. Bit 4: OVE0 0 1 Description OVI0 interrupt requested by OVF0 is disabled OVI0 interrupt requested by OVF0 is enabled (Initial value) * Bit 3--Input Capture Interrupt Enable 0D (ICE0D): Enables or disables interrupt requests by the input capture flag (ICF0D) in TSR0 when ICF0D is set to 1. Setting the DMAC while interrupt requests are enabled allows the DMAC to be activated by an interrupt request. Bit 3: ICE0D 0 1 Description ICI0D interrupt requested by ICF0D is disabled ICI0D interrupt requested by ICF0D is enabled (Initial value) Rev.2.0, 07/03, page 279 of 960 * Bit 2--Input Capture Interrupt Enable 0C (ICE0C): Enables or disables interrupt requests by the input capture flag (ICF0C) in TSR0 when ICF0C is set to 1. Setting the DMAC while interrupt requests are enabled allows the DMAC to be activated by an interrupt request. Bit 2: ICE0C 0 1 Description ICI0C interrupt requested by ICF0C is disabled ICI0C interrupt requested by ICF0C is enabled (Initial value) * Bit 1--Input Capture Interrupt Enable 0B (ICE0B): Enables or disables interrupt requests by the input capture flag (ICF0B) in TSR0 when ICF0B is set to 1. Setting the DMAC while interrupt requests are enabled allows the DMAC to be activated by an interrupt request. Bit 1: ICE0B 0 1 Description ICI0B interrupt requested by ICF0B is disabled ICI0B interrupt requested by ICF0B is enabled (Initial value) * Bit 0--Input Capture Interrupt Enable 0A (ICE0A): Enables or disables interrupt requests by the input capture flag (ICF0A) in TSR0 when ICF0A is set to 1. Setting the DMAC while interrupt requests are enabled allows the DMAC to be activated by an interrupt request. Bit 0: ICE0A 0 1 Description ICI0A interrupt requested by ICF0A is disabled ICI0A interrupt requested by ICF0A is enabled (Initial value) Timer Interrupt Enable Registers 1A and 1B (TIER1A, TIER1B) TIER1A: TIER1A controls enabling/disabling of channel 1 input capture, compare-match, and overflow interrupt requests. Bit: Bit name: Initial value: R/W: Bit: Bit name: Initial value: R/W: 15 -- 0 R 7 IME1H 0 R/W 14 -- 0 R 6 IME1G 0 R/W 13 -- 0 R 5 IME1F 0 R/W 12 -- 0 R 4 IME1E 0 R/W 11 -- 0 R 3 IME1D 0 R/W 10 -- 0 R 2 IME1C 0 R/W 9 -- 0 R 1 IME1B 0 R/W 8 OVE1A 0 R/W 0 IME1A 0 R/W Rev.2.0, 07/03, page 280 of 960 * Bits 15 to 9--Reserved: These bits are always read as 0. The write value should always be 0. * Bit 8--Overflow Interrupt Enable 1A (OVE1A): Enables or disables interrupt requests by OVF1A in TSR1A when OVF1A is set to 1. Bit 8: OVE1A 0 1 Description OVI1A interrupt requested by OVF1A is disabled OVI1A interrupt requested by OVF1A is enabled (Initial value) * Bit 7--Input Capture/Compare-Match Interrupt Enable 1H (IME1H): Enables or disables interrupt requests by IMF1H in TSR1A when IMF1H is set to 1. Bit 7: IME1H 0 1 Description IMI1H interrupt requested by IMF1H is disabled IMI1H interrupt requested by IMF1H is enabled (Initial value) * Bit 6--Input Capture/Compare-Match Interrupt Enable 1G (IME1G): Enables or disables interrupt requests by IMF1G in TSR1A when IMF1G is set to 1. Bit 6: IME1G 0 1 Description IMI1G interrupt requested by IMF1G is disabled IMI1G interrupt requested by IMF1G is enabled (Initial value) * Bit 5--Input Capture/Compare-Match Interrupt Enable 1F (IME1F): Enables or disables interrupt requests by IMF1F in TSR1A when IMF1F is set to 1. Bit 5: IME1F 0 1 Description IMI1F interrupt requested by IMF1F is disabled IMI1F interrupt requested by IMF1F is enabled (Initial value) * Bit 4--Input Capture/Compare-Match Interrupt Enable 1E (IME1E): Enables or disables interrupt requests by IMF1E in TSR1A when IMF1E is set to 1. Bit 4: IME1E 0 1 Description IMI1E interrupt requested by IMF1E is disabled IMI1E interrupt requested by IMF1E is enabled (Initial value) Rev.2.0, 07/03, page 281 of 960 * Bit 3--Input Capture/Compare-Match Interrupt Enable 1D (IME1D): Enables or disables interrupt requests by IMF1D in TSR1A when IMF1D is set to 1. Bit 3: IME1D 0 1 Description IMI1D interrupt requested by IMF1D is disabled IMI1D interrupt requested by IMF1D is enabled (Initial value) * Bit 2--Input Capture/Compare-Match Interrupt Enable 1C (IME1C): Enables or disables interrupt requests by IMF1C in TSR1A when IMF1C is set to 1. Bit 2: IME1C 0 1 Description IMI1C interrupt requested by IMF1C is disabled IMI1C interrupt requested by IMF1C is enabled (Initial value) * Bit 1--Input Capture/Compare-Match Interrupt Enable 1B (IME1B): Enables or disables interrupt requests by IMF1B in TSR1A when IMF1B is set to 1. Bit 1: IME1B 0 1 Description IMI1B interrupt requested by IMF1B is disabled IMI1B interrupt requested by IMF1B is enabled (Initial value) * Bit 0--Input Capture/Compare-Match Interrupt Enable 1A (IME1A): Enables or disables interrupt requests by IMF1A in TSR1A when IMF1A is set to 1. Bit 0: IME1A 0 1 Description IMI1A interrupt requested by IMF1A is disabled IMI1A interrupt requested by IMF1A is enabled (Initial value) Rev.2.0, 07/03, page 282 of 960 TIER1B: TIER1B controls enabling/disabling of channel 1 compare-match and overflow interrupt requests. Bit: 15 -- Initial value: R/W: Bit: 0 R 7 -- Initial value: R/W: 0 R 14 -- 0 R 6 -- 0 R 13 -- 0 R 5 -- 0 R 12 -- 0 R 4 -- 0 R 11 -- 0 R 3 -- 0 R 10 -- 0 R 2 -- 0 R 9 -- 0 R 1 -- 0 R 8 OVE1B 0 R/W 0 CME1 0 R/W * Bits 15 to 9--Reserved: These bits are always read as 0. The write value should always be 0. * Bit 8--Overflow Interrupt Enable 1B (OVE1B): Enables or disables interrupt requests by OVF1B in TSR1B when OVF1B is set to 1. Bit 8: OVE1B 0 1 Description OVI1B interrupt requested by OVF1B is disabled OVI1B interrupt requested by OVF1B is enabled (Initial value) * Bits 7 to 1--Reserved: These bits are always read as 0. The write value should always be 0. * Bit 0--Compare-Match Interrupt Enable 1 (CME1): Enables or disables interrupt requests by CMF1 in TSR1B when CMF1 is set to 1. Bit 0: CME1 0 1 Description CMI1 interrupt requested by CMF1 is disabled CMI1 interrupt requested by CMF1 is enabled (Initial value) Rev.2.0, 07/03, page 283 of 960 Timer Interrupt Enable Registers 2A and 2B (TIER2A, TIER2B) TIER2A: TIER2A controls enabling/disabling of channel 2 input capture, compare-match, and overflow interrupt requests. Bit: 15 -- Initial value: R/W: Bit: 0 R 7 IME2H Initial value: R/W: 0 R/W 14 -- 0 R 6 IME2G 0 R/W 13 -- 0 R 5 IME2F 0 R/W 12 -- 0 R 4 IME2E 0 R/W 11 -- 0 R 3 IME2D 0 R/W 10 -- 0 R 2 IME2C 0 R/W 9 -- 0 R 1 IME2B 0 R/W 8 OVE2A 0 R/W 0 IME2A 0 R/W * Bits 15 to 9--Reserved: These bits are always read as 0. The write value should always be 0. * Bit 8--Overflow Interrupt Enable 2A (OVE2A): Enables or disables interrupt requests by OVF2A in TSR2A when OVF2A is set to 1. Bit 8: OVE2A 0 1 Description OVI2A interrupt requested by OVF2A is disabled OVI2A interrupt requested by OVF2A is enabled (Initial value) * Bit 7--Input Capture/Compare-Match Interrupt Enable 2H (IME2H): Enables or disables interrupt requests by IMF2H in TSR2A when IMF2H is set to 1. Bit 7: IME2H 0 1 Description IMI2H interrupt requested by IMF2H is disabled IMI2H interrupt requested by IMF2H is enabled (Initial value) * Bit 6--Input Capture/Compare-Match Interrupt Enable 2G (IME2G): Enables or disables interrupt requests by IMF2G in TSR2A when IMF2G is set to 1. Bit 6: IME2G 0 1 Description IMI2G interrupt requested by IMF2G is disabled IMI2G interrupt requested by IMF2G is enabled (Initial value) Rev.2.0, 07/03, page 284 of 960 * Bit 5--Input Capture/Compare-Match Interrupt Enable 2F (IME2F): Enables or disables interrupt requests by IMF2F in TSR2A when IMF2F is set to 1. Bit 5: IME2F 0 1 Description IMI2F interrupt requested by IMF2F is disabled IMI2F interrupt requested by IMF2F is enabled (Initial value) * Bit 4--Input Capture/Compare-Match Interrupt Enable 2E (IME2E): Enables or disables interrupt requests by IMF2E in TSR2A when IMF2E is set to 1. Bit 4: IME2E 0 1 Description IMI2E interrupt requested by IMF2E is disabled IMI2E interrupt requested by IMF2E is enabled (Initial value) * Bit 3--Input Capture/Compare-Match Interrupt Enable 2D (IME2D): Enables or disables interrupt requests by IMF2D in TSR2A when IMF2D is set to 1. Bit 3: IME2D 0 1 Description IMI2D interrupt requested by IMF2D is disabled IMI2D interrupt requested by IMF2D is enabled (Initial value) * Bit 2--Input Capture/Compare-Match Interrupt Enable 2C (IME2C): Enables or disables interrupt requests by IMF2C in TSR2A when IMF2C is set to 1. Bit 2: IME2C 0 1 Description IMI2C interrupt requested by IMF2C is disabled IMI2C interrupt requested by IMF2C is enabled (Initial value) * Bit 1--Input Capture/Compare-Match Interrupt Enable 2B (IME2B): Enables or disables interrupt requests by IMF2B in TSR2A when IMF2B is set to 1. Bit 1: IME2B 0 1 Description IMI2B interrupt requested by IMF2B is disabled IMI2B interrupt requested by IMF2B is enabled (Initial value) Rev.2.0, 07/03, page 285 of 960 * Bit 0--Input Capture/Compare-Match Interrupt Enable 2A (IME2A): Enables or disables interrupt requests by IMF2A in TSR2A when IMF2A is set to 1. Bit 0: IME2A 0 1 Description IMI2A interrupt requested by IMF2A is disabled IMI2A interrupt requested by IMF2A is enabled (Initial value) TIER2B: TIER2B controls enabling/disabling of channel 2 compare-match and overflow interrupt requests. Bit: 15 -- Initial value: R/W: Bit: 0 R 7 CME2H Initial value: R/W: 0 R/W 14 -- 0 R 6 CME2G 0 R/W 13 -- 0 R 5 CME2F 0 R/W 12 -- 0 R 4 CME2E 0 R/W 11 -- 0 R 3 CME2D 0 R/W 10 -- 0 R 2 CME2C 0 R/W 9 -- 0 R 1 CME2B 0 R/W 8 OVE2B 0 R/W 0 CME2A 0 R/W * Bits 15 to 9--Reserved: These bits are always read as 0. The write value should always be 0. * Bit 8--Overflow Interrupt Enable 2B (OVE2B): Enables or disables interrupt requests by OVF2B in TSR2B when OVF2B is set to 1. Bit 8: OVE2B 0 1 Description OVI2B interrupt requested by OVF2B is disabled OVI2B interrupt requested by OVF2B is enabled (Initial value) * Bit 7--Compare-Match Interrupt Enable 2H (CME2H): Enables or disables interrupt requests by CMF2F in TSR2B when CMF2H is set to 1. Bit 7: CME2H 0 1 Description CMI2H interrupt requested by CMF2H is disabled CMI2H interrupt requested by CMF2H is enabled (Initial value) Rev.2.0, 07/03, page 286 of 960 * Bit 6--Compare-Match Interrupt Enable 2G (CME2G): Enables or disables interrupt requests by CMF2G in TSR2B when CMF2G is set to 1. Bit 6: CME2G 0 1 Description CMI2G interrupt requested by CMF2G is disabled CMI2G interrupt requested by CMF2G is enabled (Initial value) * Bit 5--Compare-Match Interrupt Enable 2F (CME2F): Enables or disables interrupt requests by CMF2F in TSR2B when CMF2F is set to 1. Bit 5: CME2F 0 1 Description CMI2F interrupt requested by CMF2F is disabled CMI2F interrupt requested by CMF2F is enabled (Initial value) * Bit 4--Compare-Match Interrupt Enable 2E (CME2E): Enables or disables interrupt requests by CMF2E in TSR2B when CMF2E is set to 1. Bit 4: CME2E 0 1 Description CMI2E interrupt requested by CMF2E is disabled CMI2E interrupt requested by CMF2E is enabled (Initial value) * Bit 3--Compare-Match Interrupt Enable 2D (CME2D): Enables or disables interrupt requests by CMF2D in TSR2B when CMF2D is set to 1. Bit 3: CME2D 0 1 Description CMI2D interrupt requested by CMF2D is disabled CMI2D interrupt requested by CMF2D is enabled (Initial value) * Bit 2--Compare-Match Interrupt Enable 2C (CME2C): Enables or disables interrupt requests by CMF2C in TSR2B when CMF2C is set to 1. Bit 2: CME2C 0 1 Description CMI2C interrupt requested by CMF2C is disabled CMI2C interrupt requested by CMF2C is enabled (Initial value) Rev.2.0, 07/03, page 287 of 960 * Bit 1--Compare-Match Interrupt Enable 2B (CME2BB): Enables or disables interrupt requests by CMF2B in TSR2B when CMF2B is set to 1. Bit 1: CME2B 0 1 Description CMI2B interrupt requested by CMF2B is disabled CMI2B interrupt requested by CMF2B is enabled (Initial value) * Bit 0--Compare-Match Interrupt Enable 2A (CME2A): Enables or disables interrupt requests by CMF2A in TSR2B when CMF2A is set to 1. Bit 0: CME2A 0 1 Description CMI2A interrupt requested by CMF2A is disabled CMI2A interrupt requested by CMF2A is enabled (Initial value) Timer Interrupt Enable Register 3 (TIER3) TIER3 controls enabling/disabling of channel 3 to 5 input capture, compare-match, and overflow interrupt requests. Bit: 15 -- Initial value: R/W: Bit: 0 R 7 IME4C Initial value: R/W: 0 R/W 14 OVE5 0 R/W 6 IME4B 0 R/W 13 IME5D 0 R/W 5 IME4A 0 R/W 12 IME5C 0 R/W 4 OVE3 0 R/W 11 IME5B 0 R/W 3 IME3D 0 R/W 10 IME5A 0 R/W 2 IME3C 0 R/W 9 OVE4 0 R/W 1 IME3B 0 R/W 8 IME4D 0 R/W 0 IME3A 0 R/W * Bit 15--Reserved: This bit is always read as 0. The write value should always be 0. * Bit 14--Overflow Interrupt Enable 5 (OVE5): Enables or disables interrupt requests by OVF5 in TSR3 when OVF5 is set to 1. Bit 14: OVE5 0 1 Description OVI5 interrupt requested by OVF5 is disabled OVI5 interrupt requested by OVF5 is enabled (Initial value) Rev.2.0, 07/03, page 288 of 960 * Bit 13--Input Capture/Compare-Match Interrupt Enable 5D (IME5D): Enables or disables interrupt requests by IMF5D in TSR3 when IMF5D is set to 1. Bit 13: IME5D 0 1 Description IMI5D interrupt requested by IMF5D is disabled IMI5D interrupt requested by IMF5D is enabled (Initial value) * Bit 12--Input Capture/Compare-Match Interrupt Enable 5C (IME5C): Enables or disables interrupt requests by IMF5C in TSR3 when IMF5C is set to 1. Bit 12: IME5C 0 1 Description IMI5C interrupt requested by IMF5C is disabled IMI5C interrupt requested by IMF5C is enabled (Initial value) * Bit 11--Input Capture/Compare-Match Interrupt Enable 5B (IME5B): Enables or disables interrupt requests by IMF5B in TSR3 when IMF5B is set to 1. Bit 11: IME5B 0 1 Description IMI5B interrupt requested by IMF5B is disabled IMI5B interrupt requested by IMF5B is enabled (Initial value) * Bit 10--Input Capture/Compare-Match Interrupt Enable 5A (IME5A): Enables or disables interrupt requests by IMF5A in TSR3 when IMF5A is set to 1. Bit 10: IME5A 0 1 Description IMI5A interrupt requested by IMF5A is disabled IMI5A interrupt requested by IMF5A is enabled (Initial value) * Bit 9--Overflow Interrupt Enable 4 (OVE4): Enables or disables interrupt requests by OVF4 in TSR3 when OVF4 is set to 1. Bit 9: OVE4 0 1 Description OVI4 interrupt requested by OVF4 is disabled OVI4 interrupt requested by OVF4 is enabled (Initial value) Rev.2.0, 07/03, page 289 of 960 * Bit 8--Input Capture/Compare-Match Interrupt Enable 4D (IME4D): Enables or disables interrupt requests by IMF4D in TSR3 when IMF4D is set to 1. Bit 8: IME4D 0 1 Description IMI4D interrupt requested by IMF4D is disabled IMI4D interrupt requested by IMF4D is enabled (Initial value) * Bit 7--Input Capture/Compare-Match Interrupt Enable 4C (IME4C): Enables or disables interrupt requests by IMF4C in TSR3 when IMF4C is set to 1. Bit 7: IME4C 0 1 Description IMI4C interrupt requested by IMF4C is disabled IMI4C interrupt requested by IMF4C is enabled (Initial value) * Bit 6--Input Capture/Compare-Match Interrupt Enable 4B (IME4B): Enables or disables interrupt requests by IMF4B in TSR3 when IMF4B is set to 1. Bit 6: IME4B 0 1 Description IMI4B interrupt requested by IMF4B is disabled IMI4B interrupt requested by IMF4B is enabled (Initial value) * Bit 5--Input Capture/Compare-Match Interrupt Enable 4A (IME4A): Enables or disables interrupt requests by IMF4A in TSR3 when IMF4A is set to 1. Bit 5: IME4A 0 1 Description IMI4A interrupt requested by IMF4A is disabled IMI4A interrupt requested by IMF4A is enabled (Initial value) * Bit 4--Overflow Interrupt Enable 3 (OVE3): Enables or disables interrupt requests by OVF3 in TSR3 when OVF3 is set to 1. Bit 4: OVE3 0 1 Description OVI3 interrupt requested by OVF3 is disabled OVI3 interrupt requested by OVF3 is enabled (Initial value) Rev.2.0, 07/03, page 290 of 960 * Bit 3--Input Capture/Compare-Match Interrupt Enable 3D (IME3D): Enables or disables interrupt requests by IMF3D in TSR3 when IMF3D is set to 1. Bit 3: IME3D 0 1 Description IMI3D interrupt requested by IMF3D is disabled IMI3D interrupt requested by IMF3D is enabled (Initial value) * Bit 2--Input Capture/Compare-Match Interrupt Enable 3C (IME3C): Enables or disables interrupt requests by IMF3C in TSR3 when IMF3C is set to 1. Bit 2: IME3C 0 1 Description IMI3C interrupt requested by IMF3C is disabled IMI3C interrupt requested by IMF3C is enabled (Initial value) * Bit 1--Input Capture/Compare-Match Interrupt Enable 3B (IME3B): Enables or disables interrupt requests by IMF3B in TSR3 when IMF3B is set to 1. Bit 1: IME3B 0 1 Description IMI3B interrupt requested by IMF3B is disabled IMI3B interrupt requested by IMF3B is enabled (Initial value) * Bit 0--Input Capture/Compare-Match Interrupt Enable 3A (IME3A): Enables or disables interrupt requests by IMF3A in TSR3 when IMF3A is set to 1. Bit 0: IME3A 0 1 Description IMI3A interrupt requested by IMF3A is disabled IMI3A interrupt requested by IMF3A is enabled (Initial value) Rev.2.0, 07/03, page 291 of 960 Timer Interrupt Enable Registers 6 and 7 (TIER6, TIER7) TIER6 and TIER7 control enabling/disabling of channel 6 and 7 cycle register compare interrupt requests. Bit: 15 -- Initial value: R/W: Bit: 0 R 7 -- Initial value: R/W: x = 6 or 7 0 R 14 -- 0 R 6 -- 0 R 13 -- 0 R 5 -- 0 R 12 -- 0 R 4 -- 0 R 11 -- 0 R 3 10 -- 0 R 2 9 -- 0 R 1 8 -- 0 R 0 CMExA 0 R/W CMExD CMExC CMExB 0 R/W 0 R/W 0 R/W * Bits 15 to 4--Reserved: These bits are always read as 0. The write value should always be 0. * Bit 3--Cycle Register Compare-Match Interrupt Enable 6D/7D (CME6D/CME7D): Enables or disables interrupt requests by CMFxD in TSR6 or TSR7 when CMFxD is set to 1. Setting the DMAC while interrupt requests are enabled allows the DMAC to be activated by an interrupt request. Bit 3: CMExD 0 1 x = 6 or 7 Description CMIxD interrupt requested by CMFxD is disabled CMIxD interrupt requested by CMFxD is enabled (Initial value) * Bit 2--Cycle Register Compare-Match Interrupt Enable 6C/7C (CME6C/CME7C): Enables or disables interrupt requests by CMFxC in TSR6 or TSR7 when CMFxC is set to 1. Setting the DMAC while interrupt requests are enabled allows the DMAC to be activated by an interrupt request. Bit 2: CMExC 0 1 x = 6 or 7 Description CMIxC interrupt requested by CMFxC is disabled CMIxC interrupt requested by CMFxC is enabled (Initial value) Rev.2.0, 07/03, page 292 of 960 * Bit 1--Cycle Register Compare-Match Interrupt Enable 6B/7B (CME6B/CME7B): Enables or disables interrupt requests by CMFxB in TSR6 or TSR7 when CMFxB is set to 1. Setting the DMAC while interrupt requests are enabled allows the DMAC to be activated by an interrupt request. Bit 1: CMExB 0 1 x = 6 or 7 Description CMIxB interrupt requested by CMFxB is disabled CMIxB interrupt requested by CMFxB is enabled (Initial value) * Bit 0--Cycle Register Compare-Match Interrupt Enable 6A/7A (CME6A/CME7A): Enables or disables interrupt requests by CMFxA in TSR6 or TSR7 when CMFxA is set to 1. Setting the DMAC while interrupt requests are enabled allows the DMAC to be activated by an interrupt request. Bit 0: CMExA 0 1 x = 6 or 7 Description CMIxA interrupt requested by CMFxA is disabled CMIxA interrupt requested by CMFxA is enabled (Initial value) Timer Interrupt Enable Register 8 (TIER8) TIER8 controls enabling/disabling of channel 8 one-shot pulse interrupt requests. Bit: 15 OSE8P Initial value: R/W: Bit: 0 R/W 7 14 13 12 11 OSE8L 0 R/W 3 OSE8D 0 R/W 10 OSE8K 0 R/W 2 OSE8C 0 R/W 9 OSE8J 0 R/W 1 OSE8B 0 R/W 8 OSE8I 0 R/W 0 OSE8A 0 R/W OSE8O OSE8N OSE8M 0 R/W 6 0 R/W 5 OSE8F 0 R/W 0 R/W 4 OSE8E 0 R/W OSE8H OSE8G Initial value: R/W: 0 R/W 0 R/W Rev.2.0, 07/03, page 293 of 960 * Bit 15--One-Shot Pulse Interrupt Enable 8P (OSE8P): Enables or disables interrupt requests by OSF8P in TSR8 when OSF8P is set to 1. Bit 15: OSE8P 0 1 Description OSI8P interrupt requested by OSF8P is disabled OSI8P interrupt requested by OSF8P is enabled (Initial value) * Bit 14--One-Shot Pulse Interrupt Enable 8O (OSE8O): Enables or disables interrupt requests by OSF8O in TSR8 when OSF8O is set to 1. Bit 14: OSE8O 0 1 Description OSI8O interrupt requested by OSF8O is disabled OSI8O interrupt requested by OSF8O is enabled (Initial value) * Bit 13--One-Shot Pulse Interrupt Enable 8N (OSE8N): Enables or disables interrupt requests by OSF8N in TSR8 when OSF8N is set to 1. Bit 13: OSE8N 0 1 Description OSI8N interrupt requested by OSF8N is disabled OSI8N interrupt requested by OSF8N is enabled (Initial value) * Bit 12--One-Shot Pulse Interrupt Enable 8M (OSE8M): Enables or disables interrupt requests by OSF8M in TSR8 when OSF8M is set to 1. Bit 12: OSE8M 0 1 Description OSI8M interrupt requested by OSF8M is disabled OSI8M interrupt requested by OSF8M is enabled (Initial value) * Bit 11--One-Shot Pulse Interrupt Enable 8L (OSE8L): Enables or disables interrupt requests by OSF8L in TSR8 when OSF8L is set to 1. Bit 11: OSE8L 0 1 Description OSI8L interrupt requested by OSF8L is disabled OSI8L interrupt requested by OSF8L is enabled (Initial value) Rev.2.0, 07/03, page 294 of 960 * Bit 10--One-Shot Pulse Interrupt Enable 8K (OSE8K): Enables or disables interrupt requests by OSF8K in TSR8 when OSF8K is set to 1. Bit 10: OSE8K 0 1 Description OSI8K interrupt requested by OSF8K is disabled OSI8K interrupt requested by OSF8K is enabled (Initial value) * Bit 9--One-Shot Pulse Interrupt Enable 8J (OSE8J): Enables or disables interrupt requests by OSF8J in TSR8 when OSF8J is set to 1. Bit 9: OSE8J 0 1 Description OSI8J interrupt requested by OSF8J is disabled OSI8J interrupt requested by OSF8J is enabled (Initial value) * Bit 8--One-Shot Pulse Interrupt Enable 8I (OSE8I): Enables or disables interrupt requests by OSF8I in TSR8 when OSF8I is set to 1. Bit 8: OSE8I 0 1 Description OSI8I interrupt requested by OSF8I is disabled OSI8I interrupt requested by OSF8I is enabled (Initial value) * Bit 7--One-Shot Pulse Interrupt Enable 8H (OSE8H): Enables or disables interrupt requests by OSF8H in TSR8 when OSF8H is set to 1. Bit 7: OSE8H 0 1 Description OSI8H interrupt requested by OSF8H is disabled OSI8H interrupt requested by OSF8H is enabled (Initial value) * Bit 6--One-Shot Pulse Interrupt Enable 8G (OSE8G): Enables or disables interrupt requests by OSF8G in TSR8 when OSF8G is set to 1. Bit 6: OSE8G 0 1 Description OSI8G interrupt requested by OSF8G is disabled OSI8G interrupt requested by OSF8G is enabled (Initial value) Rev.2.0, 07/03, page 295 of 960 * Bit 5--One-Shot Pulse Interrupt Enable 8F (OSE8F): Enables or disables interrupt requests by OSF8F in TSR8 when OSF8F is set to 1. Bit 5: OSE8F 0 1 Description OSI8F interrupt requested by OSF8F is disabled OSI8F interrupt requested by OSF8F is enabled (Initial value) * Bit 4--One-Shot Pulse Interrupt Enable 8E (OSE8E): Enables or disables interrupt requests by OSF8E in TSR8 when OSF8E is set to 1. Bit 4: OSE8E 0 1 Description OSI8E interrupt requested by OSF8E is disabled OSI8E interrupt requested by OSF8E is enabled (Initial value) * Bit 3--One-Shot Pulse Interrupt Enable 8D (OSE8D): Enables or disables interrupt requests by OSF8D in TSR8 when OSF8D is set to 1. Bit 3: OSE8D 0 1 Description OSI8D interrupt requested by OSF8D is disabled OSI8D interrupt requested by OSF8D is enabled (Initial value) * Bit 2--One-Shot Pulse Interrupt Enable 8C (OSE8C): Enables or disables interrupt requests by OSF8C in TSR8 when OSF8C is set to 1. Bit 2: OSE8C 0 1 Description OSI8C interrupt requested by OSF8C is disabled OSI8C interrupt requested by OSF8C is enabled (Initial value) * Bit 1--One-Shot Pulse Interrupt Enable 8B (OSE8B): Enables or disables interrupt requests by OSF8B in TSR8 when OSF8B is set to 1. Bit 1: OSE8B 0 1 Description OSI8B interrupt requested by OSF8B is disabled OSI8B interrupt requested by OSF8B is enabled (Initial value) Rev.2.0, 07/03, page 296 of 960 * Bit 0--One-Shot Pulse Interrupt Enable 8A (OSE8A): Enables or disables interrupt requests by OSF8A in TSR8 when OSF8A is set to 1. Bit 0: OSE8A 0 1 Description OSI8A interrupt requested by OSF8A is disabled OSI8A interrupt requested by OSF8A is enabled (Initial value) Timer Interrupt Enable Register 9 (TIER9) TIER9 controls enabling/disabling of channel 9 event counter compare-match interrupt requests. Bit: 15 -- Initial value: R/W: Bit: 0 R 7 -- Initial value: R/W: 0 R 14 -- 0 R 6 -- 0 R 13 -- 0 R 5 12 -- 0 R 4 11 -- 0 R 3 10 -- 0 R 2 9 -- 0 R 1 8 -- 0 R 0 CME9F CME9E CME9D CME9C CME9B CME9A 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W * Bits 15 to 6--Reserved: These bits are always read as 0. The write value should always be 0. * Bit 5--Compare-Match Interrupt Enable 9F (CME9F): Enables or disables interrupt requests by CMF9F in TSR9 when CMF9F is set to 1. Bit 5: CME9F 0 1 Description CMI9F interrupt requested by CMF9F is disabled CMI9F interrupt requested by CMF9F is enabled (Initial value) * Bit 4--Compare-Match Interrupt Enable 9E (CME9E): Enables or disables interrupt requests by CMF9E in TSR9 when CMF9E is set to 1. Bit 4: CME9E 0 1 Description CMI9E interrupt requested by CMF9E is disabled CMI9E interrupt requested by CMF9E is enabled (Initial value) Rev.2.0, 07/03, page 297 of 960 * Bit 3--Compare-Match Interrupt Enable 9D (CME9D): Enables or disables interrupt requests by CMF9D in TSR9 when CMF9D is set to 1. Bit 3: CME9D 0 1 Description CMI9D interrupt requested by CMF9D is disabled CMI9D interrupt requested by CMF9D is enabled (Initial value) * Bit 2--Compare-Match Interrupt Enable 9C (CME9C): Enables or disables interrupt requests by CMF9C in TSR9 when CMF9C is set to 1. Bit 2: CME9C 0 1 Description CMI9C interrupt requested by CMF9C is disabled CMI9C interrupt requested by CMF9C is enabled (Initial value) * Bit 1--Compare-Match Interrupt Enable 9B (CME9B): Enables or disables interrupt requests by CMF9B in TSR9 when CMF9B is set to 1. Bit 1: CME9B 0 1 Description CMI9B interrupt requested by CMF9B is disabled CMI9B interrupt requested by CMF9B is enabled (Initial value) * Bit 0--Compare-Match Interrupt Enable 9A (CME9A): Enables or disables interrupt requests by CMF9A in TSR9 when CMF9A is set to 1. Bit 0: CME9A 0 1 Description CMI9A interrupt requested by CMF9A is disabled CMI9A interrupt requested by CMF9A is enabled (Initial value) Rev.2.0, 07/03, page 298 of 960 Timer Interrupt Enable Register 11 (TIER11) TIER11 controls enabling/disabling of channel 11 input capture, compare-match, and overflow interrupt requests. Bit: 15 -- Initial value: R/W: Bit: 0 R 7 -- Initial value: R/W: 0 R 14 -- 0 R 6 -- 0 R 13 -- 0 R 5 -- 0 R 12 -- 0 R 4 -- 0 R 11 -- 0 R 3 -- 0 R 10 -- 0 R 2 -- 0 R 9 -- 0 R 1 8 OVE11 0 R/W 0 IME11B IME11A 0 R/W 0 R/W * Bits 15 to 9--Reserved: These bits are always read as 0. The write value should always be 0. * Bit 8--Overflow Interrupt Enable 11 (OVE11): Enables or disables interrupt requests by OVF11 in TSR11 when OVF11 is set to 1. Bit 8: OVE11 0 1 Description OVI11 interrupt requested by OVF11 is disabled OVI11 interrupt requested by OVF11 is enabled (Initial value) * Bits 7 to 2--Reserved: These bits are always read as 0. The write value should always be 0. * Bit 1--Input Capture/Compare-Match Interrupt Enable 11B (IME11B): Enables or disables interrupt requests by IMF11B in TSR11 when IMF11B is set to 1. Bit 1: IME11B 0 1 Description IMI11B interrupt requested by IMF11B is disabled IMI11B interrupt requested by IMF11B is enabled (Initial value) * Bit 0--Input Capture/Compare-Match Interrupt Enable 11A (IME11A): Enables or disables interrupt requests by IMF11A in TSR11 when IMF11A is set to 1. Bit 0: IME11A 0 1 Description IMI11A interrupt requested by IMF11A is disabled IMI11A interrupt requested by IMF11A is enabled (Initial value) Rev.2.0, 07/03, page 299 of 960 11.2.7 Interval Interrupt Request Registers (ITVRR) The interval interrupt request registers (ITVRR) are 8-bit registers. The ATU-II has three ITVRR registers in channel 0. Channel 0 Abbreviation ITVRR1 ITVRR2A ITVRR2B Function TCNT0 bit 6 to 9 interval interrupt generation and A/D2 converter activation TCNT0 bit 10 to 13 interval interrupt generation and A/D0 converter activation TCNT0 bit 10 to 13 interval interrupt generation and A/D1 converter activation Interval Interrupt Request Register 1 (ITVRR1) Bit: 7 ITVA9 Initial value: R/W: 0 R/W 6 ITVA8 0 R/W 5 ITVA7 0 R/W 4 ITVA6 0 R/W 3 ITVE9 0 R/W 2 ITVE8 0 R/W 1 ITVE7 0 R/W 0 ITVE6 0 R/W ITVRR1 is an 8-bit readable/writable register that detects the rise of bits corresponding to the channel 0 free-running counter (TCNT0) and controls cyclic interrupt output and A/D2 converter activation. ITVRR1 is initialized to H'00 by a power-on reset, and in hardware standby mode and software standby mode. * Bit 7--A/D2 Converter Interval Activation Bit 9 (ITVA9): A/D2 converter activation setting bit corresponding to bit 9 in TCNT0. The rise of bit 9 in TCNT0 is ANDed with ITVA9, and the result is output to the A/D2 converter as an activation signal. Bit 7: ITVA9 0 1 Description A/D2 converter activation by rise of TCNT0 bit 9 is disabled A/D2 converter activation by rise of TCNT0 bit 9 is enabled (Initial value) Rev.2.0, 07/03, page 300 of 960 * Bit 6--A/D2 Converter Interval Activation Bit 8 (ITVA8): A/D2 converter activation setting bit corresponding to bit 8 in TCNT0. The rise of bit 8 in TCNT0 is ANDed with ITVA8, and the result is output to the A/D2 converter as an activation signal. Bit 6: ITVA8 0 1 Description A/D2 converter activation by rise of TCNT0 bit 8 is disabled A/D2 converter activation by rise of TCNT0 bit 8 is enabled (Initial value) * Bit 5--A/D2 Converter Interval Activation Bit 7 (ITVA7): A/D2 converter activation setting bit corresponding to bit 7 in TCNT0. The rise of bit 7 in TCNT0 is ANDed with ITVA7, and the result is output to the A/D2 converter as an activation signal. Bit 5: ITVA7 0 1 Description A/D2 converter activation by rise of TCNT0 bit 7 is disabled A/D2 converter activation by rise of TCNT0 bit 7 is enabled (Initial value) * Bit 4--A/D2 Converter Interval Activation Bit 6 (ITVA6): A/D2 converter activation setting bit corresponding to bit 6 in TCNT0. The rise of bit 6 in TCNT0 is ANDed with ITVA6, and the result is output to the A/D2 converter as an activation signal. Bit 4: ITVA6 0 1 Description A/D2 converter activation by rise of TCNT0 bit 6 is disabled A/D2 converter activation by rise of TCNT0 bit 6 is enabled (Initial value) * Bit 3--Interval Interrupt Bit 9 (ITVE9): INTC interval interrupt setting bit corresponding to bit 9 in TCNT0. The rise of bit 9 in TCNT0 is ANDed with ITVE9, the result is stored in IIF1 in TSR0, and an interrupt request is sent to the CPU. Bit 3: ITVE9 0 1 Description Interrupt request (ITV1) by rise of TCNT0 bit 9 is disabled Interrupt request (ITV1) by rise of TCNT0 bit 9 is enabled (Initial value) * Bit 2--Interval Interrupt Bit 8 (ITVE8): INTC interval interrupt setting bit corresponding to bit 8 in TCNT0. The rise of bit 8 in TCNT0 is ANDed with ITVE8, the result is stored in IIF1 in TSR0, and an interrupt request is sent to the CPU. Bit 2: ITVE8 0 1 Description Interrupt request (ITV1) by rise of TCNT0 bit 8 is disabled Interrupt request (ITV1) by rise of TCNT0 bit 8 is enabled (Initial value) Rev.2.0, 07/03, page 301 of 960 * Bit 1--Interval Interrupt Bit 7 (ITVE7): INTC interval interrupt setting bit corresponding to bit 7 in TCNT0. The rise of bit 7 in TCNT0 is ANDed with ITVE7, the result is stored in IIF1 in TSR0, and an interrupt request is sent to the CPU. Bit 1: ITVE7 0 1 Description Interrupt request (ITV1) by rise of TCNT0 bit 7 is disabled Interrupt request (ITV1) by rise of TCNT0 bit 7 is enabled (Initial value) * Bit 0--Interval Interrupt Bit 6 (ITVE6): INTC interval interrupt setting bit corresponding to bit 6 in TCNT0. The rise of bit 6 in TCNT0 is ANDed with ITVE6, the result is stored in IIF1 in TSR0, and an interrupt request is sent to the CPU. Bit 0: ITVE6 0 1 Description Interrupt request (ITV1) by rise of TCNT0 bit 6 is disabled Interrupt request (ITV1) by rise of TCNT0 bit 6 is enabled (Initial value) Interval Interrupt Request Registers 2A and 2B (ITVRR2A, ITVRR2B) Bit: 7 6 5 4 3 2 1 0 ITVA13x ITVA12x ITVA11x ITVA10x ITVE13x ITVE12x ITVE11x ITVE10x Initial value: R/W: x = A or B 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W * Bit 7--A/D0 / A/D1 Converter Interval Activation Bit 13A/13B (ITVA13A/ITVA13B): A/D0 or A/D1 (ITVRR2A: A/D0; ITVRR2B: A/D1) converter activation setting bit corresponding to bit 13 in TCNT0. The rise of bit 13 in TCNT0 is ANDed with ITVA13x, and the result is output to the A/D0 or A/D1 converter as an activation signal. Bit 7: ITVA13x 0 1 x = A or B Description A/D0 or A/D1 converter activation by rise of TCNT0 bit 13 is disabled (Initial value) A/D0 or A/D1 converter activation by rise of TCNT0 bit 13 is enabled Rev.2.0, 07/03, page 302 of 960 * Bit 6--A/D0 / A/D1 Converter Interval Activation Bit 12A/12B (ITVA12A/ITVA12B): A/D0 or A/D1 (ITVRR2A: A/D0; ITVRR2B: A/D1) converter activation setting bit corresponding to bit 12 in TCNT0. The rise of bit 12 in TCNT0 is ANDed with ITVA12x, and the result is output to the A/D0 or A/D1 converter as an activation signal. Bit 6: ITVA12x 0 1 x = A or B Description A/D0 or A/D1 converter activation by rise of TCNT0 bit 12 is disabled (Initial value) A/D0 or A/D1 converter activation by rise of TCNT0 bit 12 is enabled * Bit 5--A/D0 / A/D1 Converter Interval Activation Bit 11A/11B (ITVA11A/ITVA11B): A/D0 or A/D1 (ITVRR2A: A/D0; ITVRR2B: A/D1) converter activation setting bit corresponding to bit 11 in TCNT0. The rise of bit 11 in TCNT0 is ANDed with ITVA11x, and the result is output to the A/D0 or A/D1 converter as an activation signal. Bit 5: ITVA11x 0 1 x = A or B Description A/D0 or A/D1 converter activation by rise of TCNT0 bit 11 is disabled (Initial value) A/D0 or A/D1 converter activation by rise of TCNT0 bit 11 is enabled * Bit 4--A/D0 / A/D1 Converter Interval Activation Bit 10A/10B (ITVA10A/ITVA10B): A/D0 or A/D1 (ITVRR2A: A/D0; ITVRR2B: A/D1) converter activation setting bit corresponding to bit 10 in TCNT0. The rise of bit 10 in TCNT0 is ANDed with ITVA10x, and the result is output to the A/D0 or A/D1 converter as an activation signal. Bit 4: ITVA10x 0 1 x = A or B Description A/D0 or A/D1 converter activation by rise of TCNT0 bit 10 is disabled (Initial value) A/D0 or A/D1 converter activation by rise of TCNT0 bit 10 is enabled Rev.2.0, 07/03, page 303 of 960 * Bit 3--Interval Interrupt Bit 13A/13B (ITVE13A/ITVE13B): INTC interval interrupt setting bit corresponding to bit 13 in TCNT0. The rise of bit 13 in TCNT0 is ANDed with ITVE13x, the result is stored in IIF2x in TSR0, and an interrupt request is sent to the CPU. Bit 3: ITVE13x 0 1 x = A or B Description Interrupt request (ITV2x) by rise of TCNT0 bit 13 is disabled Interrupt request (ITV2x) by rise of TCNT0 bit 13 is enabled (Initial value) * Bit 2--Interval Interrupt Bit 12A/12B (ITVE12A/ITVE12B): INTC interval interrupt setting bit corresponding to bit 12 in TCNT0. The rise of bit 12 in TCNT0 is ANDed with ITVE12x, the result is stored in IIF2x in TSR0, and an interrupt request is sent to the CPU. Bit 2: ITVE12x 0 1 x = A or B Description Interrupt request (ITV2x) by rise of TCNT0 bit 12 is disabled Interrupt request (ITV2x) by rise of TCNT0 bit 12 is enabled (Initial value) * Bit 1--Interval Interrupt Bit 11A/11B (ITVE11A/ITVE11B): INTC interval interrupt setting bit corresponding to bit 11 in TCNT0. The rise of bit 11 in TCNT0 is ANDed with ITVE11x, the result is stored in IIF2x in TSR0, and an interrupt request is sent to the CPU. Bit 1: ITVE11x 0 1 x = A or B Description Interrupt request (ITV2x) by rise of TCNT0 bit 11 is disabled Interrupt request (ITV2x) by rise of TCNT0 bit 11 is enabled (Initial value) * Bit 0--Interval Interrupt Bit 10 (ITVE10): INTC interval interrupt setting bit corresponding to bit 10 in TCNT0. The rise of bit 10 in TCNT0 is ANDed with ITVE10x, the result is stored in IIF2x in TSR0, and an interrupt request is sent to the CPU. Bit 0: ITVE10x 0 1 x = A or B Description Interrupt request (ITV2x) by rise of TCNT0 bit 10 is disabled Interrupt request (ITV2x) by rise of TCNT0 bit 10 is enabled (Initial value) For details, see section 11.3.7, Interval Timer Operation. Rev.2.0, 07/03, page 304 of 960 11.2.8 Trigger Mode Register (TRGMDR) The trigger mode register (TRGMDR) is an 8-bit register. The ATU-II has one TRGMDR register. Bit: 7 TRGMD Initial value: R/W: 0 R/W 6 -- 0 R 5 -- 0 R 4 -- 0 R 3 -- 0 R 2 -- 0 R 1 -- 0 R 0 -- 0 R TRGMDR is an 8-bit readable/writable register that selects whether a channel 1 compare-match is used as a channel 8 one-shot pulse start trigger or as a one-shot pulse terminate trigger when channel 1 and channel 8 are used in combination. TRGMDR is initialized to H'00 by a power-on reset, and in hardware standby mode and software standby mode. * Bit 7--Trigger Mode Selection Register (TRGMD): Selects the channel 8 one-shot pulse start trigger/one-shot pulse terminate trigger setting. Bit 7: TRGMD 0 1 Description One-shot pulse start trigger (TCNT1B = OCR1) One-shot pulse terminate trigger (TCNT1A = GR1A-GR1H) One-shot pulse start trigger (TCNT1A = GR1A-GR1H) One-shot pulse terminate trigger (TCNT1B = OCR1) (Initial value) * Bits 6 to 0--Reserved: These bits are always read as 0. The write value should always be 0. 11.2.9 Timer Mode Register (TMDR) The timer mode register (TMDR) is an 8-bit register. The ATU-II has one TDR register. Bit: 7 -- Initial value: R/W: 0 R 6 -- 0 R 5 -- 0 R 4 -- 0 R 3 -- 0 R 2 1 0 T5PWM T4PWM T3PWM 0 R/W 0 R/W 0 R/W TMDR is an 8-bit readable/writable register that specifies whether channels 3 to 5 are used in input capture/output compare mode or PWM mode. TMDR is initialized to H'00 by a power-on reset, and in hardware standby mode and software standby mode. Rev.2.0, 07/03, page 305 of 960 * Bits 7 to 3--Reserved: These bits are always read as 0. The write value should always be 0. * Bit 2--PWM Mode 5 (T5PWM): Selects whether channel 5 operates in input capture/output compare mode or PWM mode. Bit 2: T5PWM 0 1 Description Channel 5 operates in input capture/output compare mode Channel 5 operates in PWM mode (Initial value) When bit T5PWM is set to 1 to select PWM mode, pins TIO5A to TIO5C become PWM output pins, general register 5D (GR5D) functions as a cycle register, and general registers 5A to 5C (GR5A to GR5C) function as duty registers. Settings in the timer I/O control registers (TIOR5A, TIOR5B) are invalid, and general registers 5A to 5D (GR5A to GR5D) can be written to. Do not use the TIO5D pin as a timer output. * Bit 1--PWM Mode 4 (T4PWM): Selects whether channel 4 operates in input capture/output compare mode or PWM mode. Bit 1: T4PWM 0 1 Description Channel 4 operates in input capture/output compare mode Channel 4 operates in PWM mode (Initial value) When bit T4PWM is set to 1 to select PWM mode, pins TIO4A to TIO4C become PWM output pins, general register 4D (GR4D) functions as a cycle register, and general registers 4A to 4C (GR4A to GR4C) function as duty registers. Settings in the timer I/O control registers (TIOR4A, TIOR4B) are invalid, and general registers 4A to 4D (GR4A to GR4D) can be written to. Do not use the TIO4D pin as a timer output. * Bit 0--PWM Mode 3 (T3PWM): Selects whether channel 3 operates in input capture/output compare mode or PWM mode. Bit 0: T3PWM 0 1 Description Channel 3 operates in input capture/output compare mode Channel 3 operates in PWM mode (Initial value) When bit T3PWM is set to 1 to select PWM mode, pins TIO3A to TIO3C become PWM output pins, general register 3D (GR3D) functions as a cycle register, and general registers 3A to 3C (GR3A to GR3C) function as duty registers. Settings in the timer I/O control registers (TIOR3A, TIOR3B) are invalid, and general registers 3A to 3D (GR3A to GR3D) can be written to. Do not use the TIO3D pin as a timer output. Rev.2.0, 07/03, page 306 of 960 11.2.10 PWM Mode Register (PMDR) The PWM mode register (PMDR) is an 8-bit register. The ATU-II has one PMDR register. Bit: 7 DTSELD 6 DTSELC 5 DTSELB 4 3 2 1 0 DTSELA CNTSELD CNTSELC CNTSELB CNTSELA Initial value: R/W: 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W PMDR is an 8-bit readable/writable register that selects whether channel 6 PWM output is set to on-duty/off-duty, or to non-complementary PWM mode/complementary PWM mode. PMDR is initialized to H'00 by a power-on reset, and in hardware standby mode and software standby mode. * Bit 7--Duty Selection Register D (DTSELD): Selects whether channel 6D TO6D output PWM is set to on-duty or to off-duty. Bit 7: DTSELD 0 1 Description TO6D PWM output is on-duty TO6D PWM output is off-duty (Initial value) * Bit 6--Duty Selection Register C (DTSELC): Selects whether channel 6C TO6C output PWM is set to on-duty or to off-duty. Bit 6: DTSELC 0 1 Description TO6C PWM output is on-duty TO6C PWM output is off-duty (Initial value) * Bit 5--Duty Selection Register B (DTSELB): Selects whether channel 6B TO6B output PWM is set to on-duty or to off-duty. Bit 5: DTSELB 0 1 Description TO6B PWM output is on-duty TO6B PWM output is off-duty (Initial value) Rev.2.0, 07/03, page 307 of 960 * Bit 4--Duty Selection Register A (DTSELA): Selects whether channel 6A TO6A output PWM is set to on-duty or to off-duty. Bit 4: DTSELA 0 1 Description TO6A PWM output is on-duty TO6A PWM output is off-duty (Initial value) * Bit 3--Counter Selection Register D (CNTSELD): Selects whether channel 6D PWM is set to non-complementary PWM mode or to complementary PWM mode. Bit 3: CNTSELD 0 1 Description TCNT6D is set to non-complementary PWM mode TCNT6D is set to complementary PWM mode (Initial value) * Bit 2--Counter Selection Register C (CNTSELC): Selects whether channel 6C PWM is set to non-complementary PWM mode or to complementary PWM mode. Bit 2: CNTSELC 0 1 Description TCNT6C is set to non-complementary PWM mode TCNT6C is set to complementary PWM mode (Initial value) * Bit 1--Counter Selection Register B (CNTSELB): Selects whether channel 6B PWM is set to non-complementary PWM mode or to complementary PWM mode. Bit 1: CNTSELB 0 1 Description TCNT6B is set to non-complementary PWM mode TCNT6B is set to complementary PWM mode (Initial value) * Bit 0--Counter Selection Register A (CNTSELA): Selects whether channel 6A PWM is set to non-complementary PWM mode or to complementary PWM mode. Bit 0: CNTSELA 0 1 Description TCNT6A is set to non-complementary PWM mode TCNT6A is set to complementary PWM mode (Initial value) Rev.2.0, 07/03, page 308 of 960 11.2.11 Down-Count Start Register (DSTR) The down-count start register (DSTR) is a 16-bit register. The ATU-II has one DSTR register in channel 8. Bit: 15 DST8P Initial value: R/W: Bit: 0 R/W* 7 DST8H Initial value: R/W: 0 R/W* 14 DST8O 0 R/W* 6 DST8G 0 R/W* 13 DST8N 0 R/W* 5 DST8F 0 R/W* 12 DST8M 0 R/W* 4 DST8E 0 R/W* 11 DST8L 0 R/W* 3 DST8D 0 R/W* 10 DST8K 0 R/W* 2 DST8C 0 R/W* 9 DST8J 0 R/W* 1 DST8B 0 R/W* 8 DST8I 0 R/W* 0 DST8A 0 R/W* Note: * Only 1 can be written. DSTR is a 16-bit readable/writable register that starts the channel 8 down-counter (DCNT). When the one-shot pulse function is used, a value of 1 can be set in a DST8x bit at any time by the user program, except when the corresponding DCNT8x value is H'0000. The DST8x bits are cleared to 0 automatically when the DCNT value overflows. When the offset one-shot pulse function is used, DST8x is automatically set to 1 (except when the DCNT8x value is H'0000) when a compare-match occurs between the channel 1 or 2 free-running counter (TCNT) and a general register (GR) or the output compare register (OCR1) while the corresponding timer connection register (TCNR) bit is set to 1. As regards DST8I to DST8P, if the RLDEN bit in the reload enable register (RLDENR) is set to 1 and the reload register (RLDR8) value is not H'0000, a reload is performed into the corresponding DCNT8x, and the DST8x bit is set to 1. DST8x is automatically cleared to 0 when the DCNT8x vaue underflows, or by input of a channel 1 or 2 one-shot terminate trigger signal set in the trigger mode register (TRGMDR) while the corresponding one-shot pulse terminate register (OTR) bit is set to 1, whichever occurs first. DCNT8x is cleared to H'0000 when underflow occurs. DSTR is initialized to H'0000 by a power-on reset, and in hardware standby mode and software standby mode. For details, see sections 11.3.5, One-Shot Pulse Function, and 11.3.6, Offset One-Shot Pulse Function and Output Cutoff Function. Rev.2.0, 07/03, page 309 of 960 * Bit 15--Down-Count Start 8P (DST8P): Starts down-counter 8P (DCNT8P). Bit 15: DST8P 0 Description DCNT8P is halted (Initial value) [Clearing conditions] When the DCNT8P value underflows, or on channel 2 (GR2H) comparematch 1 DCNT8P counts [Setting conditions] * One-shot pulse function: Set by user program (DCNT8P H'0000) * Offset one-shot pulse function: Set on OCR2H compare-match (DCNT8P H'0000 or reload possible) or by user program (DCNT8P H'0000) * Bit 14--Down-Count Start 8O (DST8O): Starts down-counter 8O (DCNT8O). Bit 14: DST8O 0 Description DCNT8O is halted (Initial value) [Clearing conditions] When the DCNT8O value underflows, or on channel 2 (GR2G) comparematch 1 DCNT8O counts [Setting conditions] * One-shot pulse function: Set by user program (DCNT8O H'0000) * Offset one-shot pulse function: Set on OCR2G compare-match (DCNT8O H'0000 or reload possible) or by user program (DCNT8O H'0000) * Bit 13--Down-Count Start 8N (DST8N): Starts down-counter 8N (DCNT8N). Bit 13: DST8N 0 Description DCNT8N is halted (Initial value) [Clearing conditions] When the DCNT8N value underflows, or on channel 2 (GR2F) comparematch 1 DCNT8N counts [Setting conditions] * One-shot pulse function: Set by user program (DCNT8N H'0000) * Offset one-shot pulse function: Set on OCR2F compare-match (DCNT8N H'0000 or reload possible) or by user program (DCNT8N H'0000) Rev.2.0, 07/03, page 310 of 960 * Bit 12--Down-Count Start 8M (DST8M): Starts down-counter 8M (DCNT8M). Bit 12: DST8M 0 Description DCNT8M is halted (Initial value) [Clearing conditions] When the DCNT8M value underflows, or on channel 2 (GR2E) comparematch 1 DCNT8M counts [Setting conditions] * One-shot pulse function: Set by user program (DCNT8M H'0000) * Offset one-shot pulse function: Set on OCR2E compare-match (DCNT8M H'0000 or reload possible) or by user program (DCNT8M H'0000) * Bit 11--Down-Count Start 8L (DST8L): Starts down-counter 8L (DCNT8L). Bit 11: DST8L 0 Description DCNT8L is halted (Initial value) [Clearing conditions] When the DCNT8L value underflows, or on channel 2 (GR2D) comparematch 1 DCNT8L counts [Setting conditions] * One-shot pulse function: Set by user program (DCNT8L H'0000) * Offset one-shot pulse function: Set on OCR2D compare-match (DCNT8L H'0000 or reload possible) or by user program (DCNT8L H'0000) * Bit 10--Down-Count Start 8K (DST8K): Starts down-counter 8K (DCNT8K). Bit 10: DST8K 0 Description DCNT8K is halted (Initial value) [Clearing conditions] When the DCNT8K value underflows, or on channel 2 (GR2C) comparematch 1 DCNT8K counts [Setting conditions] * One-shot pulse function: Set by user program (DCNT8K H'0000) * Offset one-shot pulse function: Set on OCR2C compare-match (DCNT8K H'0000 or reload possible) or by user program (DCNT8K H'0000) Rev.2.0, 07/03, page 311 of 960 * Bit 9--Down-Count Start 8J (DST8J): Starts down-counter 8J (DCNT8J). Bit 9: DST8J 0 Description DCNT8J is halted (Initial value) [Clearing conditions] When the DCNT8J value underflows, or on channel 2 (GR2B) comparematch 1 DCNT8J counts [Setting conditions] * One-shot pulse function: Set by user program (DCNT8J H'0000) * Offset one-shot pulse function: Set on OCR2B compare-match (DCNT8J H'0000 or reload possible) or by user program (DCNT8J H'0000) * Bit 8--Down-Count Start 8I (DST8I): Starts down-counter 8I (DCNT8I). Bit 8: DST8I 0 Description DCNT8I is halted (Initial value) [Clearing conditions] When the DCNT8I value underflows, or on channel 2 (GR2A) compare-match 1 DCNT8I counts [Setting conditions] * One-shot pulse function: Set by user program (DCNT8I H'0000) * Offset one-shot pulse function: Set on OCR2A compare-match (DCNT8I H'0000 or reload possible) or by user program (DCNT8I H'0000) * Bit 7--Down-Count Start 8H (DST8H): Starts down-counter 8H (DCNT8H). Bit 7: DST8H 0 Description DCNT8H is halted (Initial value) [Clearing conditions] When the DCNT8H value underflows, or on channel 1 (GR1H or OCR1) compare-match 1 DCNT8H counts [Setting conditions] * One-shot pulse function: Set by user program (DCNT8H H'0000) * Offset one-shot pulse function: Set on OCR1 compare-match or GR1H compare-match, or by user program (DCNT8H H'0000) Rev.2.0, 07/03, page 312 of 960 * Bit 6--Down-Count Start 8G (DST8G): Starts down-counter 8G (DCNT8G). Bit 6: DST8G 0 Description DCNT8G is halted (Initial value) [Clearing conditions] When the DCNT8G value underflows, or on channel 1 (GR1G or OCR1) compare-match 1 DCNT8G counts [Setting conditions] * One-shot pulse function: Set by user program (DCNT8G H'0000) * Offset one-shot pulse function: Set on OCR1 compare-match or GR1G compare-match, or by user program (DCNT8G H'0000) * Bit 5--Down-Count Start 8F (DST8F): Starts down-counter 8F (DCNT8F). Bit 5: DST8F 0 Description DCNT8F is halted (Initial value) [Clearing conditions] When the DCNT8F value underflows, or on channel 1 (GR1F or OCR1) compare-match 1 DCNT8F counts [Setting conditions] * One-shot pulse function: Set by user program (DCNT8F H'0000) * Offset one-shot pulse function: Set on OCR1 compare-match or GR1F compare-match, or by user program (DCNT8F H'0000) * Bit 4--Down-Count Start 8E (DST8E): Starts down-counter 8E (DCNT8E). Bit 4: DST8E 0 Description DCNT8E is halted (Initial value) [Clearing conditions] When the DCNT8E value underflows, or on channel 1 (GR1E or OCR1) compare-match 1 DCNT8E counts [Setting conditions] * One-shot pulse function: Set by user program (DCNT8E H'0000) * Offset one-shot pulse function: Set on OCR1 compare-match or GR1E compare-match, or by user program (DCNT8E H'0000) Rev.2.0, 07/03, page 313 of 960 * Bit 3--Down-Count Start 8D (DST8D): Starts down-counter 8D (DCNT8D). Bit 3: DST8D 0 Description DCNT8D is halted (Initial value) [Clearing conditions] When the DCNT8D value underflows, or on channel 1 (GR1D or OCR1) compare-match 1 DCNT8D counts [Setting conditions] * One-shot pulse function: Set by user program (DCNT8D H'0000) * Offset one-shot pulse function: Set on OCR1 compare-match or GR1D compare-match, or by user program (DCNT8D H'0000) * Bit 2--Down-Count Start 8C (DST8C): Starts down-counter 8C (DCNT8C). Bit 2: DST8C 0 Description DCNT8C is halted (Initial value) [Clearing conditions] When the DCNT8C value underflows, or on channel 1 (GR1C or OCR1) compare-match 1 DCNT8C counts [Setting conditions] * One-shot pulse function: Set by user program (DCNT8C H'0000) * Offset one-shot pulse function: Set on OCR1 compare-match or GR1C compare-match, or by user program (DCNT8C H'0000) * Bit 1--Down-Count Start 8B (DST8B): Starts down-counter 8B (DCNT8B). Bit 1: DST8B 0 Description DCNT8B is halted (Initial value) [Clearing conditions] When the DCNT8B value underflows, or on channel 1 (GR1B or OCR1) compare-match 1 DCNT8B counts [Setting conditions] * One-shot pulse function: Set by user program (DCNT8B H'0000) * Offset one-shot pulse function: Set on OCR1 compare-match or GR1B compare-match, or by user program (DCNT8B H'0000) Rev.2.0, 07/03, page 314 of 960 * Bit 0--Down-Count Start 8A (DST8A): Starts down-counter 8A (DCNT8A). Bit 0: DST8A 0 Description DCNT8A is halted (Initial value) [Clearing conditions] When the DCNT8A value underflows, or on channel 1 (GR1A or OCR1) compare-match 1 DCNT8A counts [Setting conditions] * One-shot pulse function: Set by user program (DCNT8A H'0000) * Offset one-shot pulse function: Set on OCR1 compare-match or GR1A compare-match, or by user program (DCNT8A H'0000) 11.2.12 Timer Connection Register (TCNR) The timer connection register (TCNR) is a 16-bit register. The ATU-II has one TCNR register in channel 8. Bit: 15 CN8P Initial value: R/W: Bit: 0 R/W 7 CN8H Initial value: R/W: 0 R/W 14 CN8O 0 R/W 6 CN8G 0 R/W 13 CN8N 0 R/W 5 CN8F 0 R/W 12 CN8M 0 R/W 4 CN8E 0 R/W 11 CN8L 0 R/W 3 CN8D 0 R/W 10 CN8K 0 R/W 2 CN8C 0 R/W 9 CN8J 0 R/W 1 CN8B 0 R/W 8 CN8I 0 R/W 0 CN8A 0 R/W TCNR is a 16-bit readable/writable register that enables or disables connection between the channel 8 down-count start register (DSTR) and channel 1 and 2 compare-match signals (downcount start triggers). Channel 1 down-count start triggers A to H are channel 1 OCR1 comparematch signals or GR1x compare-match signals (set in TRGMDR). Channel 2 down-count start triggers A to H are channel 2 OCR2x compare-match signals. When GR1x compare-matches are used, set TIOR1A to TIOR1D to allow compare-matches. TCNR is initialized to H'0000 by a power-on reset, and in hardware standby mode and software standby mode. For details, see sections 11.3.5, One-Shot Pulse Function, and 11.3.6, Offset One-Shot Pulse Function and Output Cutoff Function. Rev.2.0, 07/03, page 315 of 960 * Bit 15--Connection Flag 8P (CN8P): Enables or disables connection between DST8P and the channel 2 down-count start trigger. Bit 15: CN8P 0 1 Description Connection between DST8P and channel 2 down-count start trigger H is disabled (Initial value) Connection between DST8P and channel 2 down-count start trigger H is enabled * Bit 14--Connection Flag 8O (CN8O): Enables or disables connection between DST8O and the channel 2 down-count start trigger. Bit 14: CN8O 0 1 Description Connection between DST8O and channel 2 down-count start trigger G is disabled (Initial value) Connection between DST8O and channel 2 down-count start trigger G is enabled * Bit 13--Connection Flag 8N (CN8N): Enables or disables connection between DST8N and the channel 2 down-count start trigger. Bit 13: CN8N 0 1 Description Connection between DST8N and channel 2 down-count start trigger F is disabled (Initial value) Connection between DST8N and channel 2 down-count start trigger F is enabled * Bit 12--Connection Flag 8M (CN8M): Enables or disables connection between DST8M and the channel 2 down-count start trigger. Bit 12: CN8M 0 1 Description Connection between DST8M and channel 2 down-count start trigger E is disabled (Initial value) Connection between DST8M and channel 2 down-count start trigger E is enabled Rev.2.0, 07/03, page 316 of 960 * Bit 11--Connection Flag 8L (CN8L): Enables or disables connection between DST8L and the channel 2 down-count start trigger. Bit 11: CN8L 0 1 Description Connection between DST8L and channel 2 down-count start trigger D is disabled (Initial value) Connection between DST8L and channel 2 down-count start trigger D is enabled * Bit 10--Connection Flag 8K (CN8K): Enables or disables connection between DST8K and the channel 2 down-count start trigger. Bit 10: CN8K 0 1 Description Connection between DST8K and channel 2 down-count start trigger C is disabled (Initial value) Connection between DST8K and channel 2 down-count start trigger C is enabled * Bit 9--Connection Flag 8J (CN8J): Enables or disables connection between DST8J and the channel 2 down-count start trigger. Bit 9: CN8J 0 1 Description Connection between DST8J and channel 2 down-count start trigger B is disabled (Initial value) Connection between DST8J and channel 2 down-count start trigger B is enabled * Bit 8--Connection Flag 8I (CN8I): Enables or disables connection between DST8I and the channel 2 down-count start trigger. Bit 8: CN8I 0 1 Description Connection between DST8I and channel 2 down-count start trigger A is disabled (Initial value) Connection between DST8I and channel 2 down-count start trigger A is enabled Rev.2.0, 07/03, page 317 of 960 * Bit 7--Connection Flag 8H (CN8H): Enables or disables connection between DST8H and the channel 1 down-count start trigger. Bit 7: CN8H 0 1 Description Connection between DST8H and channel 1 down-count start trigger H is disabled (Initial value) Connection between DST8H and channel 1 down-count start trigger H is enabled * Bit 6--Connection Flag 8G (CN8G): Enables or disables connection between DST8G and the channel 1 down-count start trigger. Bit 6: CN8G 0 1 Description Connection between DST8G and channel 1 down-count start trigger G is disabled (Initial value) Connection between DST8G and channel 1 down-count start trigger G is enabled * Bit 5--Connection Flag 8F (CN8F): Enables or disables connection between DST8F and the channel 1 down-count start trigger. Bit 5: CN8F 0 1 Description Connection between DST8F and channel 1 down-count start trigger F is disabled (Initial value) Connection between DST8F and channel 1 down-count start trigger F is enabled * Bit 4--Connection Flag 8E (CN8E): Enables or disables connection between DST8E and the channel 1 down-count start trigger. Bit 4: CN8E 0 1 Description Connection between DST8E and channel 1 down-count start trigger E is disabled (Initial value) Connection between DST8E and channel 1 down-count start trigger E is enabled Rev.2.0, 07/03, page 318 of 960 * Bit 3--Connection Flag 8D (CN8D): Enables or disables connection between DST8D and the channel 1 down-count start trigger. Bit 3: CN8D 0 1 Description Connection between DST8D and channel 1 down-count start trigger D is disabled (Initial value) Connection between DST8D and channel 1 down-count start trigger D is enabled * Bit 2--Connection Flag 8C (CN8C): Enables or disables connection between DST8C and the channel 1 down-count start trigger. Bit 2: CN8C 0 1 Description Connection between DST8C and channel 1 down-count start trigger C is disabled (Initial value) Connection between DST8C and channel 1 down-count start trigger C is enabled * Bit 1--Connection Flag 8B (CN8B): Enables or disables connection between DST8B and the channel 1 down-count start trigger. Bit 1: CN8B 0 1 Description Connection between DST8B and channel 1 down-count start trigger B is disabled (Initial value) Connection between DST8B and channel 1 down-count start trigger B is enabled * Bit 0--Connection Flag 8A (CN8A): Enables or disables connection between DST8A and the channel 1 down-count start trigger. Bit 0: CN8A 0 1 Description Connection between DST8A and channel 1 down-count start trigger A is disabled (Initial value) Connection between DST8A and channel 1 down-count start trigger A is enabled Rev.2.0, 07/03, page 319 of 960 11.2.13 One-Shot Pulse Terminate Register (OTR) The one-shot pulse terminate register (OTR) is a 16-bit register. The ATU-II has one OTR register in channel 8. Bit: 15 OTEP Initial value: R/W: Bit: 0 R/W 7 OTEH Initial value: R/W: 0 R/W 14 OTEO 0 R/W 6 OTEG 0 R/W 13 OTEN 0 R/W 5 OTEF 0 R/W 12 OTEM 0 R/W 4 OTEE 0 R/W 11 OTEL 0 R/W 3 OTED 0 R/W 10 OTEK 0 R/W 2 OTEC 0 R/W 9 OTEJ 0 R/W 1 OTEB 0 R/W 8 OTEI 0 R/W 0 OTEA 0 R/W OTR is a 16-bit readable/writable register that enables or disables forced termination of channel 8 one-shot pulse output by channel 1 and 2 compare-match signals. When one-shot pulse output is forcibly terminated, the corresponding DSTR bit and down-counter are cleared, and the corresponding TSR8 bit is set. The channel 1 one-shot pulse terminate signal is generated by GR1A to GR1H compare-matches and OCR1 compare-match (see TRGMDR). The channel 2 one-shot pulse terminate signal is generated by GR2A to GR2H compare-matches. To generate the terminate signal with GR1A to GR1H and GR2A to GR2H, select the respective compare-matches in TIOR1A to TIOR1D. OTR is initialized to H'0000 by a power-on reset, and in hardware standby mode and software standby mode. * Bit 15--One-Shot Pulse Terminate Enable P (OTEP): Enables or disables forced termination of output by channel 2 down-counter terminate trigger H. Bit 15: OTEP 0 1 Description Forced termination of TO8P by down-counter terminate trigger is disabled (Initial value) Forced termination of TO8P by down-counter terminate trigger is enabled Rev.2.0, 07/03, page 320 of 960 * Bit 14--One-Shot Pulse Terminate Enable O (OTEO): Enables or disables forced termination of output by channel 2 down-counter terminate trigger G. Bit 14: OTEO 0 1 Description Forced termination of TO8O by down-counter terminate trigger is disabled (Initial value) Forced termination of TO8O by down-counter terminate trigger is enabled * Bit 13--One-Shot Pulse Terminate Enable N (OTEN): Enables or disables forced termination of output by channel 2 down-counter terminate trigger F. Bit 13: OTEN 0 1 Description Forced termination of TO8N by down-counter terminate trigger is disabled (Initial value) Forced termination of TO8N by down-counter terminate trigger is enabled * Bit 12--One-Shot Pulse Terminate Enable M (OTEM): Enables or disables forced termination of output by channel 2 down-counter terminate trigger E. Bit 12: OTEM 0 1 Description Forced termination of TO8M by down-counter terminate trigger is disabled (Initial value) Forced termination of TO8M by down-counter terminate trigger is enabled * Bit 11--One-Shot Pulse Terminate Enable L (OTEL): Enables or disables forced termination of output by channel 2 down-counter terminate trigger D. Bit 11: OTEL 0 1 Description Forced termination of TO8L by down-counter terminate trigger is disabled (Initial value) Forced termination of TO8L by down-counter terminate trigger is enabled * Bit 10--One-Shot Pulse Terminate Enable K (OTEK): Enables or disables forced termination of output by channel 2 down-counter terminate trigger C. Bit 10: OTEK 0 1 Description Forced termination of TO8K by down-counter terminate trigger is disabled (Initial value) Forced termination of TO8K by down-counter terminate trigger is enabled Rev.2.0, 07/03, page 321 of 960 * Bit 9--One-Shot Pulse Terminate Enable J (OTEJ): Enables or disables forced termination of output by channel 2 down-counter terminate trigger B. Bit 9: OTEJ 0 1 Description Forced termination of TO8J by down-counter terminate trigger is disabled (Initial value) Forced termination of TO8J by down-counter terminate trigger is enabled * Bit 8--One-Shot Pulse Terminate Enable I (OTEI): Enables or disables forced termination of output by channel 2 down-counter terminate trigger A. Bit 8: OTEI 0 1 Description Forced termination of TO8I by down-counter terminate trigger is disabled (Initial value) Forced termination of TO8I by down-counter terminate trigger is enabled * Bit 7--One-Shot Pulse Terminate Enable H (OTEH): Enables or disables forced termination of output by channel 1 down-counter terminate trigger H. Bit 7: OTEH 0 1 Description Forced termination of TO8H by down-counter terminate trigger is disabled (Initial value) Forced termination of TO8H by down-counter terminate trigger is enabled * Bit 6--One-Shot Pulse Terminate Enable G (OTEG): Enables or disables forced termination of output by channel 1 down-counter terminate trigger G. Bit 6: OTEG 0 1 Description Forced termination of TO8G by down-counter terminate trigger is disabled (Initial value) Forced termination of TO8G by down-counter terminate trigger is enabled * Bit 5--One-Shot Pulse Terminate Enable F (OTEF): Enables or disables forced termination of output by channel 1 down-counter terminate trigger F. Bit 5: OTEF 0 1 Description Forced termination of TO8F by down-counter terminate trigger is disabled (Initial value) Forced termination of TO8F by down-counter terminate trigger is enabled Rev.2.0, 07/03, page 322 of 960 * Bit 4--One-Shot Pulse Terminate Enable E (OTEE): Enables or disables forced termination of output by channel 1 down-counter terminate trigger E. Bit 4: OTEE 0 1 Description Forced termination of TO8E by down-counter terminate trigger is disabled (Initial value) Forced termination of TO8E by down-counter terminate trigger is enabled * Bit 3--One-Shot Pulse Terminate Enable D (OTED): Enables or disables forced termination of output by channel 1 down-counter terminate trigger D. Bit 3: OTED 0 1 Description Forced termination of TO8D by down-counter terminate trigger is disabled (Initial value) Forced termination of TO8D by down-counter terminate trigger is enabled * Bit 2--One-Shot Pulse Terminate Enable C (OTEC): Enables or disables forced termination of output by channel 1 down-counter terminate trigger C. Bit 2: OTEC 0 1 Description Forced termination of TO8C by down-counter terminate trigger is disabled (Initial value) Forced termination of TO8C by down-counter terminate trigger is enabled * Bit 1--One-Shot Pulse Terminate Enable B (OTEB): Enables or disables forced termination of output by channel 1 down-counter terminate trigger B. Bit 1: OTEB 0 1 Description Forced termination of TO8B by down-counter terminate trigger is disabled (Initial value) Forced termination of TO8B by down-counter terminate trigger is enabled * Bit 0--One-Shot Pulse Terminate Enable A (OTEA): Enables or disables forced termination of output by channel 1 down-counter terminate trigger A. Bit 0: OTEA 0 1 Description Forced termination of TO8A by down-counter terminate trigger is disabled (Initial value) Forced termination of TO8A by down-counter terminate trigger is enabled Rev.2.0, 07/03, page 323 of 960 11.2.14 Reload Enable Register (RLDENR) The reload enable register (RLDENR) is an 8-bit register. The ATU-II has one RLDENR register in channel 8. Bit: 7 RLDEN Initial value: R/W: 0 R/W 6 -- 0 R 5 -- 0 R 4 -- 0 R 3 -- 0 R 2 -- 0 R 1 -- 0 R 0 -- 0 R RLDENR is an 8-bit readable/writable register that enables or disables loading of the reload register8 (RLDR8) value into the down-counters (DCNT8I to DCNT8P). Loading is performed on generation of a channel 2 compare-match signal one-shot pulse start trigger. Reloading is not performed if there is no linkage with channel 2 (one-shot pulse function), or while the downcounter (DCNT8I to DCNT8P) is running. RLDENR is initialized to H'00 by a power-on reset and in hardware standby mode and software standby mode. * Bit 7--Reload Enable (RLDEN): Enables or disables loading of the RLDR value into DCNT8I to DCNT8P. Bit 7: RLDEN 0 1 Description Loading of reload register value into down-counters is disabled (Initial value) Loading of reload register value into down-counters is enabled * Bits 6 to 0--Reserved: These bits are always read as 0. The write value should always be 0. Rev.2.0, 07/03, page 324 of 960 11.2.15 Free-Running Counters (TCNT) The free-running counters (TCNT) are 32- or 16-bit up- or up/down-counters. The ATU-II has 17 TCNT counters: one 32-bit TCNT in channel 0, and sixteen 16-bit TCNTs in each of channels 1 to 7 and 11. For details of the channel 10 free-running counters, see section 11.2.26, Channel 10 Registers. Channel 0 1 2 3 4 5 6 7 11 Abbreviation TCNT0H, TCNT0L TCNT1A, TCNT1B TCNT2A, TCNT2B TCNT3 TCNT4 TCNT5 TCNT6A-D TCNT7A-D TCNT11 16-bit up/down-counters (initial value H'0001) 16-bit up-counters (initial value H'0001) 16-bit up-counter (initial value H'0000) Function 32-bit up-counter (initial value Hi00000000) 16-bit up-counters (initial value H'0000) Free-Running Counter 0 (TCNT0H, TCNT0L): Free-running counter 0 (comprising TCNT0H and TCNT0L) is a 32-bit readable/writable register that counts on an input clock. The counter is started when the corresponding bit in the timer start register (TSTR1) is set to 1. The input clock is selected with prescaler register 1 (PSCR1). Bit: 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Initial value: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 R/W: R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Bit: 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Initial value: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 R/W: R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W When TCNT0 overflows (from H'FFFFFFFF to H'00000000), the OVF0 overflow flag in the timer status register (TSR0) is set to 1. TCNT0 can only be accessed by a longword read or write. Word reads or writes cannot be used. Rev.2.0, 07/03, page 325 of 960 TCNT0 is initialized to H'00000000 by a power-on reset, and in hardware standby mode and software standby mode. Free-Running Counters 1A, 1B, 2A, 2B, 3, 4, 5, 11 (TCNT1A, TCNT1B, TCNT2A, TCNT2B, TCNT3, TCNT4, TCNT5, TCNT11): Free-running counters 1A, 1B, 2A, 2B, 3, 4, 5, and 11 (TCNT1A, TCNT1B, TCNT2A, TCNT2B, TCNT3, TCNT4, TCNT5, TCNT11) are 16-bit readable/writable registers that count on an input clock. Counting is started when the corresponding bit in the timer start register (TSTR1 or TSTR3) is set to 1. The input clock is selected with prescaler register 1 (PSCR1) and the timer control register (TCR). Bit: Bit name: Initial value: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 R/W: R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 The TCNT1A, TCNT1B, TCNT2A, and TCNT2B counters are cleared if incremented during counter clear trigger input from channel 10. TCNT3 to TCNT5 counter clearing is performed by a compare-match with the corresponding general register, according to the setting in TIOR. When one of counters TCNT1A/1B/2A/2B/3/4/5/11 overflows (from H'FFFF to H'0000), the overflow flag (OVF) for the corresponding channel in the timer status register (TSR) is set to 1. TCNT1A, TCNT1B, TCNT2A, TCNT2B, TCNT3, TCNT4, TCNT5, and TCNT11 can only be accessed by a word read or write. TCNT1A, TCNT1B, TCNT2A, TCNT2B, TCNT3, TCNT4, TCNT5, and TCNT11 are initialized to H'0000 by a power-on reset, and in hardware standby mode and software standby mode. TCNT1A, TCNT1B, TCNT2A, TCNT2B, TCNT3, TCNT4, and TCNT5 can count on external clock (TCLKA or TCLKB) input. TCNT1A, TCNT1B, TCNT2A, TCNT2B, TCNT3, TCNT4, and TCNT5 can count on an external interrupt clock (TI10) (AGCK) generated in channel 10 and on a channel 10 multiplied clock (AGCKM). Rev.2.0, 07/03, page 326 of 960 Free-Running Counters 6A to 6D and 7A to 7D (TCNT6A to TCNT6D, TCNT7A to TCNT7D): Free-running counters 6A to 6D and 7A to 7D (TCNT6A to TCNT6D, TCNT7A to TCNT7D) are 16-bit readable/writable registers. Channel 6 and 7 counts are started by the timer start register (TSTR2). The clock input to channels 6 and 7 is selected with prescaler registers 2 and 3 (PSCR2, PSCR3) and timer control registers 6 and 7 (TCR6, TCR7). Bit: 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Initial value: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 R/W: R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W TCNT6A to TCNT6D (in non-complementary PWM mode) and TCNT7A to TCNT7D are cleared by a compare-match with the cycle register (CYLR). TCNT6A to TCNT6D (in complementary PWM mode) count up and down between zero and the cycle register value. TCNT6A to TCNT6D and TCNT7A to TCNT7D are connected to the CPU by an internal 16-bit bus, and can only be accessed by a word read or write. TCNT6A to TCNT6D and TCNT7A to TCNT7D are initialized to H'0001 by a power-on reset, and in hardware standby mode and software standby mode. 11.2.16 Down-Counters (DCNT) The DCNT registers are 16-bit down-counters. The ATU-II has 16 DCNT counters in channel 8. Channel 8 Abbreviation DCNT8A, DCNT8B, DCNT8C, DCNT8D, DCNT8E, DCNT8F, DCNT8G, DCNT8H, DCNT8I, DCNT8J, DCNT8K, DCNT8L, DCNT8M, DCNT8N, DCNT8O, DCNT8P Function 16-bit down-counters Rev.2.0, 07/03, page 327 of 960 Down-Counters 8A to 8P (DCNT8A to DCNT8P): Down-counters 8A to 8P (DCNT8A to DCNT8P) are 16-bit readable/writable registers that count on an input clock. The input clock is selected with prescaler register 1 (PSCR1) and the timer control register (TCR). Bit: Bit name: Initial value: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 R/W: R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 When the one-shot pulse function is used, DCNT8x starts counting down when the corresponding DSTR bit is set to 1 by the user program after the DCNT8x value has been set. When the DCNT8x value underflows, DSTR and DCNT8x are automatically cleared to 0, and the count is stopped. At the same time, the corresponding channel 8 timer status register 8 (TSR8) status flag is set to 1. When the offset one-shot pulse function is used, on compare-match with a channel 1 or 2 general register (GR) or output compare register (OCR) (the compare-match setting being made in the trigger mode register (TRGMDR) (for channel 1 only) ) when the corresponding timer connection register (TCNR) bit is 1, the corresponding down-count start register (DSTR) bit is automatically set to 1 and the down-count is started. When the DCNT8x value underflows, the corresponding DSTR bit and DCNT8x are automatically cleared to 0, the count is stopped, and the output is inverted, or, if a one-shot terminate register (OTR) setting has been made to forcibly terminate output by means of a trigger, DSTR is cleared to 0 by a channel 1 or 2 compare-match between GR and OCR, the count is forcibly terminated, and the output is inverted. The output is inverted for whichever is first. When the output is inverted, the corresponding channel 8 TSR8 status flag is set to 1. The DCNT8x counters can only be accessed by a word read or write. The DCNT8x counters are initialized to H'0000 by a power-on reset, and in hardware standby mode and software standby mode. For details, see sections 11.3.5, One-Shot Pulse Function, and 11.3.6, Offset One-Shot Pulse Function and Output Cutoff Function. Rev.2.0, 07/03, page 328 of 960 11.2.17 Event Counters (ECNT) The event counters (ECNT) are 8-bit up-counters. The ATU-II has six ECNT counters in channel 9. Channel 9 Abbreviation ECNT9A, ECNT9B, ECNT9C, ECNT9D, ECNT9E, ECNT9F Function 8-bit event counters The ECNT counters are 8-bit readable/writable registers that count on detection of an input signal from input pins TI9A to TI9F. Rising edge, falling edge, or both rising and falling edges can be selected for edge detection. Bit: 7 6 5 4 3 2 1 0 Initial value: R/W: 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W When a compare-match with GR9 corresponding to an ECNT9x counter occurs, the comparematch flag (CMF9) in the timer status register (TSR9) is set to 1. When a compare-match with GR occurs, the ECNT9x counter is cleared automatically. The ECNT9x counters can only be accessed by a byte read or write. The ECNT9x counters are initialized to H'00 by a power-on reset, and in hardware standby mode and software standby mode. 11.2.18 Output Compare Registers (OCR) The output compare registers (OCR) are 16-bit registers. The ATU-II has nine OCR registers: one in channel 1 and eight in channel 2. For details of the channel 10 free-running counters, see section 11.2.26, Channel 10 Registers. Channel 1 2 Abbreviation OCR1 OCR2A, OCR2B, OCR2C, OCR2D, OCR2E, OCR2F, OCR2G, OCR2H Function Output compare registers Rev.2.0, 07/03, page 329 of 960 Output Compare Registers 1 and 2A to 2H (OCR1, OCR2A to OCR2H) Bit: 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Initial value: 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 R/W: R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W The OCR registers are 16-bit readable/writable registers that have an output compare register function. The OCR and free-running counter (TCNT1B, TCNT2B) values are constantly compared, and if the two values match, the CMF bit in the timer status register (TSR) is set to 1. If channels 1 and 2 and channel 8 are linked by the timer connection register (TCNR), the corresponding channel 8 down-counter (DCNT) is started at the same time. The OCR registers can only be accessed by a word read. The OCR registers are initialized to H'FFFF by a power-on reset, and in hardware standby mode and software standby mode. 11.2.19 Input Capture Registers (ICR) The input capture registers (ICR) are 32-bit registers. The ATU-II has four 32-bit ICR registers in channel 0. For details of the channel 10 free-running counters, see section 11.2.26, Channel 10 Registers. Channel 0 Abbreviation ICR0AH, ICR0AL, ICR0BH, ICR0BL, ICR0CH, ICR0CL, ICR0DH, ICR0DL Function Dedicated input capture registers Rev.2.0, 07/03, page 330 of 960 Input Capture Registers 0AH, 0AL to 0DH, 0DL (ICR0AH, ICR0AL to ICR0DH, ICR0DL) Bit: 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Initial value: R/W: Bit: 0 R 15 0 R 14 0 R 13 0 R 12 0 R 11 0 R 10 0 R 9 0 R 8 0 R 7 0 R 6 0 R 5 0 R 4 0 R 3 0 R 2 0 R 1 0 R 0 Initial value: R/W: 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R The ICR registers are 32-bit read-only registers used exclusively for input capture. These dedicated input capture registers store the TCNT0 value on detection of an input capture signal from an external source. The corresponding TSR0 bit is set to 1 at this time. The input capture signal edge to be detected is specified by timer I/O control register TIOR0. By setting the TRG0DEN bit in TCR10, ICR0DH and ICR0DL can also be used for input capture in a compare match between TCNT10B and OCR10B. The ICR registers can only be accessed by a longword read. Word reads cannot be used. The ICR registers are initialized to H'00000000 by a power-on reset, and in hardware standby mode and software standby mode. 11.2.20 General Registers (GR) The general registers (GR) are 16-bit registers. The ATU-II has 36 general registers: eight each in channels 1 and 2, four each in channels 3 to 5, six in channel 9, and two in channel 11. For details of the channel 10 free-running counters, see section 11.2.26, Channel 10 Registers. Channel 1 2 3 4 5 9 11 Abbreviation GR1A-GR1H GR2A-GR2H GR3A-GR3D GR4A-GR4D GR5A-GR5D GR9A-GR9F GR11A, GR11B Dedicated output compare registers Dual-purpose input capture and output compare registers Function Dual-purpose input capture and output compare registers Rev.2.0, 07/03, page 331 of 960 General Registers 1A to 1H and 2A to 2H (GR1A to GR1H, GR2A to GR2H) Bit: 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Initial value: 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 R/W: R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W These GR registers are 16-bit readable/writable registers with both input capture and output compare functions. Function switching is performed by means of the timer I/O control registers (TIOR). When a general register is used for input capture, it stores the TCNT1A or TCNT2A value on detection of an input capture signal from an external source. The corresponding IMF bit in TSR is set to 1 at this time. The input capture signal edge to be detected is specified by the corresponding TIOR. When a general register is used for output compare, the GR value and free-running counter (TCNT1A, TCNT2A) value are constantly compared, and when both values match, the IMF bit in the timer status register (TSR) is set to 1. If connection of channels 1 and 2 and channel 8 is specified in the timer connection register (TCNR), the corresponding channel 8 down-counter (DCNT) is started. Compare-match output is specified by the corresponding TIOR. The GR registers can only be accessed by a word read or write. The GR registers are initialized to H'FFFF by a power-on reset, and in hardware standby mode and software standby mode. General Registers 3A to 3D, 4A to 4D, 5A to 5D, 11A and 11B (GR3A to GR3D, GR4A to GR4D, GR5A to GR5D, GR11A and GR11B) Bit: 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Initial value: 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 R/W: R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W These GR registers are 16-bit readable/writable registers with both input capture and output compare functions. Function switching is performed by means of the timer I/O control registers (TIOR). When a general register is used for input capture, it stores the corresponding TCNT value on detection of an input capture signal from an external source. The corresponding IMF bit in TSR is set to 1 at this time. The input capture signal edge to be detected is specified by the corresponding Rev.2.0, 07/03, page 332 of 960 TIOR. GR3A to GR3D can also be used for input capture with a channel 9 compare-match as the trigger. In this case, the corresponding IMF bit in TSR is not set. When a general register is used for output compare, the GR value and free-running counter (TCNT) value are constantly compared, and when both values match, the IMF bit in the timer status register (TSR) is set to 1. Compare-match output is specified by the corresponding TIOR. GRIIA and GR11B compare-match signals are transmitted to the advanced pulse controller (APC). For details, see section 12, Advanced Pulse Controller (APC). The GR registers can only be accessed by a word read or write. The GR registers are initialized to H'FFFF by a power-on reset, and in hardware standby mode and software standby mode. General Registers 9A to 9F (GR9A to GR9F) Bit: 7 6 5 4 3 2 1 0 Initial value: R/W: 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W These GR registers are 8-bit readable/writable registers with a compare-match function. The GR value and event counter (ECNT) value are constantly compared, and when both values match a compare-match signal is generated and the next edge is input, the corresponding CMF bit in TSR is set to 1. In addition, channel 3 (GR3A to GR3D) input capture can be generated by GR9A to GR9D compare-matches. This function is set by TRG3xEN in the timer control register (TCR). The GR registers can be accessed by a byte read or write. The GR registers are initialized to H'FF by a power-on reset, and in hardware standby mode and software standby mode. Rev.2.0, 07/03, page 333 of 960 11.2.21 Offset Base Registers (OSBR) The offset base registers (OSBR) are 16-bit registers. The ATU-II has two OSBR registers, one each in channels 1 and 2. Channel 1 2 Abbreviation OSBR1 OSBR2 Function Dedicated input capture registers with signal from channel 0 ICR0A as input trigger Offset Base Registers 1 and 2 (OSBR1, OSBR2) Bit: 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Initial value: R/W: 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R OSBR1 and OSBR2 are 16-bit read-only registers used exclusively for input capture. OSBR1 and OSBR2 use the channel 0 ICR0A input capture register input as their trigger signal, and store the TCNT1A or TCNT2A value on detection of an edge. The OSBR registers can only be accessed by a word read. The OSBR registers are initialized to H'0000 by a power-on reset, and in hardware standby mode and software standby mode. For details, see sections 11.3.8, Twin Capture Function. 11.2.22 Cycle Registers (CYLR) The cycle registers (CYLR) are 16-bit registers. The ATU-II has eight cycle registers, four each in channels 6 and 7. Channel 6 7 Abbreviation CYLR6A- CYLR6D CYLR7A- CYLR7D Function 16-bit PWM cycle registers Rev.2.0, 07/03, page 334 of 960 Cycle Registers (CYLR6A to CYLR6D, CYLR7A to CYLR7D) Bit: 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Initial value: 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 R/W: R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W The CYLR registers are 16-bit readable/writable registers used for PWM cycle storage. The CYLR value is constantly compared with the corresponding free-running counter (TCNT6A to TCNT6D, TCNT7A to TCNT7D) value, and when the two values match, the corresponding timer start register (TSR) bit (CMF6A to CMF6D, CMF7A to CMF7D) is set to 1, and the freerunning counter (TCNT6A to TCNT6D, TCNT7A to TCNT7D) is cleared. At the same time, the buffer register (BFR) value is transferred to the duty register (DTR). Output pin (TO6A to TO6D, TO7A to TO7D) of corresponding channnel will be 0 when H'0000 of BFR is 0 output and otherwise will be 1. The CYLR registers can only be accessed by a word read or write. The CYLR registers are initialized to H'FFFF by a power-on reset, and in hardware standby mode and software standby mode. For details of the CYLR, BFR, and DTR registers, see section 11.3.9, PWM Timer Function. 11.2.23 Buffer Registers (BFR) The buffer registers (BFR) are 16-bit registers. The ATU-II has eight buffer registers, four each in channels 6 and 7. Channel 6 7 Abbreviation BFR6A-BFR6D BFR7A-BFR7D Function 16-bit PWM buffer registers Buffer register (BFR) value is transferred to duty register (DTR) on compare-match of corresponding cycle register (CYLR) Buffer Registers (BFR6A to BFR6D, BFR7A to BFR7D) Bit: 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Initial value: 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 R/W: R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Rev.2.0, 07/03, page 335 of 960 The BFR registers are 16-bit readable/writable registers that store the value to be transferred to the duty register (DTR) in the event of a cycle register (CYLR) compare-match. The BFR registers can only be accessed by a word read or write. The BFR registers are initialized to H'FFFF by a power-on reset, and in hardware standby mode and software standby mode. 11.2.24 Duty Registers (DTR) The duty registers (DTR) are 16-bit registers. The ATU-II has eight duty registers, four each in channels 6 and 7. Channel 6 7 Abbreviation DTR6A-DTR6D DTR7A-DTR7D Function 16-bit PWM duty registers Duty Registers (DTR6A to DTR6D, DTR7A to DTR7D) Bit: 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Initial value: 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 R/W: R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W The DTR registers are 16-bit readable/writable registers used for PWM duty storage. The DTR value is constantly compared with the corresponding free-running counter (TCNT6A to TCNT6D, TCNT7A to TCNT7D) value, and when the two values match, the corresponding channel output pin (TO6A to TO6D, TO7A to TO7D) goes to 0 output. Also, when CYLR and the corresponding the free-running counter match, the corresponding BFR value is loaded. Set a value in the range 0 to CYLR for DTR; do not set a value greater than CYLR. The DTR registers can only be accessed by a word read or write. The DTR registers are initialized to H'FFFF by a power-on reset, and in hardware standby mode and software standby mode. Rev.2.0, 07/03, page 336 of 960 11.2.25 Reload Register (RLDR) The reload register is a 16-bit register. The ATU-II has one RLDR register in channel 8. Reload Register 8 (RLDR8) Bit: 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Initial value: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 R/W: R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W RLDR8 is a 16-bit readable/writable register. When reload is enabled (by a setting in RLDENR) and DSTR8I to DSTR8P are set to 1 by the channel 2 compare-match signal one-shot pulse start trigger, the reload register value is transferred to DCNT8I to DCNT8P before the down-count is started. The reload register value is not transferred when the one-shot pulse function is used independently, without linkage to channel 2, or when down-counters DCNT8I to DCNT8P are running. RLDR8 can only be accessed by a word read or write. RLDR is initialized to H'0000 by a power-on reset, and in hardware standby mode and software standby mode. 11.2.26 Channel 10 Registers Counters (TCNT) Channel 10 has seven TCNT counters: one 32-bit TCNT, four 16-bit TCNTs, and two 8-bit TCNTs. The input clock is selected with prescaler register 4 (PSCR4). Count operations are performed by setting STR10 to 1 in timer start register 1 (TSTR1). Channel 10 Abbreviation TCNT10AH, AL TCNT10B TCNT10C TCNT10D TCNT10E TCNT10F TCNT10G Function 32-bit free-running counter (initial value H'00000001) 8-bit event counter (initial value H'00) 16-bit reload counter (initial value H'0001) 8-bit correction counter (initial value H'00) 16-bit correction counter (initial value H'0000) 16-bit correction counter (initial value H'0001) 16-bit free-running counter (initial value H'0000) Rev.2.0, 07/03, page 337 of 960 Free-Running Counter 10AH, AL (TCNT10AH, TCNT10AL): Free-running counter 10AH, AL (comprising TCNT10AH and TCNT10AL) is a 32-bit readable/writable register that counts on an input clock and is cleared to the initial value by input capture input (TI10) (AGCK). Bit: 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Initial value: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 R/W: R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Bit: 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Initial value: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 R/W: R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W TCNT10A can only be accessed by a longword read or write. Word reads or writes cannot be used. TCNT10A is initialized to H'00000001 by a power-on reset, and in hardware standby mode and software standby mode. Event Counter 10B (TCNT10B): Event counter 10B (TCNT10B) is an 8-bit readable/writable register that counts on external clock input (TI10) (AGCK). For this operation, TI10 input must be set with bits CKEG1 and CKEG0 in TCR10. TI10 input will be counted even if halting of the count operation is specified by bit STR10 in TSTR1. Bit: 7 6 5 4 3 2 1 0 Initial value: R/W: 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W TCNT10B can only be accessed by a byte read or write. TCNT10B is initialized to H'00 by a power-on reset, and in hardware standby mode and software standby mode. Rev.2.0, 07/03, page 338 of 960 Reload Counter 10C (TCNT10C): Reload counter 10C (TCNT10C) is a 16-bit readable/writable register. Bit: 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Initial value: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 R/W: R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W When TCNT10C = H'0001 in the down-count operation, the value in the reload register (RLD10C) is transferred to TCNT10C, and a multiplied clock (AGCK1) is generated. TCNT10C is connected to the CPU via an internal 16-bit bus, and can only be accessed by a word read or write. TCNT10C is initialized to H'0001 by a power-on reset, and in hardware standby mode and software standby mode. Correction Counter 10D (TCNT10D): Correction counter 10D (TCNT10D) is an 8-bit readable/writable register that counts on external clock input (TI10) after transfer of the counter value to correction counter E (TCNT10E). Set TI10 input with bits CKEG1 and CKEG0 in TCR10. Transfer and counting will not be performed on TI10 input unless the count operation is enabled by bit STR10 in TSTR1. Bit: 7 6 5 4 3 2 1 0 Initial value: R/W: 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W At the external clock input (TI10) (AGCK) timing, the value in this counter is shifted according to the multiplication factor set by bits PIM1 and PIM0 in timer I/O control register 10 (TIOR10) and transferred to correction counter E (TCNT10E). TCNT10D can only be accessed by a byte read or write. TCNT10D is initialized to H'00 by a power-on reset, and in hardware standby mode and software standby mode. Rev.2.0, 07/03, page 339 of 960 Correction Counter 10E (TCNT10E): Correction counter 10E (TCNT10E) is a 16-bit readable/writable register that loads the TCNT10D shift value at the external input (TI10) timing, and counts on the multiplied clock (AGCK1) output by reload counter 10C (TCNT10C). However, if CCS in timer I/O control register 10 (TIOR10) is set to 1, when the TCNT10D shifted value is reached the count is halted. Bit: 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Initial value: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 R/W: R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W TCNT10E can only be accessed by a word read or write. TCNT10E is initialized to H'0000 by a power-on reset, and in hardware standby mode and software standby mode. Correction Counter 10F (TCNT10F): Correction counter 10F (TCNT10F) is a 16-bit readable/writable register that counts up on P clock cycles if the counter value is smaller than the correction counter 10E (TCNT10E) value when the STR10 bit in TSTR1 has been set for counter operation. The count is halted by a match with the correction counter clear register (TCCLR10). If TI10 is input when TCNT10D = H'00, TCNT10F is initialized and correction is carried out. When TCNT10F = TCCLR10, TCNT10F is cleared to H'0001. While TCNT10F TCCLR10, TCNT10F is incremented automatically until it reaches the TCCLR10 value, and is then cleared to H'0001. A corrected clock (AGCKM) is output following correction each time this counter is incremented. Bit: 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Initial value: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 R/W: R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W TCNT10F is can only be accessed by a word read or write. TCNT10F is initialized to H'0001 by a power-on reset, and in hardware standby mode and software standby mode. Rev.2.0, 07/03, page 340 of 960 Free-Running Counter 10G (TCNT10G): Free-running counter 10G (TCNT10G) is a 16-bit readable/writable register that counts up on the multiplied clock (AGCK1). TCNT10G is initialized to H'0000 by input from external input (TI10) (AGCK). Bit: 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Initial value: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 R/W: R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W TCNT10G can only be accessed by a word read or write. TCNT10G is initialized to H'0000 by a power-on reset, and in hardware standby mode and software standby mode. Registers There are six registers in channel 10: a 32-bit ICR, 32-bit OCR, 16-bit GR, 16-bit RLD, 16-bit TCCLR, and 8-bit OCR. Channel 10 Abbreviation ICR10AH, AL OCR10AH, AL OCR10B RLD10C GR10G TCCLR10 Function 32-bit input capture register (initial value H'00000000) 32-bit output compare register (initial value H'FFFFFFFF) 8-bit output compare register (initial value H'FF) 16-bit reload register (initial value H'0000) 16-bit general register (initial value H'FFFF) 16-bit correction counter clear register (initial value H'0000) Rev.2.0, 07/03, page 341 of 960 Input Capture Register 10AH, AL (ICR10AH, ICR10AL): Input capture register 10AH, AL (comprising ICR10AH and ICR10AL) is a 32-bit read-only register to which the TCNT10AH, AL value is transferred on external input (TI10) (AGCK). At the same time, ICF10A in timer status register 10 (TSR10) is set to 1. Bit: 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Initial value: R/W: Bit: 0 R 15 0 R 14 0 R 13 0 R 12 0 R 11 0 R 10 0 R 9 0 R 8 0 R 7 0 R 6 0 R 5 0 R 4 0 R 3 0 R 2 0 R 1 0 R 0 Initial value: R/W: 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R ICR10A is initialized to H'00000000 by a power-on reset, and in hardware standby mode and software standby mode. Output Compare Register 10AH, AL (OCR10AH, OCR10AL): Output compare register 10AH, AL (comprising OCR10AH and OCR10AL) is a 32-bit readable/writable register that is constantly compared with free-running counter 10AH, AL (TCNT10AH, TCNT10AL). When both values match, CMF10A in timer status register 10 (TSR10) is set to 1. Bit: 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Initial value: 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 R/W: R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Bit: 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Initial value: 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 R/W: R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W OCR10A is initialized to H'FFFFFFFF by a power-on reset, and in hardware standby mode and software standby mode. Rev.2.0, 07/03, page 342 of 960 Output Compare Register 10B (OCR10B): Output compare register 10B (OCR10B) is an 8-bit readable/writable register that is constantly compared with free-running counter 10B (TCNT10B). When AGCK is input with both values matching, CMF10B in timer status register 10 (TSR10) is set to 1. Bit: 7 6 5 4 3 2 1 0 Initial value: R/W: 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W OCR10B is initialized to H'FF by a power-on reset, and in hardware standby mode and software standby mode. Reload Register 10C (RLD10C): Reload register 10C (RLD10C) is a 16-bit readable/writable register. When STR10 in timer start register 1 (TSTR1) is 1 and RLDEN in the timer I/O control register (TIOR10) is 0, and the value of TCNT10A is captured into input capture register 10A (ICR10A), the ICR10A capture value is shifted according to the multiplication factor set by bits PIM1 and PIM0 in TIOR10 before being transferred to RLD10C. The contents of reload register 10C (RLD10C) are loaded when reload counter 10C (TCNT10C) reaches H'0001. Bit: 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Initial value: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 R/W: R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W RLD10C is initialized to H'0000 by a power-on reset, and in hardware standby mode and software standby mode. General Register 10G (GR10G): General register 10G (GR10G) is a 16-bit readable/writable register with an output compare function. Function switching is performed by means of timer I/O control register 10 (TIOR10). The GR10G value and free-running counter 10G (TCNT10G) value are constantly compared, and when AGCK is input with both values matching, CMF10G in timer status register 10 (TSR10) is set to 1. Bit: 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Initial value: 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 R/W: R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W GR10G is initialized to H'FFFF by a power-on reset, and in hardware standby mode and software standby mode. Rev.2.0, 07/03, page 343 of 960 Correction Counter Clear Register 10 (TCCLR10): Correction counter clear register 10 (TCCLR10) is a 16-bit readable/writable register. TCCLR10 is constantly compared with TCNT10F, and when the two values match, TCNT10F halts. TCNTxx can be cleared at this time by setting TRGxxEN (xx = 1A, 1B, 2A, 2B) in TCR10. Then, when TCNT10D is H'00 and TI10 is input, TCNT10F is cleared to H'0001. Bit: 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Initial value: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 R/W: R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W TCCLR10 is initialized to H'0000 by a power-on reset, and in hardware standby mode and software standby mode. Noise Canceler Registers There are two 8-bit noise canceler registers in channel 10: TCNT10H and NCR10. Channel 10 Abbreviation TCNT10H NCR10 Function Noise canceler counter Noise canceler compare-match register (Initial value H'00) (Initial value H'FF) Noise Canceler Counter 10H (TCNT10H): Noise canceler counter 10H (TCNT10H) is an 8-bit readable/writable register. When the noise canceler function is enabled, TCNT10H starts counting up on P x 10, with the signal from external input (TI10) (AGCK) as a trigger. The counter operates even if STR10 is cleared to 0 in the timer start register (TSTR1). TI10 input is masked while the counter is running. When the count matches the noise canceler register (NCR10) value, the counter is cleared and TI10 input masking is released. Bit: 7 6 5 4 3 2 1 0 Initial value: R/W: 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W TCNT10H is initialized to H'00 by a power-on reset, and in hardware standby mode and software standby mode. Rev.2.0, 07/03, page 344 of 960 Noise Canceler Register 10 (NCR10): Noise canceler register 10 (NCR10) is an 8-bit readable/writable register used to set the upper count limit of noise canceler counter 10H (TCNT10H). TCNT10H is constantly compared with NCR10 during the count, and when a compare-match occurs the TCNT10H counter is halted and input signal masking is released. Bit: 7 6 5 4 3 2 1 0 Initial value: R/W: 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W NCR10 is initialized to H'FF by a power-on reset, and in hardware standby mode and software standby mode. Channel 10 Control Registers There are four control registers in channel 10. Channel 10 Abbreviation TIOR10 Function Reload setting, counter correction setting, external input (TI10) edge interval multiplier setting GR compare-match setting TCR10 TCCLR10 counter clear source Noise canceler function enabling/disabling selection External input (TI10) edge selection TSR10 TIER10 Input capture/compare-match status (Initial value H'00) (Initial value H'0000) (Initial value H'00) Input capture/compare-match interrupt request enabling/disabling selection (Initial value H'0000) Rev.2.0, 07/03, page 345 of 960 Timer I/O Control Register 10 (TIOR10): TIOR10 is an 8-bit readable/writable register that selects the value for multiplication of the external input (TI10) edge interval. It also makes a setting for using the general register (GR10G) for output compare, and makes the edge detection setting. TIOR10 is initialized to H'00 by a power-on reset, and in hardware standby mode and software standby mode. Bit: 7 RLDEN Initial value: R/W: 0 R/W 6 CCS 0 R/W 5 PIM1 0 R/W 4 PIM0 0 R/W 3 -- 0 -- 2 1 0 IO10G2 IO10G1 IO10G0 0 R/W 0 R/W 0 R/W * Bit 7--Reload Enable (RLDEN): Enables or disables transfer of the input capture register 10A (ICR10A) value to reload register 10C (RLD10C). Bit 7: RLDEN 0 1 Description Transfer of ICR10A value to RLD10C on input capture is enabled (Initial value) Transfer of ICR10A value to RLD10C on input capture is disabled * Bit 6--Counter Clock Select (CCS): Selects the operation of correction counter 10E (TCNT10E). Set the multiplication factor with bits PIM1 and PIM0. Bit 6: CCS 0 1 Description TCNT10E count is not halted when TCNT10D x multiplication factor = TCNT10E* (Initial value) TCNT10E count is halted when TCNT10D x multiplication factor = TCNT10E* Note: * When [TCNT10D x multiplication factor] matches the value of TCNT10E with bits 8 to 0 masked * Bits 5 and 4--Pulse Interval Multiplier (PIM1, PIM0): These bits select the external input (TI10) cycle multiplier. Bit 5: PIM1 0 Bit 4: PIM0 0 1 1 0 1 Description Counting on external input cycle x 32 Counting on external input cycle x 64 Counting on external input cycle x 128 Counting on external input cycle x 256 (Initial value) Rev.2.0, 07/03, page 346 of 960 * Bit 3--Reserved: This bit always reads 0. The write value should always be 0. * Bits 2 to 0--I/O Control 10G2 to 10G0 (IO10G2 to IO10G0): These bits select the function of general register 10G (GR10G). Bit 2: IO10G2 0 Bit 1: IO10G1 0 Bit 0: IO10G0 0 1 1 1 * *: Donit care * * Cannot be used Description GR is an output compare register Compare-match disabled (Initial value) GR10G = TCNT10G compare-match Cannot be used Timer Control Register 10 (TCR10): TCR10 is an 8-bit readable/writable register that selects the correction counter clear register (TCCLR10) compare-match counter clear source, enables or disables the noise canceler function, and selects the external input (TI10) edge. TCR10 is initialized to H'00 by a power-on reset, and in hardware standby mode and software standby mode. Bit: 7 6 5 4 3 2 NCE 1 CKEG1 0 CKEG0 TRG2BEN TRG1BEN TRG2AEN TRG1AEN TRG0DEN Initial value: R/W: 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W * Bit 7--Trigger 2B Enable (TRG2BEN): Enables or disables counter clearing for channel 2 TCNT2B. When clearing is enabled, set the correction angle clock (AGCKM) as the TCNT2B count clock. If TCNT2B counts while clearing is enabled, TCNT2B will be cleared. Bit 7: TRG2BEN 0 1 Description Channel 2 counter B (TCNT2B) clearing when correction counter clear register (TCCLR10) = correction counter (TCNT10F) is disabled (Initial value) Channel 2 counter B (TCNT2B) clearing when correction counter clear register (TCCLR10) = correction counter (TCNT10F) is enabled Rev.2.0, 07/03, page 347 of 960 * Bit 6--Trigger 1B Enable (TRG1BEN): Enables or disables counter clearing for channel 1 TCNT1B. When clearing is enabled, set the correction angle clock (AGCKM) as the TCNT1B count clock. If TCNT1B counts while clearing is enabled, TCNT1B will be cleared. Bit 6: TRG1BEN 0 1 Description Channel 1 counter B (TCNT1B) clearing when correction counter clear register (TCCLR10) = correction counter (TCNT10F) is disabled (Initial value) Channel 1 counter B (TCNT1B) clearing when correction counter clear register (TCCLR10) = correction counter (TCNT10F) is enabled * Bit 5--Trigger 2A Enable (TRG2AEN): Enables or disables counter clearing for channel 2 TCNT2A. When clearing is enabled, set the correction angle clock (AGCKM) as the TCNT2A count clock. If TCNT2A counts while clearing is enabled, TCNT2A will be cleared. Bit 5: TRG2AEN 0 1 Description Channel 2 counter 2A (TCNT2A) clearing when correction counter clear register (TCCLR10) = correction counter (TCNT10F) is disabled (Initial value) Channel 2 counter 2A (TCNT2A) clearing when correction counter clear register (TCCLR10) = correction counter (TCNT10F) is enabled * Bit 4--Trigger 1A Enable (TRG1AEN): Enables or disables counter clearing for channel 1 TCNT1A. When clearing is enabled, set the correction angle clock (AGCKM) as the TCNT1A count clock. If TCNT1A counts while clearing is enabled, TCNT1A will be cleared. Bit 4: TRG1AEN 0 1 Description Channel 1 counter 1A (TCNT1A) clearing when correction counter clear register (TCCLR10) = correction counter (TCNT10F) is disabled (Initial value) Channel 1 counter 1A (TCNT1A) clearing when correction counter clear register (TCCLR10) = correction counter (TCNT10F) is enabled * Bit 3--Trigger 0D Enable (TRG0DEN): Enables or disables channel 0 ICR0D input capture signal requests. Bit 3: TRG0DEN 0 1 Description Capture requests for channel 0 input capture register (ICR0D) on event counter (TCNT10B) compare-match are disabled (Initial value) Capture requests for channel 0 input capture register (ICR0D) on event counter (TCNT10B) compare-match are enabled Rev.2.0, 07/03, page 348 of 960 * Bit 2--Noise Canceler Enable (NCE): Enables or disables the noise canceler function. Bit 2: NCE 0 1 Description Noise canceler function is disabled Noise canceler function is enabled (Initial value) * Bits 1 and 0--Clock Edge 1 and 0 (CKEG1, CKEG0): These bits select the channel 10 external input (TI10) edge(s). The clock (AGCK) is generated by the detected edge(s). Bit 1: CKEG1 0 Bit 0: CKEG0 0 1 1 0 1 Description TI10 input disabled TI10 input rising edges detected TI10 input falling edges detected TI10 input rising and falling edges both detected (Initial value) Timer Status Register 10 (TSR10): TSR10 is a 16-bit readable/writable register that indicates the occurrence of channel 10 input capture or compare-match. Each flag is an interrupt source, and issues an interrupt request to the CPU if the interrupt is enabled by the corresponding bit in timer interrupt enable register 10 (TIER10). TSR10 is initialized to H'0000 by a power-on reset, and in hardware standby mode and software standby mode. Bit: 15 -- Initial value: R/W: Bit: 0 R 7 -- Initial value: R/W: 0 R 14 -- 0 R 6 -- 0 R 13 -- 0 R 5 -- 0 R 12 -- 0 R 4 -- 0 R 11 -- 0 R 3 10 -- 0 R 2 9 -- 0 R 1 8 -- 0 R 0 CMF10G CMF10B ICF10A CMF10A 0 R/(W)* 0 R/(W)* 0 R/(W)* 0 R/(W)* Note: * Only 0 can be written to clear the flag. Rev.2.0, 07/03, page 349 of 960 * Bits 15 to 4--Reserved: These bits are always read as 0. The write value should always be 0. * Bit 3--Compare-Match Flag 10G (CMF10G): Status flag that indicates GR10G comparematch. Bit 3: CMF10G 0 1 Description [Clearing condition] (Initial value) When CMF10G is read while set to 1, then 0 is written to IMF10G [Setting condition] When TCNT10G = GR10G * Bit 2--Compare-Match Flag 10B (CMF10B): Status flag that indicates OCR10B comparematch. Bit 2: CMF10B 0 1 Description [Clearing condition] (Initial value) When CMF10B is read while set to 1, then 0 is written to CMF10B [Setting condition] When TCNT10B is incremented while TCNT10B = OCR10B * Bit 1--Input Capture Flag 10A (ICF10A): Status flag that indicates ICR10A input capture. Bit 1: ICF10A 0 1 Description [Clearing condition] (Initial value) When ICR10A is read while set to 1, then 0 is written to ICR10A [Setting condition] When the TCNT10A value is transferred to ICR10A by an input capture signal * Bit 0--Compare-Match Flag 10A (CMF10A): Status flag that indicates OCR10A comparematch. Bit 0: CMF10A 0 1 Description [Clearing condition] (Initial value) When CMF10A is read while set to 1, then 0 is written to CMF10A [Setting condition] When TCNT10A = OCR10A Rev.2.0, 07/03, page 350 of 960 Timer Interrupt Enable Register 10 (TIER10): TIER10 is a 16-bit readable/writable register that controls enabling/disabling of channel 10 input capture and compare-match interrupt requests. TIER10 is initialized to H'0000 by a power-on reset, and in hardware standby mode and software standby mode. Bit: 15 -- Initial value: R/W: Bit: 0 R 7 -- Initial value: R/W: 0 R 14 -- 0 R 6 -- 0 R 13 -- 0 R 5 -- 0 R 12 -- 0 R 4 IREG 0 R/W 11 -- 0 R 3 10 -- 0 R 2 9 -- 0 R 1 8 -- 0 R 0 CME10G CME10B ICE10A CME10A 0 R/W 0 R/W 0 R/W 0 R/W * Bits 15 to 5--Reserved: These bits are always read as 0. The write value should always be 0. * Bit 4--Interrupt Enable Edge G (IREG): Specifies TSR10 CMF10G interrupt request timing. Bit 4: IREG 0 1 Description Interrupt is requested when CMF10G becomes 1 (Initial value) Interrupt is requested by next external input (TI10) (AGCK) after CMF10G becomes 1 * Bit 3--Compare-Match Interrupt Enable 10G (CME10G): Enables or disables interrupt requests by CMF10G in TSR10 when CMF10G is set to 1. Bit 3: CME10G 0 1 Description CMI10G interrupt requested by CMF10G is disabled CMI10G interrupt requested by CMF10G is enabled (Initial value) * Bit 2--Compare-Match Interrupt Enable 10B (CME10B): Enables or disables interrupt requests by CMF10B in TSR10 when CMF10B is set to 1. Bit 2: CME10B 0 1 Description CMI10B interrupt requested by CMF10B is disabled CMI10B interrupt requested by CMF10B is enabled (Initial value) Rev.2.0, 07/03, page 351 of 960 * Bit 1--Input Capture Interrupt Enable 10A (ICE10A): Enables or disables interrupt requests by ICF10A in TSR10 when ICF10A is set to 1. Bit 1: ICE10A 0 1 Description ICI10A interrupt requested by ICF10A is disabled ICI10A interrupt requested by ICF10A is enabled (Initial value) * Bit 0--Compare-Match Interrupt Enable 10A (CME10A): Enables or disables interrupt requests by CMF10A in TSR10 when CMF10A is set to 1. Bit 0: CME10A 0 1 Description CMI10A interrupt requested by CMF10A is disabled CMI10A interrupt requested by CMF10A is enabled (Initial value) 11.3 11.3.1 Operation Overview The ATU-II has twelve timers of eight kinds in channels 0 to 11. It also has a built-in prescaler that generates input clocks, and it is possible to generate or select internal clocks of the required frequency independently of circuitry outside the ATU-II. The operation of each channel and the prescaler is outlined below. Channel 0: Channel 0 has a 32-bit free-running counter (TCNT0) and four 32-bit input capture registers (ICR0A to ICR0D). TCNT0 is an up-counter that performs free-running operation. An interrupt request can be generated on counter overflow. The four input capture registers (ICR0A to ICR0D) capture the free-running counter (TCNT0) value by means of input from the corresponding external signal input pin (TI0A to TI0D). For capture by means of input from an external signal input pin, rising edge, falling edge, or both edges can be selected in the timer I/O control register (TIOR0). In the case of input capture register 0D (ICR0D) only, capture can be performed by means of a compare-match between free-running counter 10B (TCNT10B) and compare-match register 10B (OCR10B), by making a setting in timer control register 10 (TCR10). In this case, capture is performed even if an input capture disable setting has been made for TIOR0. In each case, the DMAC can be activated or an interrupt requested when capture occurs. Channel 0 also has three interval interrupt request registers (ITVRR1, ITVRR2A, and ITVRR2B). A/D converter (AD0 to AD2) activation can be selected by setting 1 in ITVA6 to ITVA13 in ITVRR, and an interrupt request to the CPU by setting 1 in ITVE6 to ITVE13. These operations are performed when the corresponding bit of bits 6 to 13 in TCNT0 changes to 1, enabling use as an interval timer function. Rev.2.0, 07/03, page 352 of 960 Channel 1: Channel 1 has two 16-bit free-running counters (TCNT1A and TCNT1B), eight 16-bit general registers (GR1A to GR1H), and a 16-bit output compare register (OCR1). TCNT1A and TCNT1B are up-counters that perform free-running operation. When the clock generated in channel 10 (described below) is selected, these counters can be cleared at the count specified in channel 10. Each counter can generate an interrupt request when it overflows. The eight general registers (GR1A to GR1H) can be used as input capture or output compare registers using the corresponding external signal I/O pin (TIO1A to TIO1H). When used for input capture, the free-running counter (TCNT1A) value is captured by means of input from the corresponding external signal I/O pin (TIO1A to TIO1H). Rising edge, falling edge, or both edges can be selected for the input capture signal in the timer I/O control registers (TIOR1A to TIOR1D). When used for output compare, compare-match with the free-running counter (TCNT1A) is performed. For the output from the external signal I/O pins by compare-match, 0 output, 1 output, or toggle output can be selected in the timer I/O control registers (TIOR1A to TIOR1D). When used as output compare registers, a compare-match can be used as a one-shot pulse start/terminate trigger by setting the channel 8 timer connection register (TCNR) and oneshot pulse terminate register (OTR), and using these in combination with the down-counters (DCNT8A to DCNT8H). Start/terminate trigger selection is performed by means of the trigger mode register (TRGMDR). The output compare register (OCR1) can be used as a one-shot pulse offset function, in the same way as the general registers, in combination with channel 8 down-counters DCNT8A to DCNT8H. An interrupt can be requested on the occurrence of the respective input capture or compare-match. In addition, channel 1 has a 16-bit dedicated input capture register (OSBR1). The channel 0 TI0A input pin can also be used as the OSBR1 trigger input, enabling use of a twin-capture function. Channel 2: Channel 2 has two 16-bit free-running counters (TCNT2A and TCNT2B), eight 16-bit general registers (GR2A to GR2H), and eight 16-bit output compare registers (OCR2A to OCR2H). TCNT2A and TCNT2B are up-counters that perform free-running operation. When the clock generated in channel 10 (described below) is selected, these counters can be cleared at the count specified in channel 10. Each counter can generate an interrupt request when it overflows. The eight general registers (GR2A to GR2H) can be used as input capture or output compare registers using the corresponding external signal I/O pin (TIO2A to TIO2H). When used for input capture, the free-running counter (TCNT2A) value is captured by means of input from the corresponding external signal I/O pin (TIO2A to TIO2H). Rising edge, falling edge, or both edges can be selected for the input capture signal in the timer I/O control registers (TIOR2A to TIOR2D). When used for output compare, compare-match with the free-running counter (TCNT2A) is performed. For the output from the external signal I/O pins by compare-match, 0 output, 1 output, or toggle output can be selected in the timer I/O control registers (TIOR2A to Rev.2.0, 07/03, page 353 of 960 TIOR2D). When used as output compare registers, a compare-match can be used as a one-shot pulse terminate trigger by setting the channel 8 one-shot pulse terminate register (OTR), and using this in combination with the down-counters (DCNT8I to DCNT8P). In the case of the output compare registers (OCR2A to OCR2H), a TCNT2B compare-match can be used as a one-shot pulse start trigger by setting the channel 8 timer connection register (TCNR), and using this in combination with the down-counters (DCNT8I to DCNT8P). An interrupt can be requested on the occurrence of the respective input capture or compare-match. In addition, channel 2 has a 16-bit dedicated input capture register (OSBR2). The channel 0 TI0A input pin can also be used as the OSBR2 trigger input, enabling use of a twin-capture function. Channels 3 to 5: Channels 3 to 5 each have a 16-bit free-running counter (TCNT3 to TCNT5) and four 16-bit general registers (GR3A to GR3D, GR4A to GR4D, GR5A to GR5D). TCNT3 to TCNT5 are up-counters that perform free-running operation. Channels 3 to 5 each have a 16-bit free-running counter (TCNT3 to TCNT5) and four 16-bit general registers (GR3A to GR3D, GR4A to GR4D, GR5A to GR5D). TCNT3 to TCNT5 are up-counters that perform free-running operation. In addition, counter clearing can be performed by compare-match by making a setting in the timer I/O control register (TIOR3A, TIOR3B, TIOR4A, TIOR4B, TIOR5A, TIOR5B). Each counter can generate an interrupt request when it overflows. The four general registers (GR3A to GR3D, GR4A to GR4D, GR5A to GR5D) each have corresponding external signal I/O pins (TIO3A to TIO3D, TIO4A to TIO4D, TIO5A to TIO5D), and can be used as input capture or output compare registers. When used for input capture, the free-running counter (TCNT3 to TCNT5) value is captured by means of input from the corresponding external signal I/O pin (TIO3A to TIO3D, TIO4A to TIO4D, TIO5A to TIO5D). Rising edge, falling edge, or both edges can be selected for the input capture signal in the timer I/O control registers (TIOR3A, TIOR3B, TIOR4A, TIOR4B, TIOR5A, TIOR5B). Also, in use for input capture, input capture can be performed using a compare-match between a channel 9 event counter (ECNT9A to ECNT9D), described later, and a general register (GR9A to GR9D) as the trigger (channel 3 only). In this case, capture is performed even if an input capture disable setting has been made for TIOR3A to TIOR3D. When used for output compare, compare-match with the free-running counter (TCNT3 to TCNT5) is performed. For the output from the external signal I/O pins by compare-match, 0 output, 1 output, or toggle output can be selected in the timer I/O control registers (TIOR3A, TIOR3B, TIOR4A, TIOR4B, TIOR5A, TIOR5B). An interrupt can be requested on the occurrence of the respective input capture or compare-match. However, in the case of input capture using channel 9 as a trigger, an interrupt request from channel 3 cannot be used. By selecting PWM mode in the timer mode register (TMDR), PWM output can be obtained, with three outputs for each. In this case, GR3D, GR4D, and GR5D are automatically used as cycle registers, and GR3A to GR3C, GR4A to GR4C, GR5A to GR5C, as duty registers. TCNT3 to TCNT5 are cleared by the corresponding GR3D, GR4D, or GR5D compare-match. Rev.2.0, 07/03, page 354 of 960 Channels 6 and 7: Channels 6 and 7 each have 16-bit free-running counters (TCNT6A to TCNT6D, TCNT7A to TCNT7D), 16-bit cycle registers (CYLR6A to CYLR6D, CYLR7A to CYLR7D), 16-bit duty registers (DTR6A to DTR6D, DTR7A to DTR7D), and buffer registers (BFR6A to BFR6D, BFR7A to BFR7D). Channels 6 and 7 also each have external output pins (TO6A to TO6D, TO7A to TO7D), and can be used as buffered PWM timers. The TCNT registers are up-counters, and 0 is output to the corresponding external output pin when the TCNT value matches the DTR value (when DTR CYLR). When the TCNT value matches the CYLR value (when DTR H'0000), 1 is output to the external output pin, TCNT is initialized to H'0001, and the BFR value is transferred to DTR. Thus, the configuration of channels 6 and 7 enables them to perform waveform output with the CYLR value as the cycle and the DTR value as the duty, and to use BFR to absorb the time lag between setting of data in DTR and compare-match occurrence. When DTR = CYLR, 1 is output continuously to the external output pin, giving a duty of 100%. When DTR = H'0000, 0 is output continuously to the external output pin, giving a duty of 0%. Do not set a value in DTR that will result in the condition DTR > CYLR. When H'0000 is set to DTR, do not have DTR directly read H'0000. Set BFR to H'0000 and set H'0000 by forwarding from BFR to DTR. If H'0000 is directly set to DTR, duty may not be 0%. In channel 6, TCNT can also be designated for complementary PWM output by means of the PWM mode register (PMDR). When the corresponding TSTR is set to 1, TCNT starts counting up, then switches to a down-count when the count matches the CYLR value. When TCNT reaches H'0000, it starts counting up again. When TCNT = DTR, the corresponding TO6A to TO6D output changes. Whether TCNT is counting up or down can be ascertained from the timer status register (TSR6). DMAC activation and interrupt request generation, respectively, are possible when TCNT = CYLR in asynchronous PWM mode, and when TCNT = H'0000 in complementary PWM mode. Channel 8: Channel 8 has sixteen 16-bit down-counters (DCNT8A to DCNT8P). The downcounters have corresponding external signal output pins, and can generate one-shot pulses. Setting a value in DCNT and setting the corresponding bit to 1 in the down-count start register (DSTR) starts DCNT operation and simultaneously outputs 1 to the external output pin. When DCNT counts down to H'0000, it stops and outputs 0 to the external output pin. An interrupt can be requested when DCNT underflows. Down-counter operation can be coupled with the channel 1 or channel 2 output compare function by means of settings in the timer connection register (TCNR) and one-shot pulse terminate register (OTR), respectively, so that DCNT8I to DCNT8H count operations are started and stopped from channel 1, and DCNT8I to DCNT8P count operations from channel 2. DCNT8I to DCNT8P have a reload register (RLDR), and a setting in the reload enable register (RLDEN) enables count operations to be started after reading the value from this register. Rev.2.0, 07/03, page 355 of 960 Channel 9: Channel 9 has six 8-bit event counters (ECNT9A to ECNT9F) and six 8-bit general registers (GR9A to GR9F). The event counters are up-counters, each with a corresponding external input pin (ECNT9A to ECNT9F). The event counter value is incremented by input from the corresponding external input pin. Incrementing on the rising edge, falling edge, or both edges can be selected by means of settings in the timer control registers (TCR9A to TCR9C). An event counter is cleared by edge input after a match with the corresponding general register. An interrupt can requested when an event counter is cleared. Timer control register (TCR9A, TCR9B) settings can be made to enable event counters ECNT9A to ECNT9D to send a compare-match signal to channel 3 when the count matches the corresponding general register (GR9A to GR9D), allowing input capture to be performed on channel 3. This enables the pulse input interval to be measured. Channel 10: Channel 10 generates a multiplied clock based on external input, and supplies this to channels 1 to 5. Channel 10 is divided into three blocks: (1) an inter-edge measurement block, (2) a multiplied clock generation block, and (3) a multiplied clock correction block. (1) Inter-edge measurement block This block has a 32-bit free-running counter (TCNT10A), 32-bit input capture register (ICR10A), 32-bit output compare register (OCR10A), 8-bit event counter (TCNT10B), 8-bit output compare register (OCR10B), 8-bit noise canceler counter (TCNT10H), and 8-bit noise canceler compare-match register (NCR10). The 32-bit free-running counter (TCNT10A) is an up-counter that performs free-running operations. When input capture is performed by means of TI10 input, this counter is cleared to H'00000001. When free-running counter (TCNT10A) reaches the value set in the output compare register (OCR10A), a compare-match interrupt can be requested. The input capture register (ICR10A) has an external signal input pin (TI10), and the freerunning counter (TCNT10A) value can be captured by means of input from TI10. Rising edge, falling edge, or both edges can be selected by making a setting in bits CKEG1 and CKEG0 in the timer control register (TCR10). The TI10 input has a noise canceler function, which can be enabled by setting the NCE bit in the timer control register (TCR10). When the counter value is captured, TCNT10A is cleared to 0 and an interrupt can be requested. The captured value can be transferred to the multiplied clock generation block reload register (RLD10C). The 8-bit event counter (TCNT10B) is an up-counter that is incremented by TI10 input. When the event counter (TCNT10B) value reaches the value set in the output compare register (OCR10B), a compare-match interrupt can be requested. By setting the TRG0DEN bit in the timer control register (TCR10), a capture request can also be issued for the channel 0 input capture register 0D (ICR0D) when compare-match occurs. The 16-bit noise canceler counter (TCNT10H) and 16-bit noise canceler compare-match register (NCR10) are used to set the period for which the noise canceler functions. By setting a Rev.2.0, 07/03, page 356 of 960 value in the noise canceler compare-match register (TCNT10H) and setting the NCE bit in the timer control register (TCR10), TI10 input is masked when it occurs. At the same time as TI10 input is masked, the noise canceler counter (TCNT10H) starts counting up on the Px10 clock. When the noise canceler counter (TCNT10H) value matches the noise canceler compare-match register (NCR10) value, the noise canceler counter (TCNT10H) is cleared to H'0000 and TI10 input masking is cleared. (2) Multiplied clock generation block This block has 16-bit reload counters (TCNT10C, RLD10C), a 16-bit register free-running counter (TCNT10G), and a 16-bit general register (GR10G). 16-bit reload counter 10C (RLD10C) is captured by 32-bit input capture register 10A (ICR10A), and when RLDEN in the timer I/O control register (TIOR10) is 0, the value captured in input capture register 10A is transferred to the multiplied clock generation block reload register (RLD10C). The value transferred can be selected from 1/32, 1/64, 1/128, or 1/256 the original value, according to the setting of bits PIM1 and PIM0 in TIOR10. 16-bit reload counter 10C (TCNT10C) performs down-count operations. When TCNT10C reaches H'0001, the value is read automatically from the reload buffer (RLD10C), internal clock AGCK1 is generated, and the down-count operation is repeated. Internally generated AGCK1 is input as a clock to the multiplied clock correction block 16-bit correction counter (TCNT10E) and 16-bit free-running counter 10G (TCNT10G). 16-bit register free-running counter 10G (TCNT10G) counts on AGCK1 generated by TCNT10C. It is initialized to H'0000 by external input from TI10. The 16-bit general register (GR10G) can be used in a compare-match with free-running counter 10G (TCNT10G) by setting bits IO10G2 to IO10G0 in the timer I/O control register (TIOR10). An interrupt can be requested when a compare-match occurs. Also, by setting timer interrupt enable register 10 (TIER10), an interrupt can be request in the event of TI10 input after a compare-match. (3) Multiplied clock correction block This block has three 16-bit correction counters (TCNT10D, TCNT10E, TCNT10F) and a 16bit correction counter clear register (TCCLR10). When 32-bit input capture register 10A (ICR10A) performs a capture operation due to input from external input pin TI10, the value in correction counter 10D (TCNT10D) is transferred to TCNT10E and TCNT10D is incremented. The value transferred to TCNT10E is 32, 64, 128, or 256 times the TCNT10D value, according to the setting of bits PIM1 and PIM0 in the timer I/O control register (TIOR10). Rev.2.0, 07/03, page 357 of 960 16-bit correction counter 10E (TCNT10E) counts up on AGCK1 generated by reload counter 10C (TCNT10C, RLD10C) in the multiplied clock generation block. However, by setting the CCS bit in the timer I/O control register (TIOR10), it is possible to stop free-running counter 10E (TCNT10E) when the free-running counter 10D (TCNT10D) multiplication value specified by PIM1 and PIM0 and the free-running counter 10E (TCNT10E) value match. The multiplied TCNT10D value is transferred when input capture register 10A (ICR10A) performs a capture operation due to TI10 input. 16-bit correction counter 10F (TCNT10F) has P as its input and is constantly compared with 16-bit correction counter 10E (TCNT10E). When the 16-bit correction counter 10F (TCNT10F) value is smaller than that in 16-bit correction counter 10E (TCNT10E), it is incremented and generates count-up AGCKM. When the 16-bit correction counter 10F (TCNT10F) value exceeds that in 16-bit correction counter 10E (TCNT10E) (for example, when TCNT10F reloads TCNT10D), no count-up operation is performed. The TI10 multiplied signal (AGCKM) generated when TCNT10F is incremented is output to the channel 1 to 5 free-running counters (TCNT1A, TCNT1B, TCNT2A, TCNT2B, TCNT3, TCNT4, TCNT5), and an up-count can be performed on AGCKM by setting this as the counter clock on each channel. TCNT10F is constantly compared with the 16-bit correction counter clear register (TCCLR10), and when the free-running counter 10F (TCNT10F) and correction counter clear register (TCCLR10) values match, the TCNT10F up-count stops. Setting TRG1AEN, TRG1BEN, TRG2AEN, and TRG2BEN in the timer control register (TCR10) enables the channel 1 and 2 free-running counters (TCNT1A, TCNT1B, TCNT2A, TCNT2B) to be cleared at this time. If TI10 is input when TCNT10D = H'0000, initialization and correction operations are performed. When TCNT10F = TCCLR10, TCNT10F is cleared to H'0001. When TCNT10F TCCLR10, TCNT10F automatically counts up to the TCCLR10 value, and is cleared to H'0001. Channel 11: Channel 11 has a 16-bit free-running counter (TCNT11) and two 16-bit general registers (GR11A and GR11B). TCNT11 is an up-counter that performs free-running operation. The counter can generate an interrupt request when it overflows. The two general registers (GR11A and GR11B) each have a corresponding external signal I/O pin (TIO11A, TIO11B), and can be used as input capture or output compare registers. When used for input capture, the free-running counter (TCNT11) value is captured by means of input from the corresponding external signal I/O pin (TIO11A, TIO11B). Rising edge, falling edge, or both edges can be selected for the input capture signal in the timer I/O control register (TIOR11). When used for output compare, compare-match with the free-running counter (TCNT11) is performed. For the output from the external signal I/O pins by compare-match, 0 output, 1 output, or toggle output can be selected in the timer I/O control register (TIOR11). An interrupt can be requested on the occurrence of the respective input capture or compare-match. When the two general registers (GR11A and GR11B) are designated for compare-match use, a compare-match signal can be output to the APC. Rev.2.0, 07/03, page 358 of 960 Prescaler: The ATU-II has a dedicated prescaler with a 2-stage configuration. The first stage comprises 5-bit prescalers (PSCR1 to PSCR4) that generate a 1/m clock (where m = 1 to 32) with respect to clock P. The second prescaler stage allows selection of a clock obtained by further scaling the clock from the first stage by 2n (where n = 0 to 5) according to the timer control registers for the respective channels (TCR1A, TCR1B, TCR2A, TCR2B, TCR3 to TCR5, TCR6A, TCR6B, TCR7A, TCR7B, TCR8, TCR11). The prescalers of channels 1 to 8 and 11 have a 2-stage configuration, while the channel 0 and 10 prescalers only have a first stage. The first-stage prescaler is common to channels 0 to 5, 8, and 11, and it is not possible to set different first-stage division ratios for each. Channels 6, 7, and 10 each have a first-stage prescaler, and different first-stage division ratios can be set for each. 11.3.2 Free-Running Counter Operation and Cyclic Counter Operation The free-running counters (TCNT) in ATU-II channels 0 to 5 and 11 start counting up as freerunning counters when the corresponding timer start register (TSTR) bit is set to 1. When TCNT overflows (channel 0: from H'FFFFFFFF to H'00000000; channels 1 to 5 and 11: from H'FFFF to H'0000), the OVF bit in the timer status register (TSR) is set to 1. If the OVE bit in the corresponding timer interrupt enable register (TIER) is set to 1 at this time, an interrupt request is sent to the CPU. After overflowing, TCNT starts counting up again from H'00000000 or H'0000. If the TSTR value is cleared to 0 during TCNT operation, the corresponding TCNT halts. In this case, TCNT is not reset. If external output is being performed from the GR for the corresponding TCNT, the output value does not change. Channel 0 free-running counter operation is shown in figure 11.13. Po TSTR TST0 TCNT0 Clock TCNT0 00000001 00000001 00000002 00000003 00000004 00000005 FFFFFFFD FFFFFFFE FFFFFFFF 00000000 00000001 00000002 Cleared by software TSR0 OVF0 Figure 11.13 Free-Running Counter Operation and Overflow Timing The free-running counters (TCNT) in ATU-II channels 6 and 7 perform cyclic count operations unconditionally. With channel 3 to 5 free-running counters (TCNT), when the corresponding T3PWM to T5PWM bit in the timer mode register (TMDR) is set to 1, or the corresponding CCI bit in the timer I/O control register (TIOR) is set to 1 when bits T3PWM to T5PWM are 0, the Rev.2.0, 07/03, page 359 of 960 counter for the relevant channel performs a cyclic count. The relevant TCNT counter is cleared by a compare-match of TCNT with GR3D, GR4D, or GR5D in channel 3 to 5, or CYLR in channels 6 and 7 (counter clear function). TCNT starts counting up as a cyclic counter when the corresponding STR bit in TSTR is set to 1 after the TMDR setting is made. When the count value matches the GR3D, GR4D, GR5D, or CYLR value, the corresponding IMF3D, IMF4D, or IMF5D bit in the timer status register (TSR) (or the CMF bit in TSR6 or TSR7 for channels 6 and 7) is set to 1, and TCNT is cleared to H'0000 (H'0001 in channels 6 and 7). If the corresponding TIER bit is set to 1 at this time, an interrupt request is sent to the CPU. After the compare-match, TCNT starts counting up again from H'0000 (H'0001 in channels 6 and 7). Figure 11.14 shows the operation when channel 3 is used as a cyclic counter (with a cycle setting of H'0008). Po TCNT3 Clock TCNT3 GR3D (period) 0008 0000 0001 0002 0003 0007 0008 0000 0001 0002 0003 0004 0005 0008 Cleared by software 0008 Cleared by software TSR3 IMF3D Figure 11.14 Example of Cyclic Counter Operation 11.3.3 Compare-Match Function Designating general registers in channels 1 to 5 and 11 (GR1A to GR1H, GR2A to GR2H, GR3A to GR3D, GR4A to GR4D, GR5A to GR5D, GR11A, GR11B) for compare-match operation in the timer I/O control registers (TIOR1 to TIOR5, TIOR11) enables compare-match output to be performed at the corresponding external pins (TIO1A to TIO1H, TIO2A to TIO2H, TIO3A to TIO3D, TIO4A to TIO4D, TIO5A to TIO5D, TIO11A, TIO11B). A free-running counter (TCNT) starts counting up when 1 is set in the timer status register (TSTR). When the desired number is set beforehand in GR, and the TCNT value matches the GR value, the timer status register (TSR) bit corresponding to GR is set and a waveform is output from the corresponding external pin. 1 output, 0 output, or toggle output can be selected by means of a setting in TIOR. If the appropriate interrupt enable register (TIER) setting is made, an interrupt request will be sent to the CPU when a compare-match occurs. Rev.2.0, 07/03, page 360 of 960 To perform internal interrupts by compare-match or compare-match flag polling processing without performing compare-match output, designate the corresponding compare-match output pin as a general I/O pin and select 1 output, 0 output, or toggle output on compare-match in TIOR. Channel 1 and 2 compare-match registers (OCR1, OCR2A to OCR2H) perform compare-match operations unconditionally. However, there are no corresponding output pins. If the appropriate TIER setting is made, an interrupt request will be sent to the CPU when a compare-match occurs. Channel 1 and 2 GR and OCR registers can send a trigger/terminate signal to channel 8 when a compare-match occurs. In this case, settings should be made in the trigger mode register (TRGMDR), timer connection register (TCNR), and one-shot pulse terminate register (OTR). An example of compare-match operation is shown in figure 11.15. In the example in figure 11.15, channel 1 is activated, and external output is performed with toggle output specified for GR1A, 1 output for GR1B, and 0 output for GR1C. Po TCNT1 Clock TCNT1 003C 003D 003E 003F 0040 007E 007F 0080 0081 0082 0083 0084 0085 GR1A-1C 003E 0081 TIO1A TIO1B TIO1C TSR1 IMF1A-1D Channel 8 start/terminate trigger signal Cleared by software Cleared by software Figure 11.15 Compare-Match Operation 11.3.4 Input Capture Function If input capture registers (ICR0A to ICR0D) and general registers (GR1A to GR1H, GR2A to GR2H, GR3A to GR3D, GR4A to GR4D, GR5A to GR5D, GR11A, GR11B) in channels 1 to 5 and 11 are designated for input capture operation in the timer I/O control registers (TIOR0 to TIOR5, TIOR11), input capture is performed when an edge is input at the corresponding external Rev.2.0, 07/03, page 361 of 960 pins (TI0A to TI0D, TIO1A to TIO1H, TIO2A to TIO2H, TIO3A to TIO3D, TIO4A to TIO4D, TIO5A to TIO5D). A free-running counter (TCNT) starts counting up when a setting is made in the timer start register (TSTR). When an edge is input at an external pin corresponding to ICR or GR, the corresponding timer status register (TSR) bit is set and the TCNT value is transferred to ICR or GR. Rising-edge, falling-edge, or both-edge detection can be selected. By making the appropriate setting in the interrupt enable register (TIER), an interrupt request can be sent to the CPU. An example of input capture operation is shown in figure 11.16. In the example in figure 11.16, channel 1 is activated, and input capture operation is performed with both-edge detection specified for TIO1A, rising-edge detection for TIO1B, and falling-edge detection for TIO1C. Po TCNT1 Clock TCNT1 0000 0001 0002 0003 0004 0005 5678 5679 567A 567B 567C 567D 567E TIO1A-1C GR1A GR1B GR1C 0003 0003 567A 0003 567A Cleared by software Cleared by software TSR1 IMF1A TSR1 IMF1B TSR1 IMF1C Figure 11.16 Input Capture Operation 11.3.5 One-Shot Pulse Function Channel 8 has sixteen down-counters (DCNT8A to DCNT8P) and corresponding external pins (TO8A to TO8P) which can be used as one-shot pulse output pins. When a value is set beforehand in DCNT and the corresponding bit in the down-counter start register (DSTR) is set, DCNT starts counting down, and at the same time 1 is output from the corresponding external pin. When DCNT reaches H'0000 the down-count stops, the corresponding bit in the timer status register (TSR) is set, and 0 is output from the external pin. The Rev.2.0, 07/03, page 362 of 960 corresponding bit in DSTR is cleared automatically. By making the appropriate setting in the interrupt enable register (TIER), an interrupt request can be sent to the CPU. An example of one-shot pulse operation is shown in figure 11.17. In the example in figure 11.17, H'0005 is set in DCNT and a down-count is started. Po DSTR DST8A DCNT Clock Synchronized with down-counter clock TO8A DCNT8A 0005 0004 0003 0002 0001 0000 Cleared by software TSR8 Figure 11.17 One-Shot Pulse Output Operation 11.3.6 Offset One-Shot Pulse Function and Output Cutoff Function By making an appropriate setting in the timer connection register (TCNR), down-counting by channel 8 down-counters (DCNT8A to DCNT8P) can be started using compare-match signals from channel 1 general registers (GR1A to GR1H) or channel 1 and 2 compare-match registers (OCR1, OCR2A to OCR2H). DCNT8A to DCNT8H are connected to channel 1 OCR1 or GR1A to GR1H, and DCNT8I to DCNT8P are connected to channel 2 OCR2A to OCR2H or GR2A to GR2H. This enables one-shot pulse output from the external pin (TO8A to TO8P) corresponding to DCNT. The down-count can be forcibly stopped by making a setting in the one-shot pulse terminate register (OTR). On channel 1, down-count start or termination by a GR or OCR compare-match can be selected with the trigger mode register (TRGMDR). Making a setting in the timer start register (TSTR) starts an up-count by a free-running counter (TCNT) in channel 1 or 2. When TCNT matches GR or OCR while connection is enabled by TCNR, the corresponding DSTR is automatically set and DCNT starts counting down. At the same time, 1 is output from the corresponding external pin (TO8A to TO8P). By making the appropriate setting in the interrupt enable register (TIER), an interrupt request can be sent to the CPU. When TCNT1 matches GR or OCR, or TCNT2 matches GR, while channel 8 one-shot pulse termination by a channel 1 or 2 compare-match signal is enabled by OTR, the corresponding Rev.2.0, 07/03, page 363 of 960 DSTR is automatically cleared and DCNT stops counting down. DCNT is cleared to H'0000 at this time, and must be rewritten before the down-count is restarted. DCNT8I to DCNT8P are connected to the reload register (RLDR8), and when the DSTR corresponding to DCNT8I to DCNT8P is set, the DCNT8I to DCNT8P counter loads RLDR8 before starting the down-count. An example of the offset one-shot pulse output function and output cutoff function is shown in figure 11.18. P First prescaler 1 Second prescaler 1 Start trigger (OSTRG1A-P) Terminate trigger (OSTRG0A-P) Down-count start trigger (corresponding bit) Down-counter 10A-10P clock One-shot pulse (TOA10-TOP10) Down-counter 10A-10P Synchronized with down-counter clock 0009 0008 0007 0006 0005 0004 0003 0000 One-shot end detection signal One-shot end interrupt (flag) Figure 11.18 Offset One-Shot Pulse Output Function and Output Cutoff Function Operation 11.3.7 Interval Timer Operation The interval interrupt request registers (ITVRR1, ITVRR2A, ITVRR2B) are connected to bits 6 to 9 and 10 to 13 of the channel 0 free-running counter (TCNT0). The ITVRR registers are 8-bit registers; the upper 4 bits (ITVA) are used for A/D converter activation, and the lower 4 bits (ITVE) are used for interrupt requests. ITVRR1 is connected to A/D converter 2 (AD2), ITVRR2A to A/D converter 0 (AD0), and ITVRR2B to A/D converter 1 (AD1). When the ITVA bit for the desired timing is set, the A/D converter is activated when the corresponding bit of TCNT0 changes to 1. Rev.2.0, 07/03, page 364 of 960 When the ITVE bit for the desired timing is set, an interrupt can be requested when the corresponding bit of TCNT0 changes to 1. At this time, the corresponding bit of the timer status register (TSR0) is set. There are four interrupt sources for the respective ITVRR registers, but there is only one interrupt vector. To suppress interrupts and A/D converter activation, ITVRR bits should be cleared to 0. An example of interval timer function operation is shown in figure 11.19. In the example in figure 11.19, TCNT0 is started by setting ITVE to 1 in ITVRR1. Po TCNT0 Clock TCNT0 0000003C 0000003D 0000003E 0000003F 00000040 0000007E 0000007F Internal detection signal AD activation trigger In case of bit 6 detection 00000080 00000081 00000082 00000083 00000084 00000085 In case of bit 7 detection Figure 11.19 Interval Timer Function 11.3.8 Twin-Capture Function Channel 0 input capture register ICR0A, channel 1 offset base register 1 (OSBR1), and channel 2 offset base register 2 (OSBR2) can be made to perform input capture in response to the same trigger by means of a setting in timer I/O control register 0 (TIOR0). When TCNT0, TCNT1A, and TCNT2A in channel 0, channel 1, and channel 2 are started by a setting in the timer status register (TSR), and an edge detection is carried out by the ICR0A input as a trigger signal, the TCNT1A value is transferred to OSBR1, and the TCNT2A value to OSBR2. Edge detection is as described in section 11.3.4, Input Capture Function. An example of twin-capture operation is shown in figure 11.20. Rev.2.0, 07/03, page 365 of 960 Po TCNT1A Clock TCNT1A 0000 0001 0002 0003 0004 0005 5678 5679 567A 567B 567C 567D 567E Edge detection signal (from channel 0) OSBR1 0003 567A Figure 11.20 Twin-Capture Operation 11.3.9 PWM Timer Function Channels 6 and 7 can be used unconditionally as PWM timers using external pins (TO6A to TO6D, TO7A to TO7D). In channels 6 and 7, when the corresponding bit is set in the timer start register (TSTR) and the free-running counter (TCNT) is started, the counter counts up until its value matches the corresponding cycle register (CYLR). When TCNT matches CYLR, it is cleared to H'0001 and starts counting up again from that value. At this time, 1 is output from the corresponding external pin. An interrupt request can be sent to the CPU by setting the corresponding bit in the timer interrupt enable register (TIER). If a value has been set in the duty register (DTR), when TCNT matches DTR, 0 is output to the corresponding external pin. If the DTR value is H'0000, the output does not change (0% duty). However, when H'0000 is set to DTR, do not directly write H'0000 to DTR. Set H'0000 to BFR and forward it from BFR to DTR. If H'0000 is directly set to DTR, duty may not be 0%. A duty of 100% is specified by setting DTR = CYLR. Do not set a value in DTR that will result in the condition DTR > CYLR. Channels 6 and 7 have buffers (BFR); the BFR value is transferred to DTR when TCNT matches CYLR. The duty value written into BFR is reflected in the output value in the cycle following that in which BFR is written to. An example of PWM timer operation is shown in figure 11.21. In the example in figure 11.21, H'0004 is set in channel 6 CYLR6A, and H'0002, H'0000 (0%), H'0004 (100%), and H'0001 in BFR6A. Rev.2.0, 07/03, page 366 of 960 Po TST6A TCNT6A Clock TCNT6A 0001 0002 0003 0004 0001 0002 0003 0004 0001 0002 0003 0004 0001 0002 0003 0004 0001 0002 0003 CYLR6A Data = 0000 Write to BFR6A 0004 Data = 0004 Data = 0001 BFR6A 0002 0000 0004 0001 DTR6A 0002 0000 0004 0001 TO6A * PWM output does not change for one cycle after activation Cleared by software Cleared by software Cleared by software TSR6 Cycle Cycle Cycle Duty = 0% Cycle Duty = 100% Cycle Note: * PWM output is not guaranteed because retained value is output for one cycle after activation. Figure 11.21 PWM Timer Operation Channel 6 can be used in complementary PWM mode by making a setting in the PWM mode control register (PMDR). On-duty or off-duty can also be selected with a setting in PMDR. When TCNT6 is started by a setting in TSTR, it starts counting up. When TCNT6 reaches the CYLR6 value, it starts counting down, and on reaching H'000, starts counting up again. The counter status is shown by TSR6. When TCNT6 underflows, an interrupt request can be sent to the CPU by setting the corresponding bit in TIER. When TCNT6 matches the duty register (DTR6) value, the output is inverted. The output prior to the match depends on the PMDR setting. When a value including dead time is set in DTR6, a maximum of 4-phase PWM output is possible. Data transfer from BFR6 to DTR6 is performed when TCNT6 underflows. An example of channel 6 complementary PWM mode operation is shown in figure 11.22. In the example in figure 11.22, H'0004 is set in channel 6 CYLR6A, and H'0002, H'0003, H'0004 (100%), and H'0000 (0%) in BFR6A. Rev.2.0, 07/03, page 367 of 960 P TST6A TCNT6A Clock TCNT6A 00 01 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 02 03 04 03 02 01 00 01 02 03 04 03 02 01 00 01 02 03 04 03 02 01 00 01 02 03 04 03 02 01 00 01 02 03 04 03 02 01 up TCNT6A up/down CYLR6A Data = 0003 Write to BFR6A down up down 0004 Data = 0004 Data = 0000 up down up down up down BFR6A 0002 0003 0004 0000 DTR6A ... 0002 0003 0004 0000 TO6A PWM output does not change for one cycle after activation Cleared by software TSR6 Cycle Cycle Cycle Cleared by software Cleared by software Cycle Duty = 100% Cycle Duty = 0% Figure 11.22 Complementary PWM Mode Operation 11.3.10 Channel 3 to 5 PWM Function PWM mode is selected for channels 3 to 5 by setting the corresponding bits to 1 in the timer mode register (TMDR), enabling the channels to operate as PWM timers with the same cycle. In PWM mode, general registers D (GR3D, GR4D, GR5D) are used as cycle registers, and general registers A to C (GR3A to GR3C, GR4A to GR4C, GR5A to GR5C) as duty registers. The external pins (TIO3A to TIO3C, TIO4A to TIO4C, TIO5A to TIO5C) corresponding to the GRs used as duty registers are used as PWM outputs. External pins TIO3D, TIO4D, and TIO5D should not be used as timer outputs. The free-running counter (TCNT) is started by making a setting in the timer start register (TSTR), and when TCNT reaches the cycle register (GR3D, GR4D, GR5D) value, a compare-match is generated and TCNT starts counting up again from H'0000. At the same time, the corresponding bit is set in the timer status register (TSR) and 1 is output from the corresponding external pin. When TCNT reaches the duty register (GR3A to GR3C, GR4A to GR4C, GR5A to GR5C) value, 0 is output to the external pin. The corresponding status flag is not set. When PWM operation is performed by starting the free-running counter from its initial value of H'0000, PWM output is not performed for one cycle. To perform immediate PWM output, the value in the cycle register must be set in the free-running counter before the counter is started. If PWM operation is performed Rev.2.0, 07/03, page 368 of 960 after setting H'FFFF in the cycle register, the cycle register's compare-match flag and overflow flag will be set simultaneously. Note that 0% or 100% duty output is not possible in channel 3 to 5 PWM mode. An example of channel 3 to 5 PWM mode operation is shown in figure 11.23. In the example in figure 11.23, H'0008 is set in GR3D, H'0002 is set in GR3A, GR3B, and GR3C, and channel 3 is activated; then, during operation, H'0000 is set in GR3A, GR3B, and GR3C, and output is performed to external pins TIOA3 to TIOC3. Note that 0% duty output is not possible even though H'0000 is set. Po TCNT3 Clock TCNT3 0008 0000 0001 0002 0003 0007 0008 0000 0001 0002 0003 0004 0005 GR3D 0008 0008 Rewritten by software GR3A-3C (pulse width) TIO3A- TIO3C 0002 0000 Cleared by software TSR3 Cleared by software Figure 11.23 Channel 3 to 5 PWM Mode Operation 11.3.11 Event Count Function and Event Cycle Measurement Channel 9 has six 8-bit event counters (ECNT9A to ECNT9F) and corresponding general registers (GR9A to GR9F). Each event counter has an external pin (TI9A to TI9F). Each ECNT9 operates unconditionally as an event counter. When an edge is input from the external pin, ECNT9 is incremented. When ECNT9 matches the value set in GR9, it is cleared, and then counts up when an edge is again input at the external pin. By making the appropriate setting in the interrupt enable register (TIER) beforehand, an interrupt request can be sent to the CPU on compare-match. For ECNT9A to ECNT9D, a trigger can be transmitted to channel 3 when a compare-match occurs. In channel 3, if the channel 9 trigger input is set in the timer I/O control register (TIOR) and the corresponding bit is set to 1 in the timer start register (TSTR), the TCNT3 value is captured in the corresponding general register (GR3A to GR3D) when an ECNT9A to ECNT9D compare-match occurs. This enables the event cycle to be measured. Rev.2.0, 07/03, page 369 of 960 An example of event count operation is shown in figure 11.24. In this example, ECNT9A counts up on both-edge, falling-edge, and rising-edge detection, H'10 is set in GR9A, and a comparematch is generated. An example of event cycle measurement operation is shown in figure 11.25. In this example, GR3A in channel 3 captures TCNT3 in response to a trigger from channel 9. Po TI9A Edge detection signal ECNT9A Clock ECNT9A 00 01 02 03 10 00 05 06 GR9A 10 TSR9 CMF9A Capture trigger To channel 3 Rising and falling edges Falling edge Cleared by software Rising edge Figure 11.24 Event Count Operation Po TCNT3 Clock TCNT3 Compare-match trigger (from channel 9) 0000 0001 0002 0003 0004 0005 5678 5679 567A 567B 567C 567D 567E GR3A 0003 567A TSR3 IMF3A Cleared by software Figure 11.25 Event Cycle Measurement Operation Rev.2.0, 07/03, page 370 of 960 11.3.12 Channel 10 Functions Inter-Edge Measurement Function and Edge Input Cessation Detection Function:32-bit input capture register 10A (ICR10A) and 32-bit output compare register 10A (OCR10A) in channel 10 unconditionally perform input capture and compare-match operations, respectively. These registers are connected to 32-bit free-running counter TCNT10A. When the corresponding bit is set in the timer start register (TSTR), the entire channel 10 starts operating. ICR10A has an external input pin (TI10), and when an edge is input at this input pin, ICR10A captures the TCNT10A value. At this time, TCNT10A is cleared to H'00000001. The captured value is transferred to the read register (RLD10C) in the multiplied clock generation block. By making the appropriate setting in the interrupt enable register (TIER), an interrupt request can be sent to the CPU. This allows inter-edge measurement to be carried out. When TCNT10A reaches the value set in OCR10A, a compare-match interrupt can be requested. In this way it is possible to detect the cessation of edge input beyond the time set in OCR10A. The input edge from TI10 is synchronized internally; the internal signal is AGCK. Noise cancellation is possible for edges input at TI10 using the timer 10H (TCNT10H) input cancellation function by setting the NCE bit in timer control register TCR10. When an edge is input at TI10, TCNT10H starts and input is disabled until it reaches compare-match register NCR10. Edge input operation without noise cancellation is shown in figure 11.26, edge input operation with noise cancellation in figure 11.27, and TCNT10A capture operation and compare-match operation in figure 11.28. Po TI10 After internal synchronization 1 After internal synchronization 2 AGCK AGCK operation TCNT clock When rising edge is set When falling edge is set When rising and falling edges are set Figure 11.26 Edge Input Operation (Without Noise Cancellation) Rev.2.0, 07/03, page 371 of 960 Po TI10 AGCK Noise cancellation period External edge mask period External edge mask period P x 10 (clock) 0 1 0 TCNT10H NCR10 AGCK operation TCNT clock 1 Note: When rising and falling edges are set Figure 11.27 Edge Input Operation (With Noise Cancellation) Po TSTR TST10 TCNT10A Clock 00000001 00000002 00000003 12345677 1234 5678 00000001 55555555 55555556 55555557 AGCK Capture transfer signal TCNT reset signal ICR10A 00000000 12345678 TSR10 IMF10A Cleared by software OCR10A 55555556 TSR10 CMF10A Cleared by software Figure 11.28 TCNT10A Capture Operation and Compare-Match Operation Internally synchronized AGCK is counted by event count 10B (TCNT10B), and when TCNT10B reaches the value set beforehand in compare-match register 10B (OCR10B), a compare-match occurs, and the compare-match trigger signal is transmitted to channel 0. By setting the corresponding bit in TIER, an interrupt request can be sent to the CPU. Rev.2.0, 07/03, page 372 of 960 Figure 11.29 shows TCNT10B compare-match operation. Po AGCK TCNT10B Clock 00 01 55 56 TCNT10B OCR10B 55 TSR10 CMF10B Cleared by software Channel 0 trigger Figure 11.29 TCNT10B Compare-Match Operation Multiplied Clock Generation Function: The channel 10 16-bit reload counter (TCNT10C, RLD10C) and 16-bit free-running counter 10G (TCNT10G) can be used to multiply the interval between edges input from external pin TI10 by 32, 64, 128, or 256. The value captured in ICR10A above is multiplied by 1/32, 1/64, 1/128, or 1/256 according to the value set in the timer I/O control register (TIOR10), and transferred to the reload buffer (RLD10C). At the same time, the same value is transferred to 16-bit reload counter 10C (TCNT10C) and a down-count operation is started. When this counter reaches H'0001, the value is read automatically from RLD10C and the down-count operation is repeated. When this reload occurs, a multiplied clock signal (AGCK1) is generated. AGCK1 is converted to a corrected clock (AGCKM) by the multiplied clock correction function described in the following section. Channel 10 can also perform compare-match operation by means of the multiplied clock (AGCK1) using general register 10G (GR10G) and 16-bit free-running counter 10G (TCNT10G). TCNT10G is incremented unconditionally by AGCK1. By making the appropriate setting in the interrupt enable register (TIER), an interrupt request can be sent to the CPU when TCNT10G and GR10G match. The timing of this interrupt can be selected with the IREG bit in TIER as either on occurrence of the compare-match or on input of the first TI10 edge after the compare-match. TCNT10C operation is shown in figure 11.30, and TCNT10G compare-match operation in figure 11.31. Rev.2.0, 07/03, page 373 of 960 Po TST10 AGCK ICR10A 1ck 00000000 00000020 1ck Shifter output 0000 Initial value set by software 0001 RLD10C 0002 0001 RLD10C write enable signal Not loaded when RLDEN = 1 TCNT10C 0001 0002 0001 0002 0001 0002 0001 0001 0001 0001 RLD10C load signal AGCK1 RLDEN RLDEN set to 1 by software RLDEN set to 0 by software Note: In case of multiplication factor of 32 Figure 11.30 TCNT10C Operation Po AGCK AGCK1 Write by software TCNT10G 0000 0001 0002 0034 0035 0036 Cleared by AGCK 0000 0001 GR10G 0034 TSR10 CMF10G When IREG = 1 TSR10 CMF10G When IREG = 0 Figure 11.31 TCNT10G Compare-Match Operation Rev.2.0, 07/03, page 374 of 960 Multiplied Clock Correction Function: Channel 10's three 16-bit correction counters (TCNT10D, TCNT10E, TCNT10F) and correction counter clear register (TCCLR10) have a correction function that makes the interval between edges input from TI10 the frequency multiplication value set in TIOR10. When AGCK is input, the value in TCNT10D multiplied by the multiplication factor set in TIOR10 is transferred to TCNT10E. At the same time, TCNT10D is incremented. TCNT10E counts up on AGCK1. TCNT10E loads TCNT10D on AGCK, and counts up again on AGCK1. Using the counter correction select bit (CCS) in TIOR10, it is possible to select whether or not TCNT10E is halted when TCNT10D = TCNT10E. TCNT10F has the peripheral clock (P) as its input and is constantly compared with TCNT10E. When the TCNT10F value is smaller than that in TCNT10E, TCNT10F is incremented and outputs a corrected multiplied clock signal (AGCKM). When the TCNT10E value exceeds the TCNT10F value (when TCNT10E loads TCNT10D), no count-up operation is performed. AGCKM is output to the channel 1 to 5 free-running counters (TCNT1 to TCNT5). Channel 10 also has a correction counter clear register (TCCLR10). The correction counters (TCNT10D, TCNT10E, TCNT10F) and channel 1 and 2 free-running counters (TCNT1 and TCNT2) can be cleared when TCNT10F reaches the value set in TCCLR10. TCNT10D operation is shown in figure 11.32, TCNT10E operation in figure 11.33, TCNT10F operation (at startup) in figure 11.34, TCNT10F operation (end of cycle, acceleration, deceleration) in figure 11.35, and TCNT10F operation (end of cycle, steady-state) in figure 11.36. Po TST10 AGCK TCNT10D Clock TCNT10D 00 01 02 03 Shifter output 0000 0020 0040 0060 Note: In case of multiplication factor of 32 Figure 11.32 TCNT10D Operation Rev.2.0, 07/03, page 375 of 960 Po TST10 AGCK AGCK1 Initial value load 0024 00 00 0001 0002 0003 0004 0022 0023 0020 0021 0022 0038 0039 0040 00 41 00 42 00 43 00 44 Corrected value load Corrected value load TCNT10E valid TCNT10E TCNT10D (shift amount) 0000 0020 0040 0060 Note: In case of multiplication factor of 32 Figure 11.33 TCNT10E Operation Po TST10 AGCK TCNT10E Clock 0000 TCNT10E 0001 0002 0003 0004 0022 0024 0023 0020 0021 0022 0023 0024 0025 0026 0027 TCNT10F 0080 0001 0002 0003 0004 0022 0023 0024 0025 0026 0027 Same value as cycle register set by software AGCKM TCNT clock operating on AGCKM TCNT1, TCNT2 TCNT1, TCNT2 reset trigger 0000 0001 0002 0003 0022 0023 0024 0025 0026 TCNT10D 00 01 02 Note: Multiplication factor of 32, TCCLR10 = H'0080 Figure 11.34 TCNT10F Operation (At Startup) Rev.2.0, 07/03, page 376 of 960 Po TST10 AGCK TCNT10E Clock 00 00 TCNT10E 005A 0060 0061 0062 0063 0064 0065 0066 0076 0077 0078 0079 007A 0001 0080 0002 0003 TCNT10F 005A 0063 0064 0065 0066 0076 0077 0078 0079 007A 00 01 0002 0003 AGCKM TCNT clock operating on AGCKM TCNT1, TCNT2 TCNT1, TCNT2 reset trigger Cleared to H'00 by software 0063 0064 0065 00 66 0076 0077 0078 0079 007A 00 0002 01 0000 0003 TCNT10D 02 03 00 01 Note: Multiplication factor of 32, TCCLR10 = H'0080 Figure 11.35 TCNT10F Operation (End of Cycle, Acceleration, Deceleration) Rev.2.0, 07/03, page 377 of 960 Po TST10 AGCK TCNT10E Clock 00 00 TCNT10E 005A 0060 0061 0062 0063 0064 0065 0066 007E 007F 0080 0081 0082 0001 0002 0003 TCNT10F 005A 0063 0064 0065 0066 007E 007F 0080 0001 0002 0003 AGCKM TCNT clock operating on AGCKM TCNT1, TCNT2 00 66 005A 0063 0064 0065 007E 007F 0000 0001 0002 TCNT1, TCNT2 reset trigger Set to H'00 by software TCNT10D 02 03 00 01 Note: Multiplication factor of 32, TCCLR10 = H'0080 Figure 11.36 TCNT10F Operation (End of Cycle, Steady-State) Rev.2.0, 07/03, page 378 of 960 11.4 Interrupts The ATU has 75 interrupt sources of five kinds: input capture interrupts, compare-match interrupts, overflow interrupts, underflow interrupts, and interval interrupts. 11.4.1 Status Flag Setting Timing IMF (ICF) Setting Timing in Input Capture: When an input capture signal is generated, the IMF bit and ICF bit are set to 1 in the timer status register (TSR), and the TCNT value is simultaneously transferred to the corresponding GR, ICR, and OSBR. The timing in this case is shown in figure 11.37. In the example in figure 11.37, a signal is input from an external pin, and input capture is performed on detection of a rising edge. CK tTICS (input capture input setup time) Input capture input Internal input capture signal TCNT N GR (ICR) Interrupt status flag IMF (ICF) Interrupt request signal IMI (ICI) N Figure 11.37 IMF (ICF) Setting Timing in Input Capture Rev.2.0, 07/03, page 379 of 960 IMF (ICF) Setting Timing in Compare-Match: The IMF bit and CMF bit are set to 1 in the timer status register (TSR) by the compare-match signal generated when the general register (GR) output compare register (OCR), or cycle register (CYLR) value matches the timer counter (TCNT) value. The compare-match signal is generated in the last state of the match (when the matched TCNT count value is updated). The timing in this case is shown in figure 11.38. CK TCNT input clock TCNT N N+1 GR (OCR, CYLR) N Compare-match signal Interrupt status flag IMF (CMF) Interrupt request signal IMI (CMI) Figure 11.38 IMF (CMF) Setting Timing in Compare-Match Rev.2.0, 07/03, page 380 of 960 OVF Setting Timing in Overflow: When TCNT overflows (from H'FFFF to H'0000, or from H'FFFFFFFF to H'00000000), the OVF bit is set to 1 in the timer status register (TSR). The timing in this case is shown in figure 11.39. CK TCNT input clock TCNT H'FFFF H'0000 Overflow signal Interrupt status flag OVF Interrupt request signal OVI Figure 11.39 OVF Setting Timing in Overflow Rev.2.0, 07/03, page 381 of 960 OSF Setting Timing in Underflow: When a down-counter (DCNT) counts down from H'0001 to H'0000 on DCNT input clock input, the OSF bit is set to 1 in the timer status register (TSR) when the next DCNT input clock pulse is input (when underflow occurs). However, when DCNT is H'0000, it remains unchanged at H'0000 no matter how many DCNT input clock pulses are input. When DCNT is cleared by means of the one-shot pulse function, the OSF bit is cleared when the next DCNT input clock is input. The timing in this case is shown in figure 11.40. CK DCNT input clock DCNT H'0001 H'0000 H'0000 Underflow signal Interrupt status flag OSF Interrupt request signal OSI Figure 11.40 OSF Setting Timing in Underflow Rev.2.0, 07/03, page 382 of 960 Timing of IIF Setting by Interval Timer: When 1 is generated by ANDing the rise of bit 10-13 in free-running counter TCNT0L with bit ITVE0-ITVE3 in the interval interrupt request register (ITVRR), the IIF bit is set to 1 in the timer status register (TSR). The timing in this case is shown in figure 11.41. TCNT0 value N in the figure is the counter value when TCNT0L bit 6-13 changes to 1. (For example, N = H'00000400 in the case of bit 10, H'00000800 in the case of bit 11, etc.) CK TCNT input clock TCNT0 N-1 N Internal interval signal Interrupt status flag IIF Interrupt request signal Figure 11.41 Timing of IIF Setting Timing by Interval Timer Rev.2.0, 07/03, page 383 of 960 11.4.2 Status Flag Clearing Clearing by CPU Program: The interrupt status flag is cleared when the CPU writes 0 to the flag after reading it while set to 1. The procedure and timing in this case are shown in figure 11.42. TSR write cycle T1 T2 CK Read 1 from TSR Address TSR address Start Write 0 to TSR Internal write signal Interrupt status flag IMF, ICF, CMF, OVF, OSF, IIF Interrupt request signal Interrupt status flag cleared Figure 11.42 Procedure and Timing for Clearing by CPU Program Rev.2.0, 07/03, page 384 of 960 Clearing by DMAC: The interrupt status flag (ICF0A to ICF0D, CMF6A to CMF6D, CMF7A to CMF7D) is cleared automatically during data transfer when the DMAC is activated by input capture or compare-match. The procedure and timing in this case are shown in figure 11.43. CK Start Clear request signal from DMAC Interrupt status flag clear signal Interrupt status flag ICF0B, CMF6 Interrupt request signal Activate DMAC Interrupt status flag cleared during data transfer Figure 11.43 Procedure and Timing for Clearing by DMAC Rev.2.0, 07/03, page 385 of 960 11.5 11.5.1 CPU Interface Registers Requiring 32-Bit Access Free-running counters 0 and 10A (TCNT0, TCNT10A), input capture registers 0A to 0D and 10A (ICR0A to ICR0D, ICR10A), and output compare register 10A (OCR10A) are 32-bit registers. As these registers are connected to the CPU via an internal 16-bit data bus, a read or write (read only, in the case of ICR0A to ICR0D and ICR10A) is automatically divided into two 16-bit accesses. Figure 11.44 shows a read from TCNT0, and figure 11.45 a write to TCNT0. When reading TCNT0, in the first read the TCNT0H (upper 16-bit) value is output to the internal data bus, and at the same time, the TCNT0L (lower 16-bit) value is output to an internal buffer register. Then, in the second read, the TCNT0L (lower 16-bit) value held in the internal buffer register is output to the internal data bus. When writing to TCNT0, in the first write the upper 16 bits are output to an internal buffer register. Then, in the second write, the lower 16 bits are output to TCNT0L, and at the same time, the upper 16 bits held in the internal buffer register are output to TCNT0H to complete the write. The above method performs simultaneous reading and simultaneous writing of 32-bit data, preventing contention with an up-count. 1st read operation Bus interface Module data bus H TCNT0H Internal buffer register L TCNT0L Module data bus Internal data bus H CPU Internal data bus L CPU 2nd read operation Bus interface Module data bus L Internal buffer register TCNT0H TCNT0L Figure 11.44 Read from TCNT0 Rev.2.0, 07/03, page 386 of 960 1st write operation Internal data bus H CPU Bus interface H Module data bus Internal buffer register TCNT0H TCNT0L Internal data bus L CPU 2nd write operation Bus interface L Module data bus Internal buffer H register TCNT0H TCNT0L Module data bus Figure 11.45 Write to TCNT0 Rev.2.0, 07/03, page 387 of 960 11.5.2 Registers Permitting 8-Bit, 16-Bit, or 32-Bit Access Timer registers 1, 2, and 3 (TSTR1, TSTR2, TSTR3) are 8-bit registers. As these registers are connected to the CPU via an internal 16-bit data bus, a simultaneous 32-bit read or write access to TSTR1, TSTR2, and TSTR3 is automatically divided into two 16-bit accesses. Figure 11.46 shows a read from TSTR, and figure 11.47 a write to TSTR. When reading TSTR, in the first read the TSTR1 and TSTR2 (upper 16-bit) value is output to the internal data bus. Then, in the second read, the TSTR3 (lower 16-bit) value is output to the internal data bus. When writing to TSTR, in the first write the upper 16 bits are written to TSTR1 and TSTR2. Then, in the second write, the lower 16 bits are written to TSTR3. Note that, with the above method, in a 32-bit write the write timing is not the same for TSTR1/TSTR2 and TSTR3. For information on 8-bit and 16-bit access, see section 11.5.4, 8-Bit or 16-Bit Accessible Registers. 1st read operation Bus interface Module data bus H TSTR2 TSTR1 TSTR3 Internal data bus H CPU Internal data bus L CPU 2nd read operation Bus interface Module data bus L TSTR2 TSTR1 TSTR3 Figure 11.46 Read from TSTR1, TSTR2, and TSTR3 Rev.2.0, 07/03, page 388 of 960 1st write operation Internal data bus H CPU Bus interface H Module data bus TSTR2 TSTR1 TSTR3 Internal data bus L CPU 2nd write operation Bus interface L TSTR2 TSTR1 TSTR3 Module data bus Figure 11.47 Write to TSTR1, TSTR2, and TSTR3 11.5.3 Registers Requiring 16-Bit Access The free-running counters (TCNT; but excluding TCNT0, TCNT10A, TCNT10B, TCNT10D, and TCNT10H), the general registers (GR; but excluding GR9A to GR9D), down-counters (DCNT), offset base register (OSBR), cycle registers (CYLR), buffer registers (BFR), duty registers (DTR), timer connection register (TCNR), one-shot pulse terminate register (OTR), down-count start register (DSTR), output compare registers (OCR: but excluding OCR10B), reload registers (RLDR8, RLD10C), correction counter clear register (TCCLR10), timer interrupt enable register (TIER), and timer status register (TSR) are 16-bit registers. These registers are connected to the CPU via an internal 16-bit data bus, and can be read or written (read only, in the case of OSBR) a word at a time. Figure 11.48 shows the operation when performing a word read or write access to TCNT1A. Internal data bus CPU Bus interface Module data bus TCNT1A Figure 11.48 TCNT1A Read/Write Operation Rev.2.0, 07/03, page 389 of 960 11.5.4 8-Bit or 16-Bit Accessible Registers The timer control registers (TCR1A, TCR1B, TCR2A, TCR2B, TCR6A, TCR6B, TCR7A, TCR7B), timer I/O control registers (TIOR1A to TIOR1D, TIOR2A to TIOR2D, TIOR3A, TIOR3B, TIOR4A, TIOR4B, TIOR5A, TIOR5B), and the timer start register (TSTR1, TSTR2, TSTR3) are 8-bit registers. These registers are connected to the upper 8 bits or lower 8 bits of the internal 16-bit data bus, and can be read or written a byte at a time. In addition, a pair of 8-bit registers for which only the least significant bit of the address is different, such as timer I/O control register 1A (TIOR1A) and timer I/O control register 1B (TIOR1B), can be read or written in combination a word at a time. Figures 11.49 and 11.50 show the operation when performing individual byte read or write accesses to TIOR1A and TIOR1B. Figure 11.51 shows the operation when performing a word read or write access to TIOR1A and TIOR1B simultaneously. Internal data bus CPU Only upper 8 bits used Module data bus Only upper 8 bits used Bus interface TIOR1B TIOR1A Figure 11.49 Byte Read/Write Access to TIOR1B Internal data bus CPU Only lower 8 bits used Module data bus Only lower 8 bits used Bus interface TIOR1B TIOR1A Figure 11.50 Byte Read/Write Access to TIOR1A Internal data bus CPU Module data bus Bus interface TIOR1B TIOR1A Figure 11.51 Word Read/Write Access to TIOR1A and TIOR1B Rev.2.0, 07/03, page 390 of 960 11.5.5 Registers Requiring 8-Bit Access The timer mode register (TMDR), prescaler register (PSCR), timer I/O control registers (TIOR0, TIOR10, TIOR11), trigger mode register (TRGMDR), interval interrupt request register (ITVRR), timer control registers (TCR3, TCR4, TCR5, TCR8, TCR9A to TCR9C, TCR10, TCR11), PWM mode register (PMDR), reload enable register (RLDENR), free-running counters (TCNT10B, TCNT10D, TCNT10H), event counter (ECNT), general registers (GR9A to GR9F), output compare register (OCR10B), and noise canceler register (NCR) are 8-bit registers. These registers are connected to the upper 8 bits of the internal 16-bit data bus, and can be read or written a byte at a time. Figure 11.52 shows the operation when performing individual byte read or write accesses to ITVRR1. Internal data bus CPU Only upper 8 bits used Module data bus Only upper 8 bits used Bus interface ITVRR1 Figure 11.52 Byte Read/Write Access to ITVRR1 11.6 Sample Setup Procedures Sample setup procedures for activating the various ATU-II functions are shown below. Sample Setup Procedure for Input Capture: An example of the setup procedure for input capture is shown in figure 11.53. 1. Select the first-stage counter clock o' in prescaler register (PSCR) and the second-stage counter clock o" with the CKSEL bit in the timer control register (TCR). When selecting an external clock, also select the external clock edge type with the CKEG bit in TCR. 2. Set the port control register, corresponding to the port for signal input as the input capture trigger, to ATU input capture input. 3. Select rising edge, falling edge, or both edges as the input capture signal input edge(s) with the timer I/O control register (TIOR). If necessary, a timer interrupt request can be sent to the CPU on input capture by making the appropriate setting in the interrupt enable register (TIER). In channel 0, setting the DMAC allows DMAC activation to be performed. 4. Set the corresponding bit to 1 in the timer start register (TSTR) to start the free-running counter (TCNT) for the relevant channel. Note: When input capture occurs, the counter value is always captured, irrespective of freerunning counter (TCNT) activation. Rev.2.0, 07/03, page 391 of 960 Start Select counter clock 1 Set port-ATU-II connection 2 Set input waveform edge detection 3 Start counter 4 Input capture operation Figure 11.53 Sample Setup Procedure for Input Capture Sample Setup Procedure for Waveform Output by Output Compare-Match: An example of the setup procedure for waveform output by output compare-match is shown in figure 11.54. 1. Select the first-stage counter clock o' in prescaler register (PSCR), and the second-stage counter clock o" with the CKSEL bit in the timer control register (TCR). When selecting an external clock, also select the external clock edge type with the CKEG bit in TCR. 2. Set the port control register corresponding to the waveform output port to ATU output compare-match output. Also set the corresponding bit to 1 in the port IO register to specify the output attribute for the port. 3. Select 0, 1, or toggle output for output compare-match output with the timer I/O control register (TIOR). If necessary, a timer interrupt request can be sent to the CPU on output compare-match by making the appropriate setting in the interrupt enable register (TIER). 4. Set the timing for compare-match generation in the ATU general register (GR) corresponding to the port set in 2. 5. Set the corresponding bit to 1 in the timer start register (TSTR) to start the free-running counter (TCNT). Waveform output is performed from the relevant port when the TCNT value and GR value match. Rev.2.0, 07/03, page 392 of 960 Start Select counter clock 1 Set port-ATU-II connection 2 Select waveform output mode 3 Set output timing 4 Start counter 5 Waveform output Figure 11.54 Sample Setup Procedure for Waveform Output by Output Compare-Match Rev.2.0, 07/03, page 393 of 960 Sample Setup Procedure for Channel 0 Input Capture Triggered by Channel 10 CompareMatch: An example of the setup procedure for compare-match signal transmission is shown in figure 11.55. 1. Set the timing for compare-match generation in the channel 10 output compare register (OCR10B). 2. Set the TRG0DEN bit to 1 in the channel 10 timer control register (TCR10). 3. Set the corresponding bit to 1 in the timer start register (TSTR) to start the channel 10 freerunning counter (TCNT10B). On compare-match between TCNT10 and OCR10B, the compare-match signal is transmitted to channel 0 as the channel 0 ICR0D input capture signal. Start Set compare-match 1 Set TCR10 2 Start counter 3 Signal transmission Figure 11.55 Sample Setup Procedure for Compare-Match Signal Transmission Rev.2.0, 07/03, page 394 of 960 Sample Setup Procedure for One-Shot pulse Output: An example of the setup procedure for one-shot pulse output is shown in figure 11.56. 1. Set the first-stage counter clock o' in prescaler register 1 (PSCR1), and select the second-stage counter clock o" with the CKSEL bit in timer control register8 TCR8. 2. Set port K control registers H and L (PKCRH, PKCRL) corresponding to the waveform output port to ATU one-shot pulse output. Also set the corresponding bit to 1 in the port K IO register (PKIOR) to specify the output attribute. 3. Set the one-shot pulse width in the down-counter (DCNT) corresponding to the port set in (2). If necessary, a timer interrupt request can be sent to the CPU when the down-counter underflows by making the appropriate setting in the interrupt enable register (TIER8). 4. Set the corresponding bit (DST8A to DST8P) to 1 in the down-count start register (DSTR) to start the down-counter (DCNT). Start Select counter clock 1 Set port-ATU-II connection 2 Set pulse width 3 Start down-count 4 One-shot pulse output Figure 11.56 Sample Setup Procedure for One-Shot Pulse Output Rev.2.0, 07/03, page 395 of 960 Sample Setup Procedure for Offset One-Shot Pulse Output/Cutoff Operation: An example of the setup procedure for offset one-shot pulse output is shown in figure 11.57. 1. Set the first-stage counter clock o' in prescaler register 1 (PSCR1), and select the second-stage counter clock o" with the CKSEL bit in the timer control register (TCR1, TCR2, TCR8). 2. Set port K control registers H and L (PKCRH, PKCRL) corresponding to the waveform output port to ATU one-shot pulse output. Also set the corresponding bit to 1 in the port K IO register (PKIOR) to specify the output attribute 3. Set the one-shot pulse width in the down-counter (DCNT) corresponding to the port set in (2). If necessary, a timer interrupt request can be sent to the CPU when the down-counter underflows by making the appropriate setting in the interrupt enable register (TIER8). 4. Set the offset width in the channel 1 or 2 general register (GR1A--GR1H, GR2A--GR2H) connected to the down-counter (DCNT) corresponding to the port set in (2), and in the output compare register (OCR1, OCR2A--OCR2H). Set the timer I/O control register (TIOR1A-- TIOR1D, TIOR2A--TIOR2D) to the compare-match enabled state. 5. Set the start/terminate trigger by means of the trigger mode register (TRGMDR), timer connection register (TCNR), and one-shot pulse terminate register (OTR), so that it corresponds to the port set in step 2 above. 6. Set the corresponding bit to 1 in the timer start register (TSTR) to start the channel 1 or 2 freerunning counter (TCNT1, TCNT2). When the TCNT value and GR value or OCR value match, the corresponding DCNT starts counting down or is forcibly cleared, and one-shot pulse output is performed. Rev.2.0, 07/03, page 396 of 960 Start Select counter clock 1 Set port-ATU-II connection 2 Set pulse width 3 Set offset width 4 Set offset operation 5 Start count 6 Offset one-shot pulse output Figure 11.57 Sample Setup Procedure for Offset One-Shot Pulse Output Rev.2.0, 07/03, page 397 of 960 Sample Setup Procedure for Interval Timer Operation: An example of the setup procedure for interval timer operation is shown in figure 11.58. 1. Set the first-stage counter clock o' in prescaler register 1 (PSCR1). 2. Set the ITVE bit to be used in the interval interrupt request register (ITVRR) to 1. An interrupt request can be sent to the CPU when the corresponding bit changes to 1 in the channel 0 freerunning counter (TCNT0). To start A/D converter sampling, set the ITVA bit to be used in ITVRR to 1. 3. Set bit 0 to 1 in the timer start register (TSTR) to start TCNT0. Start Select counter clock 1 Set interval 2 Start counter 3 Interrupt request to CPU or start of A/D sampling Figure 11.58 Sample Setup Procedure for Interval Timer Operation Rev.2.0, 07/03, page 398 of 960 Sample Setup Procedure for PWM Timer Operation (Channels 3 to 5 ): An example of the setup procedure for PWM timer operation (channels 3 to 5 ) is shown in figure 11.59. 1. Set the first-stage counter clock o' in prescaler register 1 (PSCR1), and select the second-stage counter clock o" with the CKSEL bit in the timer control register (TCR). When selecting an external clock, at the same time select the external clock edge type with the CKEG bit in TCR. 2. Set the port control registers (PxCRH, PxCRL) corresponding to the waveform output port to ATU output compare-match output. Also set the corresponding bit to 1 in the port IO register (PxIOR) to specify the output attribute. 3. Set bit T3PWM-T5PWM in the timer mode register (TMDR) to PWM mode. When PWM mode is set, the timer operates in PWM mode irrespective of the timer I/O control register (TIOR) contents, and general registers (GR3A to GR3D, GR4A to GR4D, GR5A to GR5D) can be written to. 4. The GR3A-GR3C, GR4A-GR4C, and GR5A-GR5C ATU general registers are used as duty registers (DTR), and the GR3D, GR4D, and GR5D ATU general registers as cycle registers (CYLR). Set the PWM waveform output 0 output timing in DTR, and the PWM waveform output 1 output timing in CYLR. Also, if necessary, interrupt requests can be sent to the CPU at the 0/1 output timing by making a setting in the timer interrupt enable register (TIER). 5. Set the corresponding bit to 1 in the timer start register (TSTR) to start the free-running counter (TCNT) for the relevant channel. Rev.2.0, 07/03, page 399 of 960 Start Select counter clock 1 Set port-ATU-II connection 2 Set PWM timer 3 Set GR 4 Start count 5 PWM waveform output Figure 11.59 Sample Setup Procedure for PWM Timer Operation (Channels 3 to 5) Rev.2.0, 07/03, page 400 of 960 Sample Setup Procedure for PWM Timer Operation (Channels 6 and 7): An example of the setup procedure for PWM timer operation (channels 6 and 7) is shown in figure 11.60. 1. Set the first-stage counter clock o' in prescaler register 2 and 3 (PSCR2, PSCR3), and select the second-stage counter clock o" with the CKSEL bit in the timer control register (TCR6A, TCR6B, TCR7A, TCR7B). 2. Set the port B control register L (PBCRL) corresponding to the waveform output port to ATU PWM output. Also set the corresponding bit to 1 in the port B IO register (PBIOR) to specify the output attribute. 3. Set PWM waveform output 1 output timing in the cycle register (CYLR6A to CYLR6D, CYLR7A to CYLR7D), and set the PWM waveform output 0 output timing in the buffer register (BFR6A to BFR6D, BFR7A to BFR7D) and duty register (DTR6A to DTR6D, DTR7A to DTR7D). If necessary, an interrupt request can be sent to the CPU on a comparematch between the CYLR value and the free-running counter (TCNT) value by making the appropriate setting in the interrupt enable register (TIERE). In addition, setting the DMAC allows DMAC activation to be performed. 4. Set the corresponding bit to 1 in the timer start register (TSTR) to start the TCNT counter for the relevant channel. Notes: 1. Do not make a setting in DTR after the counter is started. Use BFR to make a DTR setting. 2. 0% duty is specified by setting H'0000 in the duty register (DTR), and 100% duty is specified by setting buffer register (BFR) = cycle register (CYLR). Do not set BFR > CYLR. Rev.2.0, 07/03, page 401 of 960 Start Select counter clock 1 Set port-ATU-II connection 2 Set CYLR, BFR, DTR 3 Start count 4 PWM waveform output Figure 11.60 Sample Setup Procedure for PWM Timer Operation (Channels 6 and 7) Sample Setup Procedure for Event Counter Operation: An example of the setup procedure for event counter operation is shown in figure 11.61. 1. Set the number of events to be counted in a general register (GR9A to GR9D). Also, if necessary, an interrupt request can be sent to the CPU upon compare-match by making a setting in the timer interrupt enable register (TIER). 2. Set the port control register, corresponding to the port for signal input to the event counter, to ATU event counter input. 3. Select the event counter count edge with the EGSEL bits in the channel 9 timer control register (TCR9A to TCR9C). 4. Input a signal to the event counter input pin. Rev.2.0, 07/03, page 402 of 960 Start Set number of events 1 Set port-ATU-II connection 2 Select counter clock 3 Start event input 4 Event counter operation Figure 11.61 Sample Setup Procedure for Event Counter Operation Rev.2.0, 07/03, page 403 of 960 Sample Setup Procedure for Channel 3 Input Capture Triggered by Channel 9 CompareMatch: An example of the setup procedure for compare-match signal transmission is shown in figure 11.62. 1. Set the port control register, corresponding to the port for signal input to the event counter, to ATU event counter input. 2. Set the channel 3 timer I/O control register (TIOR3A, TIOR3B), and select the input capture disable setting for the general registers (GR3A to GR3D). Input from pins TIO3A to TIO3D is masked. 3. Select the event counter count edge with the EGSEL bits in the channel 9 timer control register (TCR9A, TCR9B), and set the TRG3xEN bit to 1. Set the timing for capture in the general register (GR9A to GR9D). 4. Set bit STR3 to 1 in the timer start register (TSTR) to start the channel 3 free-running counter (TCNT3). 5. Input a signal to the event counter input pin. Note: An interrupt request can be sent to the CPU upon channel 9 compare-match by making a setting in the timer interrupt enable register (TIER), but an interrupt request cannot be sent to the CPU upon channel 3 input capture. Start Set port-ATU-II commection 1 Set input capture 2 Select compare-match 3 Start counter 4 Start event input 5 Input capture operation Figure 11.62 Sample Setup Procedure for Compare-Match Signal Transmission Rev.2.0, 07/03, page 404 of 960 Sample Setup Procedure for Channel 10 Missing-Teeth Detection: An example of the setup procedure for missing-teeth detection is shown in figure 11.63. 1. Set port B control register H (PBCRH) or port L control register L (PLCRL), corresponding to the port for input of the external signal (missing-teeth signal), to ATU edge input (TI10). 2. Set 1st-stage counter clock o' in prescaler register 4 (PSCR4). Set the external input (TI10) cycle multiplication factor with the PIM bits in timer I/O control register 10 (TIOR10), and enable reload register 10C (RLD10C) updating with the RLDEN bit. Select the external input edge type with the CKEG bits in timer control register 10 (TCR10). 3. Set general register 10G (GR10G) to the compare-match function with bit IO10G in TIOR10. Also, an interrupt request can be sent to the CPU upon compare-match by making a setting in interrupt enable register 10 (TIER10). 4. Set the timing for compare-match generation in GR10G according to the multiplication factor and number of missing-teeths in the missing-teeth interval set in step 1. 5. Set the corresponding bit to 1 in timer start register 1 (TSTR1) to start the channel 10 count. A compare-match occurs when the values in free-running counter 10G (TCNT10G) and GR10G match. Note: The TCNT10G counter clock is generated according to the external input edge interval and multiplication factor selected in step 1, and the counter is cleared to H'0000 by an external input edge. Start Set port-ATU-II connection 1 Select counter clock 2 Set compare-match 3 Set missing-teeth timing 4 Start counter 5 Interrupt requests to CPU Figure 11.63 Sample Setup Procedure for Missing-Teeth Detection Rev.2.0, 07/03, page 405 of 960 11.7 Usage Notes Note that the kinds of operation and contention described below occur during ATU operation. Contention between TCNT Write and Clearing by Compare-Match: With channel 3 to 7 freerunning counters (TCNT3 to TCNT5, TCNT6A to TCNT6D, TCNT7A to TCNT7D), if a compare-match occurs in the T2 state of a CPU write cycle when counter clearing by comparematch has been set, or when PWM mode is used, the write to TCNT has priority and TCNT clearing is not performed. The compare-match remains valid, and writing of 1 to the interrupt status flag and waveform output to an external destination are performed in the same way as for a normal compare-match. The timing in this case is shown in figure 11.64. T1 Po Address TCNT address T2 Internal write signal Compare-match signal Counter clear signal TCNT CPU write value Interrupt status flag External output signal (1 output) Figure 11.64 Contention between TCNT Write and Clear Rev.2.0, 07/03, page 406 of 960 Contention between TCNT Write and Increment: If a write to a channel 0 to 11 free-running counter (TCNT0, TCNT1A, TCNT1B, TCNT2A, TCNT2B, TCNT3 to TCNT5, TCNT6A to TCNT6D, TCNT7A to TCNT7D, TCNT10A to TCNT10H, TCNT11), down-counter (DCNT8A to DCNT8P), or event counter 9 (ECNT9A to ECNT9F) is performed while that counter is counting up or down, the write to the counter has priority and the counter is not incremented or decremented. The timing in this case is shown in figure 11.65. In this example, the CPU writes H'5555 at the point at which TCNT is to be incremented from H'1001 to H'1002. T1 Po T2 TCNT input clock Address TCNT address Internal write signal TCNT 1001 5555 (CPU write value) 5556 Figure 11.65 Contention between TCNT Write and Increment Rev.2.0, 07/03, page 407 of 960 Contention between TCNT Write and Counter Clearing by Overflow: With channel 0 to 5 and 11 free-running counters (TCNT0, TCNT1A, TCNT1B, TCNT2A, TCNT2B, TCNT3 to TCNT5, TCNT11), if overflow occurs in the T2 state of a CPU write cycle, the write to TCNT has priority and TCNT is not cleared. Writing of 1 to the interrupt status flag (OVF) due to the overflow is performed in the same way as for normal overflow. The timing in this case is shown in figure 11.66. In this example, H'5555 is written at the point at which TCNT overflows. T1 Po T2 TCNT input clock Address TCNT address Internal write signal Overflow signal TCNT FFFF 5555 (CPU write value) 5556 Interrupt status flag (OVF) Figure 11.66 Contention between TCNT Write and Overflow Rev.2.0, 07/03, page 408 of 960 Contention between Interrupt Status Flag Setting by Interrupt Generation and Clearing: If an event such as input capture/compare-match or overflow/underflow occurs in the T2 state of an interrupt status flag 0 write cycle by the CPU, clearing by the 0 write has priority and the interrupt status flag is cleared. The timing in this case is shown in figure 11.67. TSR write cycle T2 T1 Po Address TSR address 0 written to TSR N N+1 Internal write signal TCNT GR N Compare-match signal Interrupt status flag IMF Figure 11.67 Contention between Interrupt Status Flag Setting by Compare-Match and Clearing Rev.2.0, 07/03, page 409 of 960 Contention between DTR Write and BFR Value transfer by Buffer Function: In channels 6 and 7, if there is contention between transfer of the buffer register (BFR) value to the corresponding duty register (DTR) due to a cycle register (CYLR) compare-match, and a write to DTR by the CPU, the CPU write value is written to DTR. Figure 11.68 shows an example in which contention arises when the BFR value is H'AAAA and the value to be written to DTR is H'5555. Po Address Internal write signal DTR address H'5555 written to DTR Compare-match signal BFR H'AAAA DTR H'5555 Figure 11.68 Contention between DTR Write and BFR Value Transfer by Buffer Function Rev.2.0, 07/03, page 410 of 960 Contention between Interrupt Status Flag Clearing by DMAC and Setting by Input Capture/Compare-Match: If a clear request signal is generated by the DMAC when the interrupt status flag (ICF0A to ICF0D, CMF6A to CMF6D, CMF7A to CMF7D) is set by input capture (ICR0A to ICR0D) or compare-match (CYLR6A to CYLR6D, CYLR7A to CYLR7D), clearing by the DMAC has priority and the interrupt status flag is not set. The timing in this case is shown in figure 11.69. Po DMAC clear request signal Interrupt status flag clear signal Input capture/ compare-match signal Interrupt status flag ICF0A to ICF0D, CMF6A to CMF6D, CMF7A to CMF7D Figure 11.69 Contention between Interrupt Status Flag Clearing by DMAC and Setting by Input Capture/Compare-Match Rev.2.0, 07/03, page 411 of 960 Halting of a Down-Counter by the CPU: A down-counter (DCNT) can be halted by writing H'0000 to it. The CPU cannot write 0 directly to the down-count start register (DSTR); instead, by setting DCNT to H'0000, the corresponding DSTR bit is cleared to 0 and the count is stopped. However, the OSF bit in the timer status register (TSR) is set when DCNT underflows. Note that when H'0000 is written to DCNT, the corresponding DSTR bit is not cleared to 0 immediately; it is cleared to 0, and the down-counter is stopped, when underflow occurs following the H'0000 write. The timing in this case is shown in figure 11.70. Po DCNT input clock DCNT N H'0000 written to DCNT H'0000 H'0000 Internal write signal DSTR TSR Port output (one-shot pulse) Figure 11.70 Halting of a Down-Counter by the CPU Rev.2.0, 07/03, page 412 of 960 Input Capture Operation when Free-Running Counter is Halted: In channels 0 to 5, channel 10, or channel 11, if input capture setting is performed and a trigger signal is input from the input pin, the TCNT value will be transferred to the corresponding general register (GR) or input capture register (ICR) irrespective of whether the free-running counter (TCNT) is running or halted, and the IMF or ICF bit will be set in the timer status register (TSR). The timing in this case is shown in figure 11.71. Po Timer status register TSR Internal input capture signal TCNT N GR (ICR) Interrupt status flag IMF (ICF) N Figure 11.71 Input Capture Operation before Free-Running Counter is Started Rev.2.0, 07/03, page 413 of 960 Contention between DCNT Write and Counter Clearing by Underflow: If an underflow occurs in the T2 state of the channel 8 down-counter (DCNT8A to DCNT8P) write cycle by the CPU, the DCNT continues counting down because the write to the DCNT by the CPU has priority. The timing in this case is shown in figure 11.72. In this example, a write of H'5555 to DCNT is attempted at the same time as DCNT underflows. Note: In the SH7055F, the retention of the H'0000 value has priority and the write to the DCNT by the CPU is not performed. Note that the operation of the channel 8 down-counters differs between SH7055SF and SH7055F. T1 Poa T2 DCNT input clock Address DCNT address Write data 5555 Internal write signal Underflow signal H'5555 is written to the DCNT because the write to the DCNT has priority 0001 0000 5555 DCNT Interrupt status flag (OSF) Figure 11.72 Contention between DCNT Write and Underflow Rev.2.0, 07/03, page 414 of 960 Contention between DSTR Bit Setting by CPU and Clearing by Underflow: If underflow occurs in the T2 state of a down-counter start register (DSTR) "1" write cycle by the CPU, clearing to 0 by the underflow has priority, and the corresponding bit of DSTR is not set to 1. The timing in this case is shown in figure 11.73. STR write cycle T1 T2 Po Address DSTR address 1 written to DSTR Internal write signal DCNT 0001 0000 0000 Underflow signal Down-count start register Figure 11.73 Contention between DSTR Bit Setting by CPU and Clearing by Underflow Rev.2.0, 07/03, page 415 of 960 Timing of Prescaler Register (PSCR), Timer Control Register (TCR), and Timer Mode Register (TMDR) Setting: Settings in the prescaler register (PSCR), timer control register (TCR), and timer mode register (TMDR) should be made before the counter is started. Operation is not guaranteed if these registers are modified while the counter is running. Also, the counter must not be started until Po has been input 32 times after setting PSCR1 to PSCR4. Interrupt Status Flag Clearing Procedure: When an interrupt status flag is cleared to 0 by the CPU, it must first be read before 0 is written to it. Correct operation cannot be guaranteed if 0 is written without first reading the flag. Setting H'0000 in Free-Running Counters 6A to 6D, 7A to 7D (TCNT6A to TCNT6D, TCNT7A to TCNT7D): If H'0000 is written to a channel 6 and 7 free-running counter (TCNT6A to TCNT6D, TCNT7A to TCNT7D), and the counter is started, the interval up to the first compare-match with the cycle register (CYLR) and duty register (DTR) will be a maximum of one TCNT input clock cycle longer than the set value. With subsequent compare-matches, the correct waveform will be output for the CYLR and DTR values. Register Values when a Free-Running Counter (TCNT) Halts: If the timer start register (TSTR) value is set to 0 during counter operation, only incrementing of the corresponding freerunning counter (TCNT) is stopped, and neither the free-running counter (TCNT) nor any other ATU registers are initialized. The external output value at the time TSTR is cleared to 0 will continue to be output. TCNT0 Writing and Interval Timer Operation: If the CPU program writes 1 to a bit in freerunning counter 0 (TCNT0) corresponding to a bit set to 1 in the interval interrupt request register (ITVRR) when that TCNT0 bit is 0, TCNT0 bit 6, 7, 8, 9, 10, 11, 12, or 13 will be detected as having changed from 0 to 1, and an interrupt request will be sent to INTC and A/D sampling will be started. While the count is halted with the STR0 bit cleared to 0 in timer start register 1 (TSTR1), the bit transition from 0 to 1 will still be detected. Automatic TSR Clearing by DMAC Activation by the ATU: Automatic clearing of TSR is performed after completion of the transfer when the DMAC is in burst mode, and each time the DMAC returns the bus in cycle steal mode. Interrupt Status Flag Setting/Resetting: With TSR, a 0 write to a bit is possible even if overlapping events occur for the same bit before writing 0 after reading 1 to clear that bit. (The duplicate events are not accepted.) Rev.2.0, 07/03, page 416 of 960 External Output Value in Software Standby Mode: In software standby mode, the ATU register and external output values are cleared to 0. However, while the channel 1, 2, and 11 TIO1A to TIO1H, TIO2A to TIO2H, TIO11A, and TIO11B external output values are cleared to 0 immediately after software standby mode is exited, other external output values and all registers are cleared to 0 immediately after a transition to software standby mode. Also, when pin output is inverted by the pin function controller's port B invert register (PBIR) or port K invert register (PKIR), the corresponding pins are set to 1. Software standby mode CK TIO1A to 1H, TIO2A to 2H, TIO11A, 11B Other external outputs Figure 11.74 External Output Value Transition Points in Relation to Software Standby Mode Contention between TCNT Clearing from Channel 10 and TCNT Overflow: When a channel 1 or 2 free-running counter (TCNT1A, TCNT1B, TCNT2A, TCNT2B) overflows, it is cleared to H'0000. If a clear signal from the channel 10 correction counter clear register (TCCLR) is input at the same time, setting 1 to the overflow interrupt status flag (OVF) due to the overflow is still performed in the same way as for a normal overflow. Contention between Channel 10 Reload Register Transfer Timing and Write: If there is contention between a multiplied-output transfer from the input capture register (ICR10A) to the channel 10 reload register (RLDR10C), and the timing of a CPU write to that register, the CPU write has priority and the multiplied output is ignored. Contention between Channel 10 Reload Timing and Write to TCNT10C: If there is contention between a multiplied-output transfer from the input capture register (ICR10A) to the channel 10 reload register (RLDR10C), and a CPU write to the reload counter (TCNT10C), the CPU write has priority and the multiplied output is ignored. Rev.2.0, 07/03, page 417 of 960 ATU Pin Setting: When a port is set to the ATU pin function, the following points must be noted because input capture or count operation may occur. When using a port for input capture input, the corresponding TIOR register must be in the input capture disabled state when the port is set. Regarding channel 10 TI10 input, TCR10 must be in the TI10 input disabled state when the port is set. When using a port for external clock input, the STR bit for the corresponding channel must be in the count operation disabled state when the port is set. When using a port for event input, the corresponding TCR register must be in the count operation disabled state when the port is set. Regarding TCLKB and TI10 input, although input is assigned to a number of pins, when using TCLKB and TI10 input, only one pin should be enabled. Writing to ROM Area Immediately after ATU Register Write: If a write cycle for a ROM address for which address bit 11 = 0 and address bit 12 = 1 (H'00001000 to H'000017FF, H'00003000 to H'000037FF, H'00005000 to H'000057FF, ..., H'0007F000 to H'0007F7FF, ..., H'000FF000 to H'000FF7FF) occurs immediately after an ATU register write cycle, the value, or part of the value, written to ROM will be written to the ATU register. The following measures should be taken to prevent this. * Do not perform a CPU write to a ROM address immediately after an ATU register write cycle. For example, an instruction arrangement in which an MOV instruction that writes to the ATU is located at an even-word address (4n address), and is immediately followed by an MOV instruction that writes to a ROM area, will meet the bug conditions. * Do not perform an AUD write to any of the above ROM addresses immediately after an ATU register write cycle. For example, in the case of a write to overlap RAM when using the RAM emulation function, the write should be performed to the on-chip RAM area address, not the overlapping ROM area address. * Do not perform a DMAC write to an ATU register when a ROM address write operation occurs. Rev.2.0, 07/03, page 418 of 960 11.8 ATU-II Registers and Pins Table 11.4 ATU-II Registers and Pins Channel Register 1 Name* Channel Channel 0 1 Channel Channel Channel Channel Channel Channel Channel Channel Channel 2 3 4 5 6 7 8 9 10 Channel 11 TSTR (3) TSTR1 PSCR (4) PSCR1 TSTR1 PSCR1 TSTR1 TSTR1 TSTR1 TSTR1 TSTR2 TSTR2 -- -- TSTR1 PSCR4 TSTR3 PSCR1 PSCR1 PSCR1 PSCR1 PSCR1 PSCR2 PSCR3 PSCR1 -- TCNT4 TCNT5 TCNT6A TCNT7A -- to to TCNT6D TCNT7D -- TCNT (25) TCNT0H, TCNT1A, TCNT2A, TCNT3 TCNT0L TCNT1B TCNT2B TCNT10AH, TCNT11 TCNT10AL, TCNT10B to TCNT10H -- -- DCNT (16) -- -- -- -- -- -- -- -- DCNT8A -- to DCNT8P -- ECNT (6) -- -- -- -- -- -- -- -- ECNT9A -- to ECNT9F TCR9A TCR10 to TCR9C -- TIOR10 -- TCR (17) -- TCR1A, TCR1B TCR2A, TCR3 TCR2B TCR4 TCR5 TCR6A, TCR7A, TCR8 TCR6B TCR7B -- -- TCR11 TIOR (17) TIOR0 TIOR1A TIOR2A TIOR3A, TIOR4A, TIOR5A, -- to to TIOR3B TIOR4B TIOR5B TIOR1D TIOR2D TSR1A, TSR1B TSR2A, TSR3 TSR2B TSR3 TIER3 -- TSR3 TIER3 -- TSR6 TIER6 -- TIOR11 TSR (12) TSR0 TIER (12) TIER0 ITVRR (3) ITVRR1, ITVRR2A, ITVRR2B TSR7 TIER7 -- TSR8 TIER8 -- TSR9 TIER9 -- TSR10 TIER10 -- TSR11 TIER11 -- TIER1A, TIER2A, TIER3 TIER1B TIER2B -- -- -- GR (37) ICR (5) -- GR1A to GR2A to GR3A to GR4A to GR5A to -- GR1H GR2H GR3D GR4D GR5D -- -- -- -- -- -- -- -- -- GR9A to GR10G GR9F -- ICR10AH, ICR10AL GR11A, GR11B -- ICR0AH, -- ICR0AL to ICR0DH, ICR0DL OCR1 OCR (11) -- OCR2A -- to OCR2H OSBR2 -- -- TMDR -- -- -- -- -- -- OCR10AH, -- OCR10AL, OCR10B -- -- -- -- -- -- OSBR (2) -- TRGMDR -- (1) TMDR (1) -- OSBR1 -- -- TMDR -- -- TMDR -- -- -- -- -- -- -- -- -- -- -- -- TRGMDR -- -- -- Rev.2.0, 07/03, page 419 of 960 Table 11.4 ATU-II Registers and Pins (cont) Channel Register 1 Name* Channel Channel Channel Channel Channel Channel Channel Channel Channel Channel Channel 0 1 2 3 4 5 6 7 8 9 10 Channel 11 CYLR (8) -- -- -- -- -- -- CYLR6A CYLR7A -- to to CYLR6D CYLR7D BFR6A BFR7A -- to to BFR6D BFR7D DTR6A DTR7A -- to to DTR6D DTR7D PMDR -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- TO7A to D -- RLDR TCNR OTR DSTR -- -- -- BFR (8) -- -- -- -- -- -- -- -- -- DTR (8) -- -- -- -- -- -- -- -- -- PMDR (1) -- RLDR (1) -- TCNR (1) -- OTR (1) -- -- -- -- -- -- -- -- -- -- TIO1A to H, TCLKA, TCLKB -- -- -- -- -- -- -- -- -- TIO2A to H, TCLKA, TCLKB -- -- -- -- -- -- -- -- -- TIO3A to D, TCLKA, TCLKB -- -- -- -- -- -- -- -- -- TIO4A to D, TCLKA, TCLKB -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- RLD10C NCR10 TCCLR10 T10 -- -- -- -- -- -- -- -- -- TIO11A, TIO11B, TCLKA, TCLKB DSTR (1) -- RLDENR -- (1) RLD (1) NCR (1) -- -- RLDENR -- -- -- -- TO8A to P -- -- -- TI9A to F TCCLR (1) -- Pins* 2 TI0A to D TIO5A TO6A to D, to D TCLKA, TCLKB Notes: *1 Figures in parentheses show the number of registers. A 32-bit register is shown as a single register. *2 Pin functions should be set as described in section 20, Pin Function Controller (PFC). Rev.2.0, 07/03, page 420 of 960 Section 12 Advanced Pulse Controller (APC) 12.1 Overview The SH7055SF has an on-chip advanced pulse controller (APC) that can generate a maximum of eight pulse outputs, using the advanced timer unit II (ATU-II) as the time base. 12.1.1 Features The features of the APC are summarized below. * Maximum eight pulse outputs The pulse output pins can be selected from among eight pins. Multiple settings are possible. * Output trigger provided by advanced timer unit II (ATU-II) channel 2 Pulse 0 output and 1 output is performed using the compare-match signal generated by the ATU-II channel II compare-match register as the trigger. Rev.2.0, 07/03, page 421 of 960 12.1.2 Block Diagram Figure 12.1 shows a block diagram of the advanced pulse controller. ATU-II Internal/external clock TCNT11 Compare GR11B GR11A Comparematch signal Comparematch signal Set Bit 7 Bit 15 Reset Set Bit 6 POPCR (pulse output port setting register) PULS7 Bit 14 Reset Set PULS6 Bit 5 Bit 13 Reset Set PULS5 Bit 4 Bit 12 Reset Set PULS4 Bit 3 Bit 11 Reset Set PULS3 Bit 2 Bit 10 Reset Set PULS2 Bit 1 Bit 9 Reset Set PULS1 Bit 0 Bit 8 Reset PULS0 APC POPCR: Pulse output port control register Figure 12.1 Advanced Pulse Controller Block Diagram Rev.2.0, 07/03, page 422 of 960 12.1.3 Pin Configuration Table 12.1 summarizes the advanced pulse controller's output pins. Table 12.1 Advanced Pulse Controller Pins Pin Name PULS0 PULS1 PULS2 PULS3 PULS4 PULS5 PULS6 PULS7 I/O Output Output Output Output Output Output Output Output Function APC pulse output 0 APC pulse output 1 APC pulse output 2 APC pulse output 3 APC pulse output 4 APC pulse output 5 APC pulse output 6 APC pulse output 7 12.1.4 Register Configuration Table 12.2 summarizes the advanced pulse controller's register. Table 12.2 Advanced Pulse Controller Register Name Pulse output port control register Abbreviation POPCR R/W R/W Initial Value H'0000 Address H'FFFFF700 Access Size 8, 16 Note: Register access requires 4 or 5 cycles. Rev.2.0, 07/03, page 423 of 960 12.2 12.2.1 Register Descriptions Pulse Output Port Control Register (POPCR) The pulse output port control register (POPCR) is a 16-bit readable/writable register. POPCR is initialized to H'0000 by a power-on reset and in hardware standby mode. It is not initialized in software standby mode. Bit: 15 PULS7 ROE Initial value: R/W: Bit: 0 R/W 7 PULS7 SOE Initial value: R/W: 0 R/W 14 PULS6 ROE 0 R/W 6 PULS6 SOE 0 R/W 13 PULS5 ROE 0 R/W 5 PULS5 SOE 0 R/W 12 PULS4 ROE 0 R/W 4 PULS4 SOE 0 R/W 11 PULS3 ROE 0 R/W 3 PULS3 SOE 0 R/W 10 PULS2 ROE 0 R/W 2 PULS2 SOE 0 R/W 9 PULS1 ROE 0 R/W 1 PULS1 SOE 0 R/W 8 PULS0 ROE 0 R/W 0 PULS0 SOE 0 R/W * Bits 15 to 8--PULS7 to PULS0 Reset Output Enable (PULS7ROE to PULS0ROE): These bits enable or disable 0 output to the APC pulse output pins (PULS7 to PULS0) bit by bit. Bits 15 to 8: PULS7ROE to PULS0ROE 0 1 Description 0 output to APC pulse output pin (PULS7-PULS0) is disabled (Initial value) 0 output to APC pulse output pin (PULS7-PULS0) is enabled When one of these bits is set to 1, 0 is output from the corresponding pin on a compare-match between the GR11B and TCNT11 values. Rev.2.0, 07/03, page 424 of 960 * Bits 7 to 0--PULS7 to PULS0 Set Output Enable (PULS7SOE to PULS0SOE): These bits enable or disable 1 output to the APC pulse output pins (PULS7 to PULS0) bit by bit. Bits 7 to 0: PULS7SOE to PULS0SOE 0 1 Description 1 output to APC pulse output pin (PULS7-PULS0) is disabled (Initial value) 1 output to APC pulse output pin (PULS7-PULS0) is enabled When one of these bits is set to 1, 1 is output from the corresponding pin on a compare-match between the GR11A and TCNT11 values. 12.3 12.3.1 Operation Overview APC pulse output is enabled by designating multiplex pins for APC pulse output with the pin function controller (PFC), and setting the corresponding bits to 1 in the pulse output port control register (POPCR). When general register IIA (GRIIA) in the advanced timer unit II (ATU-II) subsequently generates a compare-match signal, 1 is output from the pins set to 1 by bits 7 to 0 in POPCR. When general register 11B (GR11B) generates a compare-match signal, 0 is output from the pins set to 1 by bits 15 to 8 in POPCR. 0 is output from the output-enabled state until the first compare-match occurs. The advanced pulse controller output operation is shown in figure 12.2. Rev.2.0, 07/03, page 425 of 960 CR Upper 8 bits of POPCR GR11B Compare-match signal Reset signal Port function selection APC output pins (PULS0 to PULS7) Set signal Compare-match signal GRIIA Lower 8 bits of POPCR Figure 12.2 Advanced Pulse Controller Output Operation 12.3.2 Advanced Pulse Controller Output Operation Example of Setting Procedure for Advanced Pulse Controller Output Operation: Figure 12.3 shows an example of the setting procedure for advanced pulse controller output operation. 1. Set general registers GR11A and GR11B as output compare registers with the timer I/O control register (TIOR). 2. Set the pulse rise point with GR11A and the pulse fall point with GR11B. 3. Select the timer counter 11 (TCNT11) counter clock with the timer prescale register (PSCR). TCNT11 can only be cleared by an overflow. 4. Enable the respective interrupts with the timer interrupt enable register (TIER). 5. Set the pins for 1 output and 0 output with POPCR. 6. Set the control register for the port to be used by the APC to the APC output pin function. 7. Set the STR bit to 1 in the timer start register (TSTR) to start timer counter 11 (TCNT11). 8. Each time a compare-match interrupt is generated, update the GR value and set the next pulse output time. 9. Each time a compare-match interrupt is generated, update the POPCR value and set the next pin for pulse output. Rev.2.0, 07/03, page 426 of 960 APC output operation GR function selection GR setting ATU-II settings Count operation setting Interrupt request setting APC setting Port setting ATU-II setting Rise/fall port setting Port output setting Start count 3 4 5 6 7 1 2 Compare-match? Yes ATU-II setting APC setting GR setting Rise/fall port setting No 8 9 Figure 12.3 Example of Setting Procedure for Advanced Pulse Controller Output Operation Rev.2.0, 07/03, page 427 of 960 Example of Advanced Pulse Controller Output Operation: Figure 12.4 shows an example of advanced pulse controller output operation. 1. Set ATU-11 registers GR11A and GR11B (to be used for output trigger generation) as output compare registers. Set the rise point in GR11A and the fall point in GR11B, and enable the respective compare-match interrupts. 2. Write H'0101 to POPCR. 3. Start the TCNT11 count, when a GR11A compare-match occurs, 1 is output from the PULS0 pin. When a GR11B compare-match occurs, 0 is output from the PULS0 pin. 4. Pulse output widths and output pins can be continually changed by successively rewriting GR11A, GR11B, and POPCR in response to compare-match interrupts. 5. By setting POPCR to a value such as H'E0E0, pulses can be output from up to 8 pins in response to a single compare-match. Cleared on overflow TCNT value Rewritten Rewritten Rewritten Rewritten Rewritten Rewritten Rewritten Rewritten Rewritten Rewritten GR11B GR11A H'0000 POPCR 0101 0202 0404 0808 1010 E0E0 PULS0 PULS1 PULS2 PULS3 PULS4 PULS5 PULS6 PULS7 Figure 12.4 Example of Advanced Pulse Controller Output Operation Rev.2.0, 07/03, page 428 of 960 12.4 Usage Notes Contention between Compare-Match Signals: If the same value is set for both GR11A and GR11B, and 0 output and 1 output are both enabled for the same pin by the POPCR settings, 0 output has priority on pins PULS0 to PULS7 when compare-matches occur. TCNT value H'FFFF H'8000 GR11A GR11B POPCR H'8000 H'8000 H'0101 PULS0 pin Pin output is 0 Figure 12.5 Example of Compare-Match Contention Rev.2.0, 07/03, page 429 of 960 Rev.2.0, 07/03, page 430 of 960 Section 13 Watchdog Timer (WDT) 13.1 Overview The watchdog timer (WDT) is a 1-channel timer for monitoring system operations. If a system encounters a problem (crashes, for example) and the timer counter overflows without being rewritten correctly by the CPU, an overflow signal (WDTOVF) is output externally. The WDT can simultaneously generate an internal reset signal for the entire chip. When the watchdog function is not needed, the WDT can be used as an interval timer. In the interval timer operation, an interval timer interrupt is generated at each counter overflow. 13.1.1 Features The WDT has the following features: * Works in watchdog timer mode or interval timer mode * Outputs WDTOVF in watchdog timer mode When the counter overflows in watchdog timer mode, overflow signal WDTOVF is output externally. It is possible to select whether to reset the chip internally when this happens. Either the power-on reset or manual reset signal can be selected as the internal reset signal. * Generates interrupts in interval timer mode When the counter overflows, it generates an interval timer interrupt. * Works with eight counter input clocks Rev.2.0, 07/03, page 431 of 960 13.1.2 Block Diagram Figure 13.1 is the block diagram of the WDT. ITI (interrupt signal) Overflow Interrupt control Clock Clock select Internal reset signal* Reset control /2 /64 /128 /256 /512 /1024 /4096 /8192 Internal clock sources RSTCSR TCNT TCSR Module bus WDT TCSR: Timer control/status register TCNT: Timer counter RSTCSR: Reset control/status register Bus interface Note: * The internal reset signal can be generated by making a register setting. Figure 13.1 WDT Block Diagram 13.1.3 Pin Configuration Table 13.1 shows the pin configuration. Table 13.1 Pin Configuration Pin Watchdog timer overflow Abbreviation WDTOVF I/O O Function Outputs the counter overflow signal in watchdog timer mode Rev.2.0, 07/03, page 432 of 960 Internal data bus 13.1.4 Register Configuration Table 13.2 summarizes the three WDT registers. They are used to select the clock, switch the WDT mode, and control the reset signal. Table 13.2 WDT Registers Address Name Timer control/status register Timer counter Reset control/status register Abbreviation R/W TCSR TCNT RSTCSR R/(W)* R/W R/(W) * 3 3 Initial Value H'18 H'00 H'1F Write* 1 Read* 2 H'FFFFEC10 H'FFFFEC10 H'FFFFEC11 H'FFFFEC12 H'FFFFEC13 Notes: In register access, three cycles are required for both byte access and word access. *1 Write by word transfer. These registers cannot be written in byte or longword. *2 Read by byte transfer. These registers cannot be read in word or longword. *3 Only 0 can be written to bit 7 to clear the flag. 13.2 13.2.1 Register Descriptions Timer Counter (TCNT) TCNT is an 8-bit readable/writable upcounter. (TCNT differs from other registers in that it is more difficult to write to. See section 13.2.4, Register Access, for details.) When the timer enable bit (TME) in the timer control/status register (TCSR) is set to 1, the watchdog timer counter starts counting pulses of an internal clock selected by clock select bits 2 to 0 (CKS2 to CKS0) in TCSR. When the value of TCNT overflows (changes from H'FF to H'00), a watchdog timer overflow signal (WDTOVF) or interval timer interrupt (ITI) is generated, depending on the mode selected in the WT/IT bit of TCSR. TCNT is initialized to H'00 by a power-on reset, in hardware and software standby modes, and when the TME bit is cleared to 0. Bit: 7 6 5 4 3 2 1 0 Initial value: R/W: 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W Rev.2.0, 07/03, page 433 of 960 13.2.2 Timer Control/Status Register (TCSR) The timer control/status register (TCSR) is an 8-bit readable/writable register. (TCSR differs from other registers in that it is more difficult to write to. See section 13.2.4, Register Access, for details.) TCSR performs selection of the timer counter (TCNT) input clock and mode. TCSR is initialized to H'00 by a power-on reset, and in hardware standby mode and software standby mode. Bit: 7 OVF Initial value: R/W: 0 R/(W)* 6 WT/IT 0 R/W 5 TME 0 R/W 4 -- 1 R 3 -- 1 R 2 CKS2 0 R/W 1 CKS1 0 R/W 0 CKS0 0 R/W Note: * The only operation permitted on the OVF bit is a write of 0 after reading 1. * Bit 7--Overflow Flag (OVF): Indicates that TCNT has overflowed from H'FF to H'00 in interval timer mode. This flag is not set in the watchdog timer mode. Bit 7: OVF 0 Description No overflow of TCNT in interval timer mode [Clearing condition] When 0 is written to OVF after reading OVF 1 TCNT overflow in interval timer mode (Initial value) * Bit 6--Timer Mode Select (WT/IT): Selects whether to use the WDT as a watchdog timer or interval timer. When TCNT overflows, the WDT either generates an interval timer interrupt (ITI) or generates a WDTOVF signal, depending on the mode selected. Bit 6: WT/IT IT 0 1 Description Interval timer mode: interval timer interrupt (ITI) request to the CPU when TCNT overflows (Initial value) Watchdog timer mode: WDTOVF signal output externally when TCNT overflows. (Section 13.2.3, Reset Control/Status Register (RSTCSR), describes in detail what happens when TCNT overflows in watchdog timer mode.) Rev.2.0, 07/03, page 434 of 960 * Bit 5--Timer Enable (TME): Enables or disables the timer. Bit 5: TME 0 1 Description Timer disabled: TCNT is initialized to H'00 and count-up stops (Initial value) Timer enabled: TCNT starts counting. A WDTOVF signal or interrupt is generated when TCNT overflows. * Bits 4 and 3--Reserved: These bits always read 1. The write value should always be 1. * Bits 2 to 0: Clock Select 2 to 0 (CKS2 to CKS0): These bits select one of eight internal clock sources for input to TCNT. The clock signals are obtained by dividing the frequency of the system clock (). Description Bit 2: CKS2 Bit 1: CKS1 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 Bit 0: CKS0 0 1 0 1 0 1 0 1 Clock Source /2 /64 /128 /256 /512 /1024 /4096 /8192 (Initial value) Overflow Interval* ( = 40 MHz) 12.8 s 409.6 s 0.8 ms 1.6 ms 3.3 ms 6.6 ms 26.2 ms 52.4 ms Note: * The overflow interval listed is the time from when the TCNT begins counting at H'00 until an overflow occurs. Rev.2.0, 07/03, page 435 of 960 13.2.3 Reset Control/Status Register (RSTCSR) RSTCSR is an 8-bit readable/writable register. (RSTCSR differs from other registers in that it is more difficult to write. See section 13.2.4, Register Access, for details.) It controls output of the internal reset signal generated by timer counter (TCNT) overflow. RSTCR is initialized to H'1F by input of a reset signal from the RES pin, but is not initialized by the internal reset signal generated by overflow of the WDT. It is initialized to H'1F in hardware standby mode and software standby mode. Bit: 7 WOVF Initial value: R/W: 0 R/(W)* 6 RSTE 0 R/W 5 RSTS 0 R/W 4 -- 1 R 3 -- 1 R 2 -- 1 R 1 -- 1 R 0 -- 1 R Note: * Only 0 can be written to bit 7 to clear the flag. * Bit 7--Watchdog Timer Overflow Flag (WOVF): Indicates that TCNT has overflowed (H'FF to H'00) in watchdog timer mode. This flag is not set in interval timer mode. Bit 7: WOVF 0 Description No TCNT overflow in watchdog timer mode [Clearing condition] When 0 is written to WOVF after reading WOVF 1 Set by TCNT overflow in watchdog timer mode (Initial value) * Bit 6--Reset Enable (RSTE): Selects whether to reset the chip internally if TCNT overflows in watchdog timer mode. Bit 6: RSTE 0 1 Description Not reset when TCNT overflows Reset when TCNT overflows (Initial value) LSI not reset internally, but TCNT and TCSR reset within WDT. * Bit 5--Reset Select (RSTS): Selects the kind of internal reset to be generated when TCNT overflows in watchdog timer mode. Bit 5: RSTS 0 1 Description Power-on reset Manual reset (Initial value) * Bits 4 to 0--Reserved: These bits are always read as 1. The write value should always be 1. Rev.2.0, 07/03, page 436 of 960 13.2.4 Register Access The watchdog timer's TCNT, TCSR, and RSTCSR registers differ from other registers in that they are more difficult to write to. The procedures for writing and reading these registers are given below. Writing to TCNT and TCSR: These registers must be written by a word transfer instruction. They cannot be written by byte transfer instructions. TCNT and TCSR both have the same write address. The write data must be contained in the lower byte of the written word. The upper byte must be H'5A (for TCNT) or H'A5 (for TCSR) (figure 13.2). This transfers the write data from the lower byte to TCNT or TCSR. Writing to TCNT 15 Address: H'FFFFEC10 H'5A 8 7 Write data 0 Writing to TCSR 15 Address: H'FFFFEC10 H'A5 8 7 Write data 0 Figure 13.2 Writing to TCNT and TCSR Writing to RSTCSR: RSTCSR must be written by a word access to address H'FFFFEC12. It cannot be written by byte transfer instructions. Procedures for writing 0 to WOVF (bit 7) and for writing to RSTE (bit 6) and RSTS (bit 5) are different, as shown in figure 13.3. To write 0 to the WOVF bit, the write data must be H'A5 in the upper byte and H'00 in the lower byte. This clears the WOVF bit to 0. The RSTE and RSTS bits are not affected. To write to the RSTE and RSTS bits, the upper byte must be H'5A and the lower byte must be the write data. The values of bits 6 and 5 of the lower byte are transferred to the RSTE and RSTS bits, respectively. The WOVF bit is not affected. Rev.2.0, 07/03, page 437 of 960 Writing 0 to the WOVF bit 15 Address: H'FFFFEC12 H'A5 8 7 H'00 0 Writing to the RSTE and RSTS bits 15 Address: H'FFFFEC12 H'5A 8 7 Write data 0 Figure 13.3 Writing to RSTCSR Reading from TCNT, TCSR, and RSTCSR: TCNT, TCSR, and RSTCSR are read like other registers. Use byte transfer instructions. The read addresses are H'FFFFEC10 for TCSR, H'FFFFEC11 for TCNT, and H'FFFFEC13 for RSTCSR. 13.3 13.3.1 Operation Watchdog Timer Mode To use the WDT as a watchdog timer, set the WT/IT and TME bits of TCSR to 1. Software must prevent TCNT overflow by rewriting the TCNT value (normally by writing H'00) before overflow occurs. No TCNT overflows will occur while the system is operating normally, but if TCNT fails to be rewritten and overflows occur due to a system crash or the like, a WDTOVF signal is output externally (figure 13.4). The WDTOVF signal can be used to reset the system. The WDTOVF signal is output for 128 clock cycles. If the RSTE bit in RSTCSR is set to 1, a signal to reset the chip will be generated internally simultaneous to the WDTOVF signal when TCNT overflows. Either a power-on reset or a manual reset can be selected by the RSTS bit in RSTCSR. The internal reset signal is output for 512 clock cycles. When a WDT overflow reset is generated simultaneously with a reset input at the RES pin, the RES reset takes priority, and the WOVF bit in RSTCSR is cleared to 0. The following are not initialized by a WDT reset signal: * PFC (pin function controller) registers * I/O port registers These registers are initialized only by an external power-on reset. Rev.2.0, 07/03, page 438 of 960 TCNT value Overflow H'FF H'00 WT/ = 1 TME = 1 H'00 written in TCNT WOVF = 1 Time WT/ = 1 H'00 written in TCNT TME = 1 and internal reset generated signal 128 clocks Internal reset signal* 512 clocks WT/ : Timer mode select bit TME: Timer enable bit Note: * Internal reset signal occurs only when the RSTE bit is set to 1. Figure 13.4 Operation in Watchdog Timer Mode Rev.2.0, 07/03, page 439 of 960 13.3.2 Interval Timer Mode To use the WDT as an interval timer, clear WT/IT to 0 and set TME to 1 in TCSR. An interval timer interrupt (ITI) is generated each time the timer counter overflows. This function can be used to generate interval timer interrupts at regular intervals (figure 13.5). TCNT value H'FF Overflow Overflow Overflow Overflow H'00 WT/IT = 0 TME = 1 ITI ITI ITI ITI Time ITI: Interval timer interrupt request generation Figure 13.5 Operation in Interval Timer Mode 13.3.3 Timing of Setting the Overflow Flag (OVF) In interval timer mode, when TCNT overflows, the OVF flag of TCSR is set to 1 and an interval timer interrupt (ITI) is simultaneously requested (figure 13.6). CK TCNT H'FF H'00 Overflow signal (internal signal) OVF Figure 13.6 Timing of Setting OVF Rev.2.0, 07/03, page 440 of 960 13.3.4 Timing of Setting the Watchdog Timer Overflow Flag (WOVF) When TCNT overflows in watchdog timer mode, the WOVF bit of RSTCSR is set to 1 and a WDTOVF signal is output. When the RSTE bit in RSTCSR is set to 1, TCNT overflow enables an internal reset signal to be generated for the entire chip (figure 13.7). CK TCNT H'FF H'00 Overflow signal (internal signal) WOVF Figure 13.7 Timing of Setting WOVF Rev.2.0, 07/03, page 441 of 960 13.4 13.4.1 Usage Notes TCNT Write and Increment Contention If a timer counter increment clock pulse is generated during the T3 state of a write cycle to TCNT, the write takes priority and the timer counter is not incremented (figure 13.8). TCNT write cycle T1 CK Address Internal write signal TCNT input clock TCNT N M Counter write data TCNT address T2 T3 Figure 13.8 Contention between TCNT Write and Increment 13.4.2 Changing CKS2 to CKS0 Bit Values If the values of bits CKS2 to CKS0 in the timer control/status register (TCSR) are rewritten while the WDT is running, the count may not increment correctly. Always stop the watchdog timer (by clearing the TME bit to 0) before changing the values of bits CKS2 to CKS0. 13.4.3 Changing between Watchdog Timer/Interval Timer Modes To prevent incorrect operation, always stop the watchdog timer (by clearing the TME bit to 0) before switching between interval timer mode and watchdog timer mode. Rev.2.0, 07/03, page 442 of 960 13.4.4 System Reset by WDTOVF Signal If a WDTOVF signal is input to the RES pin, the chip cannot initialize correctly. Avoid logical input of the WDTOVF output signal to the RES input pin. To reset the entire system with the WDTOVF signal, use the circuit shown in figure 13.9. This LSI Reset input RES Reset signal to entire system WDTOVF Figure 13.9 Example of System Reset Circuit Using WDTOVF Signal 13.4.5 Internal Reset in Watchdog Timer Mode If the RSTE bit is cleared to 0 in watchdog timer mode, the chip will not be reset internally when a TCNT overflow occurs, but TCNT and TCSR in the WDT will be reset. Because the internal clock obtained by dividing the system clock() is also reset at this time, the SCI, A/D converter, and CMT that use the internal clock may not operate correctly from hereafter. To continue using these modules, initialize them before use. 13.4.6 Manual Reset in Watchdog Timer When an internal reset is effected by TCNT overflow in watchdog timer mode, the processor waits until the end of the bus cycle at the time of manual reset generation before making the transition to manual reset exception processing. Therefore, the bus cycle is retained in a manual reset, but if a manual reset occurs while the bus is released or during DMAC burst transfer, manual reset exception processing will be deferred until the CPU acquires the bus. However, if the interval from generation of the manual reset until the end of the bus cycle is equal to or longer than the internal manual reset interval of 512 cycles, the internal manual reset source is ignored instead of being deferred, and manual reset exception processing is not executed. Rev.2.0, 07/03, page 443 of 960 Rev.2.0, 07/03, page 444 of 960 Section 14 Compare Match Timer (CMT) 14.1 Overview The SH7055SF has an on-chip compare match timer (CMT) comprising two 16-bit timer channels. The CMT has 16-bit counters and can generate interrupts at set intervals. 14.1.1 Features The CMT has the following features: * Four types of counter input clock can be selected One of four internal clocks (P/8, P/32, P/128, P/512) can be selected independently for each channel. * Interrupt sources A compare match interrupt can be requested independently for each channel. Rev.2.0, 07/03, page 445 of 960 14.1.2 Block Diagram Figure 14.1 shows a block diagram of the CMT. P/32 CM10 P/8 P/512 CMI1 P/8 P/32 P/512 P/128 P/128 Control circuit Clock selection Control circuit Clock selection Comparator Comparator CMCOR0 CMCOR1 CMCSR0 CMCSR1 CMCNT0 CMCNT1 Bus interface Internal bus CMSTR Module bus CMT CMSTR: CMCSR: CMCOR: CMCNT: CMI: Compare match timer start register Compare match timer control/status register Compare match timer constant register Compare match timer counter Compare match interrupt Figure 14.1 CMT Block Diagram Rev.2.0, 07/03, page 446 of 960 14.1.3 Register Configuration Table 14.1 summarizes the CMT register configuration. Table 14.1 Register Configuration Channel Name Shared 0 Abbreviation R/W R/W R/(W)* R/W R/W R/(W)* R/W R/W Initial Value H'0000 H'0000 H'0000 Address Access Size (Bits) Compare match timer CMSTR start register Compare match timer CMCSR0 control/status register 0 Compare match timer CMCNT0 counter 0 Compare match timer CMCOR0 constant register 0 H'FFFFF710 8, 16, 32 H'FFFFF712 8, 16, 32 H'FFFFF714 8, 16, 32 H'FFFF H'FFFFF716 8, 16, 32 H'0000 H'0000 H'FFFFF718 8, 16, 32 H'FFFFF71A 8, 16, 32 1 Compare match timer CMCSR1 control/status register 1 Compare match timer CMCNT1 counter 1 Compare match timer CMCOR1 constant register 1 H'FFFF H'FFFFF71C 8, 16, 32 Notes: With regard to access size, four of five cycles are required for byte access and word access, and eight or nine cycles for longword access. * Only 0 can be written to the CMCSR0 and CMCSR1 CMF bits to clear the flags. Rev.2.0, 07/03, page 447 of 960 14.2 14.2.1 Register Descriptions Compare Match Timer Start Register (CMSTR) The compare match timer start register (CMSTR) is a 16-bit register that selects whether to operate or halt the channel 0 and channel 1 counters (CMCNT). It is initialized to H'0000 by a power-on reset and in the standby modes. Bit: 15 -- Initial value: R/W: Bit: 0 R 7 -- Initial value: R/W: 0 R 14 -- 0 R 6 -- 0 R 13 -- 0 R 5 -- 0 R 12 -- 0 R 4 -- 0 R 11 -- 0 R 3 -- 0 R 10 -- 0 R 2 -- 0 R 9 -- 0 R 1 STR1 0 R/W 8 -- 0 R 0 STR0 0 R/W * Bits 15-2--Reserved: These bits are always read as 0. The write value should always be 0. * Bit 1--Count Start 1 (STR1): Selects whether to operate or halt compare match timer counter 1. Bit 1: STR1 0 1 Description CMCNT1 count operation halted CMCNT1 count operation (Initial value) * Bit 0--Count Start 0 (STR0): Selects whether to operate or halt compare match timer counter 0. Bit 0: STR0 0 1 Description CMCNT0 count operation halted CMCNT0 count operation (Initial value) Rev.2.0, 07/03, page 448 of 960 14.2.2 Compare Match Timer Control/Status Register (CMCSR) The compare match timer control/status register (CMCSR) is a 16-bit register that indicates the occurrence of compare matches, sets the enable/disable status of interrupts, and establishes the clock used for incrementation. It is initialized to H'0000 by a power-on reset and in the standby modes. Bit: 15 -- Initial value: R/W: Bit: 0 R 7 CMF Initial value: R/W: 0 R/(W)* 14 -- 0 R 6 CMIE 0 R/W 13 -- 0 R 5 -- 0 R 12 -- 0 R 4 -- 0 R 11 -- 0 R 3 -- 0 R 10 -- 0 R 2 -- 0 R 9 -- 0 R 1 CKS1 0 R/W 8 -- 0 R 0 CKS0 0 R/W Note: * Only 0 can be written to clear the flag. * Bits 15-8 and 5-2--Reserved: These bits are always read as 0. The write value should always be 0. * Bit 7--Compare Match Flag (CMF): This flag indicates whether or not the CMCNT and CMCOR values have matched. Bit 7: CMF 0 Description CMCNT and CMCOR values have not matched [Clearing condition] Write 0 to CMF after reading 1 from it 1 CMCNT and CMCOR values have matched (Initial value) * Bit 6--Compare Match Interrupt Enable (CMIE): Selects whether to enable or disable a compare match interrupt (CMI) when the CMCNT and CMCOR values have matched (CMF = 1). Bit 6: CMIE 0 1 Description Compare match interrupt (CMI) disabled Compare match interrupt (CMI) enabled (Initial value) Rev.2.0, 07/03, page 449 of 960 * Bits 1 and 0--Clock Select 1 and 0 (CKS1, CKS0): These bits select the clock input to CMCNT from among the four internal clocks obtained by dividing the peripheral clock (P). When the STR bit of CMSTR is set to 1, CMCNT begins incrementing with the clock selected by CKS1 and CKS0. Bit 1: CKS1 0 Bit 0: CKS0 0 1 1 0 1 Description P/8 P/32 P/128 P/512 (Initial value) 14.2.3 Compare Match Timer Counter (CMCNT) The compare match timer counter (CMCNT) is a 16-bit register used as an up-counter for generating interrupt requests. When an internal clock is selected with the CKS1 and CKS0 bits of the CMCSR register and the STR bit of CMSTR is set to 1, CMCNT begins incrementing with that clock. When the CMCNT value matches that of the compare match timer constant register (CMCOR), CMCNT is cleared to H'0000 and the CMF flag of CMCSR is set to 1. If the CMIE bit of CMCSR is set to 1 at this time, a compare match interrupt (CMI) is requested. CMCNT is initialized to H'0000 by a power-on reset and in the standby modes. It is not initialized by a manual reset. Bit: 15 14 13 12 11 10 9 8 Initial value: R/W: Bit: 0 R/W 7 0 R/W 6 0 R/W 5 0 R/W 4 0 R/W 3 0 R/W 2 0 R/W 1 0 R/W 0 Initial value: R/W: 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W Rev.2.0, 07/03, page 450 of 960 14.2.4 Compare Match Timer Constant Register (CMCOR) The compare match timer constant register (CMCOR) is a 16-bit register that sets the period for compare match with CMCNT. CMCOR is initialized to H'FFFF by a power-on reset and in the standby modes. It is not initialized by a manual reset. Bit: 15 14 13 12 11 10 9 8 Initial value: R/W: Bit: 1 R/W 7 1 R/W 6 1 R/W 5 1 R/W 4 1 R/W 3 1 R/W 2 1 R/W 1 1 R/W 0 Initial value: R/W: 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 14.3 14.3.1 Operation Cyclic Count Operation When an internal clock is selected with the CKS1, CKS0 bits of the CMCSR register and the STR bit of CMSTR is set to 1, CMCNT begins incrementing with the selected clock. When the CMCNT counter value matches that of the compare match constant register (CMCOR), the CMCNT counter is cleared to H'0000 and the CMF flag of the CMCSR register is set to 1. If the CMIE bit of the CMCSR register is set to 1 at this time, a compare match interrupt (CMI) is requested. The CMCNT counter begins counting up again from H'0000. Figure 14.2 shows the compare match counter operation. CMCNT value CMCOR Counter cleared by CMCOR compare match H'0000 Time Figure 14.2 Counter Operation Rev.2.0, 07/03, page 451 of 960 14.3.2 CMCNT Count Timing One of four clocks (P/8, P/32, P/128, P/512) obtained by dividing the peripheral clock (P) can be selected by the CKS1 and CKS0 bits of CMCSR. Figure 14.3 shows the timing. P Internal clock CMCNT input clock CMCNT N-1 N N+1 Figure 14.3 Count Timing 14.4 14.4.1 Interrupts Interrupt Sources and DTC Activation The CMT has a compare match interrupt for each channel, with independent vector addresses allocated to each of them. The corresponding interrupt request is output when interrupt request flag CMF is set to 1 and interrupt enable bit CMIE has also been set to 1. When activating CPU interrupts by interrupt request, the priority between the channels can be changed by means of interrupt controller settings. See section 7, Interrupt Controller (INTC), for details. 14.4.2 Compare Match Flag Set Timing The CMF bit of the CMCSR register is set to 1 by the compare match signal generated when the CMCOR register and the CMCNT counter match. The compare match signal is generated upon the final state of the match (timing at which the CMCNT counter matching count value is updated). Consequently, after the CMCOR register and the CMCNT counter match, a compare match signal will not be generated until a CMCNT counter input clock occurs. Figure 14.4 shows the CMF bit set timing. Rev.2.0, 07/03, page 452 of 960 P CMCNT input clock CMCNT N 0 CMCOR N Compare match signal CMF CMI Figure 14.4 CMF Set Timing 14.4.3 Compare Match Flag Clear Timing The CMF bit of the CMCSR register is cleared by writing a 0 to it after reading a 1. Figure 14.5 shows the timing when the CMF bit is cleared by the CPU. CMCSR write cycle T1 T2 P CMF Figure 14.5 Timing of CMF Clear by the CPU Rev.2.0, 07/03, page 453 of 960 14.5 Usage Notes Take care that the contentions described in sections 14.5.1 to 14.5.3 do not arise during CMT operation. 14.5.1 Contention between CMCNT Write and Compare Match If a compare match signal is generated during the T2 state of the CMCNT counter write cycle, the CMCNT counter clear has priority, so the write to the CMCNT counter is not performed. Figure 14.6 shows the timing. CMCNT write cycle T1 T2 P Address CMCNT Internal write signal Compare match signal CMCNT N H'0000 Figure 14.6 CMCNT Write and Compare Match Contention Rev.2.0, 07/03, page 454 of 960 14.5.2 Contention between CMCNT Word Write and Incrementation If an increment occurs during the T2 state of the CMCNT counter word write cycle, the counter write has priority, so no increment occurs. Figure 14.7 shows the timing. CMCNT write cycle T1 T2 P Address CMCNT Internal write signal CMCNT input clock CMCNT N M CMCNT write data Figure 14.7 CMCNT Word Write and Increment Contention Rev.2.0, 07/03, page 455 of 960 14.5.3 Contention between CMCNT Byte Write and Incrementation If an increment occurs during the T2 state of the CMCNT byte write cycle, the counter write has priority, so no increment of the write data results on the side on which the write was performed. The byte data on the side on which writing was not performed is also not incremented, so the contents are those before the write. Figure 14.8 shows the timing when an increment occurs during the T2 state of the CMCNTH write cycle. CMCNT write cycle T1 T2 P Address CMCNTH Internal write signal CMCNT input clock CMCNTH N M CMCNTH write data CMCNTL X X Figure 14.8 CMCNT Byte Write and Increment Contention Rev.2.0, 07/03, page 456 of 960 Section 15 Serial Communication Interface (SCI) 15.1 Overview The SH7055SF has a serial communication interface (SCI) with five independent channels. The SCI supports both asynchronous and synchronous serial communication. It also has a multiprocessor communication function for serial communication between two or more processors, and a clock inverted input/output function. 15.1.1 Features The SCI has the following features: * Selection of asynchronous or synchronous as the serial communication mode Asynchronous mode Serial data communication is synchronized in character units. The SCI can communicate with a universal asynchronous receiver/transmitter (UART), an asynchronous communication interface adapter (ACIA), or any other chip that employs standard asynchronous serial communication. It can also communicate with two or more other processors using the multiprocessor communication function. There are twelve selectable serial data communication formats. * Data length: seven or eight bits * Stop bit length: one or two bits * Parity: even, odd, or none * Multiprocessor bit: one or none * Receive error detection: parity, overrun, and framing errors * Break detection: by reading the RxD level directly when a framing error occurs Synchronous mode Serial data communication is synchronized with a clock signal. The SCI can communicate with other chips having a synchronous communication function. There is one serial data communication format. * Data length: eight bits * Receive error detection: overrun errors * Serial clock inverted input/output * Full duplex communication: The transmitting and receiving sections are independent, so the SCI can transmit and receive simultaneously. Both sections use double buffering, so continuous data transfer is possible in both the transmit and receive directions. * On-chip baud rate generator with selectable bit rates Rev.2.0, 07/03, page 457 of 960 * Internal or external transmit/receive clock source: baud rate generator (internal) or SCK pin (external) * Four types of interrupts: Transmit-data-empty, transmit-end, receive-data-full, and receiveerror interrupts are requested independently. The transmit-data-empty and receive-data-full interrupts can start the direct memory access controller (DMAC) to transfer data. * Selection of LSB-first or MSB-first transfer (8-bit length) This selection is available regardless of the communication mode. (The descriptions in this section are based on LSB-first transfer.) 15.1.2 Block Diagram Figure 15.1 shows a block diagram of the SCI. Bus interface Module data bus Internal data bus RDR TDR SSR SCR SMR BRR RxD RSR TSR SDCR Transmit/ receive control Baud rate generator P P/4 P/16 P/64 TxD Parity generation Parity check SCK Clock External clock TEI TXI RXI ERI SCI RSR: RDR: TSR: TDR: Receive shift register Receive data register Transmit shift register Transmit data register SMR: SCR: SSR: BRR: SDCR: Serial mode register Serial control register Serial status register Bit rate register Serial direction control register Figure 15.1 SCI Block Diagram Rev.2.0, 07/03, page 458 of 960 15.1.3 Pin Configuration Table 15.1 summarizes the SCI pins by channel. Table 15.1 SCI Pins Channel 0 Pin Name Serial clock pin Receive data pin Transmit data pin 1 Serial clock pin Receive data pin Transmit data pin 2 Serial clock pin Receive data pin Transmit data pin 3 Serial clock pin Receive data pin Transmit data pin 4 Serial clock pin Receive data pin Transmit data pin Abbreviation Input/Output SCK0 RxD0 TxD0 SCK1 RxD1 TxD1 SCK2 RxD2 TxD2 SCK3 RxD3 TxD3 SCK4 RxD4 TxD4 Input/output Input Output Input/output Input Output Input/output Input Output Input/output Input Output Input/output Input Output Function SCI0 clock input/output SCI0 receive data input SCI0 transmit data output SCI1 clock input/output SCI1 receive data input SCI1 transmit data output SCI2 clock input/output SCI2 receive data input SCI2 transmit data output SCI3 clock input/output SCI3 receive data input SCI3 transmit data output SCI4 clock input/output SCI4 receive data input SCI4 transmit data output Note: In the text the pins are referred to as SCK, RxD, and TxD, omitting the channel number. Rev.2.0, 07/03, page 459 of 960 15.1.4 Register Configuration Table 15.2 summarizes the SCI internal registers. These registers select the communication mode (asynchronous or synchronous), specify the data format and bit rate, and control the transmitter and receiver sections. Table 15.2 Registers Channel 0 Name Serial mode register 0 Bit rate register 0 Serial control register 0 Transmit data register 0 Serial status register 0 Receive data register 0 Serial direction control register 0 1 Serial mode register 1 Bit rate register 1 Serial control register 1 Transmit data register 1 Serial status register 1 Receive data register 1 Serial direction control register 1 2 Serial mode register 2 Bit rate register 2 Serial control register 2 Transmit data register 2 Serial status register 2 Receive data register 2 Serial direction control register 2 Abbreviation R/W SMR0 BRR0 SCR0 TDR0 SSR0 RDR0 SDCR0 SMR1 BRR1 SCR1 TDR1 SSR1 RDR1 SDCR1 SMR2 BRR2 SCR2 TDR2 SSR2 RDR2 SDCR2 R/W R/W R/W R/W R/(W) * R R/W R/W R/W R/W R/W R/(W) * R R/W R/W R/W R/W R/W R/(W) * R R/W 1 1 1 Initial Value H'00 H'FF H'00 H'FF H'84 H'00 H'F2 H'00 H'FF H'00 H'FF H'84 H'00 H'F2 H'00 H'FF H'00 H'FF H'84 H'00 H'F2 Address* 2 Access Size 8, 16 H'FFFFF000 H'FFFFF001 H'FFFFF002 H'FFFFF003 H'FFFFF004 H'FFFFF005 H'FFFFF006 H'FFFFF008 H'FFFFF009 H'FFFFF00A H'FFFFF00B H'FFFFF00C H'FFFFF00D H'FFFFF00E H'FFFFF010 H'FFFFF011 H'FFFFF012 H'FFFFF013 H'FFFFF014 H'FFFFF015 H'FFFFF016 8 8, 16 8 8, 16 8 Rev.2.0, 07/03, page 460 of 960 Table 15.2 Registers (cont) Channel 3 Name Serial mode register 3 Bit rate register 3 Serial control register 3 Transmit data register 3 Serial status register 3 Receive data register 3 Serial direction control register 3 4 Serial mode register 4 Bit rate register 4 Serial control register 4 Transmit data register 4 Serial status register 4 Receive data register 4 Serial direction control register 4 Abbreviation R/W SMR3 BRR3 SCR3 TDR3 SSR3 RDR3 SDCR3 SMR4 BRR4 SCR4 TDR4 SSR4 RDR4 SDCR4 R/W R/W R/W R/W R/(W) * R R/W R/W R/W R/W R/W R/(W) * R R/W 1 1 Initial Value H'00 H'FF H'00 H'FF H'84 H'00 H'F2 H'00 H'FF H'00 H'FF H'84 H'00 H'F2 Address* 2 Access Size 8, 16 H'FFFFF018 H'FFFFF019 H'FFFFF01A H'FFFFF01B H'FFFFF01C H'FFFFF01D H'FFFFF01E H'FFFFF020 H'FFFFF021 H'FFFFF022 H'FFFFF023 H'FFFFF024 H'FFFFF025 H'FFFFF026 8 8, 16 8 Notes: In register access, four or five cycles are required for byte access, and eight or nine cycles for word access. *1 Only 0 can be written to clear the flags. *2 Do not access empty addresses. 15.2 15.2.1 Register Descriptions Receive Shift Register (RSR) The receive shift register (RSR) receives serial data. Data input at the RxD pin is loaded into RSR in the order received, LSB (bit 0) first, converting the data to parallel form. When one byte has been received, it is automatically transferred to RDR. The CPU cannot read or write to RSR directly. Bit: 7 6 5 4 3 2 1 0 R/W: -- -- -- -- -- -- -- -- Rev.2.0, 07/03, page 461 of 960 15.2.2 Receive Data Register (RDR) The receive data register (RDR) stores serial receive data. The SCI completes the reception of one byte of serial data by moving the received data from the receive shift register (RSR) into RDR for storage. RSR is then ready to receive the next data. This double buffering allows the SCI to receive data continuously. The CPU can read but not write to RDR. RDR is initialized to H'00 by a power-on reset, and in hardware standby mode and software standby mode. It is not initialized by a manual reset. Bit: 7 6 5 4 3 2 1 0 Initial value: R/W: 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 15.2.3 Transmit Shift Register (TSR) The transmit shift register (TSR) transmits serial data. The SCI loads transmit data from the transmit data register (TDR) into TSR, then transmits the data serially from the TxD pin, LSB (bit 0) first. After transmitting one data byte, the SCI automatically loads the next transmit data from TDR into TSR and starts transmitting again. If the TDRE bit of SSR is 1, however, the SCI does not load the TDR contents into TSR. The CPU cannot read or write to TSR directly. Bit: 7 6 5 4 3 2 1 0 R/W: -- -- -- -- -- -- -- -- Rev.2.0, 07/03, page 462 of 960 15.2.4 Transmit Data Register (TDR) The transmit data register (TDR) is an 8-bit register that stores data for serial transmission. When the SCI detects that the transmit shift register (TSR) is empty, it moves transmit data written in TDR into TSR and starts serial transmission. Continuous serial transmission is possible by writing the next transmit data in TDR during serial transmission from TSR. The CPU can always read and write to TDR. TDR is initialized to H'FF by a power-on reset, and in hardware standby mode and software standby mode. It is not initialized by a manual reset. Bit: 7 6 5 4 3 2 1 0 Initial value: R/W: 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 15.2.5 Serial Mode Register (SMR) The serial mode register (SMR) is an 8-bit register that specifies the SCI serial communication format and selects the clock source for the baud rate generator. The CPU can always read and write to SMR. SMR is initialized to H'00 by a power-on reset, and in hardware standby mode and software standby mode. It is not initialized by a manual reset. Bit: 7 C/A Initial value: R/W: 0 R/W 6 CHR 0 R/W 5 PE 0 R/W 4 O/E 0 R/W 3 STOP 0 R/W 2 MP 0 R/W 1 CKS1 0 R/W 0 CKS0 0 R/W * Bit 7--Communication Mode (C/A): Selects whether the SCI operates in asynchronous or synchronous mode. Bit 7: C/A A 0 1 Description Asynchronous mode Synchronous mode (Initial value) Rev.2.0, 07/03, page 463 of 960 * Bit 6--Character Length (CHR): Selects 7-bit or 8-bit data in asynchronous mode. In synchronous mode, the data length is always eight bits, regardless of the CHR setting. Bit 6: CHR 0 1 Description Eight-bit data Seven-bit data When 7-bit data is selected, the MSB (bit 7) of the transmit data register is not transmitted. LSB-first/MSB-first selection is not available. (Initial value) * Bit 5--Parity Enable (PE): Selects whether to add a parity bit to transmit data and to check the parity of receive data, in asynchronous mode. In synchronous mode and when using a multiprocessor format, a parity bit is neither added nor checked, regardless of the PE bit setting. Bit 5: PE 0 1 Description Parity bit not added or checked Parity bit added and checked When PE is set to 1, an even or odd parity bit is added to transmit data, depending on the parity mode (O/E bit) setting. Receive data parity is checked according to the even/odd (O/E bit) setting. (Initial value) * Bit 4--Parity Mode (O/E): Selects even or odd parity when parity bits are added and checked. The O/E setting is used only in asynchronous mode and only when the parity enable bit (PE) is set to 1 to enable parity addition and checking. The O/E setting is invalid in synchronous mode, in asynchronous mode when parity bit addition and checking is disabled, and when using a multiprocessor format. Bit 4: O/E E 0 Description Even parity (Initial value) If even parity is selected, the parity bit is added to transmit data to make an even number of 1s in the transmitted character and parity bit combined. Receive data is checked to see if it has an even number of 1s in the received character and parity bit combined. 1 Odd parity If odd parity is selected, the parity bit is added to transmit data to make an odd number of 1s in the transmitted character and parity bit combined. Receive data is checked to see if it has an odd number of 1s in the received character and parity bit combined. Rev.2.0, 07/03, page 464 of 960 * Bit 3--Stop Bit Length (STOP): Selects one or two bits as the stop bit length in asynchronous mode. This setting is used only in asynchronous mode. It is ignored in synchronous mode because no stop bits are added. In receiving, only the first stop bit is checked, regardless of the STOP bit setting. If the second stop bit is 1, it is treated as a stop bit, but if the second stop bit is 0, it is treated as the start bit of the next incoming character. Bit 3: STOP 0 Description One stop bit (Initial value) In transmitting, a single bit of 1 is added at the end of each transmitted character. 1 Two stop bits In transmitting, two 1-bits are added at the end of each transmitted character. * Bit 2--Multiprocessor Mode (MP): Selects multiprocessor format. When multiprocessor format is selected, settings of the parity enable (PE) and parity mode (O/E) bits are ignored. The MP bit setting is used only in asynchronous mode; it is ignored in synchronous mode. For the multiprocessor communication function, see section 15.3.3, Multiprocessor Communication. Bit 2: MP 0 1 Description Multiprocessor function disabled Multiprocessor format selected (Initial value) * Bits 1 and 0--Clock Select 1 and 0 (CKS1, CKS0): These bits select the internal clock source of the on-chip baud rate generator. Four clock sources are available: P, P/4, P/16, or P/64 (P is the peripheral clock). For further information on the clock source, bit rate register settings, and baud rate, see section 15.2.8, Bit Rate Register (BRR). Bit 1: CKS1 0 Bit 0: CKS0 0 1 1 0 1 Description P P/4 P/16 P/64 (Initial value) Rev.2.0, 07/03, page 465 of 960 15.2.6 Serial Control Register (SCR) The serial control register (SCR) operates the SCI transmitter/receiver, selects the serial clock output in asynchronous mode, enables/disables interrupt requests, and selects the transmit/receive clock source. The CPU can always read and write to SCR. SCR is initialized to H'00 by a poweron reset, and in hardware standby mode and software standby mode. It is not initialized by a manual reset. Bit: 7 TIE Initial value: R/W: 0 R/W 6 RIE 0 R/W 5 TE 0 R/W 4 RE 0 R/W 3 MPIE 0 R/W 2 TEIE 0 R/W 1 CKE1 0 R/W 0 CKE0 0 R/W * Bit 7--Transmit Interrupt Enable (TIE): Enables or disables the transmit-data-empty interrupt (TXI) requested when the transmit data register empty bit (TDRE) in the serial status register (SSR) is set to 1 by transfer of serial transmit data from TDR to TSR. Bit 7: TIE 0 Description Transmit-data-empty interrupt request (TXI) is disabled (Initial value) The TXI interrupt request can be cleared by reading TDRE after it has been set to 1, then clearing TDRE to 0, or by clearing TIE to 0. 1 Transmit-data-empty interrupt request (TXI) is enabled * Bit 6--Receive Interrupt Enable (RIE): Enables or disables the receive-data-full interrupt (RXI) requested when the receive data register full bit (RDRF) in the serial status register (SSR) is set to 1 by transfer of serial receive data from RSR to RDR. It also enables or disables receive-error interrupt (ERI) requests. Bit 6: RIE 0 Description Receive-data-full interrupt (RXI) and receive-error interrupt (ERI) requests are disabled (Initial value) RXI and ERI interrupt requests can be cleared by reading the RDRF flag or error flag (FER, PER, or ORER) after it has been set to 1, then clearing the flag to 0, or by clearing RIE to 0. 1 Receive-data-full interrupt (RXI) and receive-error interrupt (ERI) requests are enabled Rev.2.0, 07/03, page 466 of 960 * Bit 5--Transmit Enable (TE): Enables or disables the SCI serial transmitter. Bit 5: TE 0 Description Transmitter disabled (Initial value) The transmit data register empty bit (TDRE) in the serial status register (SSR) is locked at 1. 1 Transmitter enabled Serial transmission starts when the transmit data register empty (TDRE) bit in the serial status register (SSR) is cleared to 0 after writing of transmit data into TDR. Select the transmit format in SMR before setting TE to 1. * Bit 4--Receive Enable (RE): Enables or disables the SCI serial receiver. Bit 4: RE 0 Description Receiver disabled (Initial value) Clearing RE to 0 does not affect the receive flags (RDRF, FER, PER, ORER). These flags retain their previous values. 1 Receiver enabled Serial reception starts when a start bit is detected in asynchronous mode, or synchronous clock input is detected in synchronous mode. Select the receive format in SMR before setting RE to 1. Rev.2.0, 07/03, page 467 of 960 * Bit 3--Multiprocessor Interrupt Enable (MPIE): Enables or disables multiprocessor interrupts. The MPIE setting is used only in asynchronous mode, and only if the multiprocessor mode bit (MP) in the serial mode register (SMR) is set to 1 during reception. The MPIE setting is ignored in synchronous mode or when the MP bit is cleared to 0. Bit 3: MPIE 0 Description Multiprocessor interrupts are disabled (normal receive operation) (Initial value) [Clearing conditions] * * 1 When the MPIE bit is cleared to 0 When data with MPB = 1 is received Multiprocessor interrupts are enabled. Receive-data-full interrupt requests (RXI), receive-error interrupt requests (ERI), and setting of the RDRF, FER, and ORER status flags in the serial status register (SSR) are disabled until data with the multiprocessor bit set to 1 is received. The SCI does not transfer receive data from RSR to RDR, does not detect receive errors, and does not set the RDRF, FER, and ORER flags in the serial status register (SSR). When it receives data that includes MPB = 1, MPB is set to 1, and the SCI automatically clears MPIE to 0, generates RXI and ERI interrupts (if the TIE and RIE bits in SCR are set to 1), and allows the FER and ORER bits to be set. * Bit 2--Transmit-End Interrupt Enable (TEIE): Enables or disables the transmit-end interrupt (TEI) requested if TDR does not contain valid transmit data when the MSB is transmitted. Bit 2: TEIE 0 1 Description Transmit-end interrupt (TEI) requests are disabled* Transmit-end interrupt (TEI) requests are enabled* (Initial value) Note: * The TEI request can be cleared by reading the TDRE bit in the serial status register (SSR) after it has been set to 1, then clearing TDRE to 0 and clearing the transmit end (TEND) bit to 0; or by clearing the TEIE bit to 0. Rev.2.0, 07/03, page 468 of 960 * Bits 1 and 0--Clock Enable 1 and 0 (CKE1, CKE0): These bits select the SCI clock source and enable or disable clock output from the SCK pin. Depending on the combination of CKE1 and CKE0, the SCK pin can be used for serial clock output, or serial clock input. Select the SCK pin function by using the pin function controller (PFC). The CKE0 setting is valid only in asynchronous mode, and only when the SCI is internally clocked (CKE1 = 0). The CKE0 setting is ignored in synchronous mode, or when an external clock source is selected (CKE1 = 1). For further details on selection of the SCI clock source, see table 15.9 in section 15.3, Operation. Bit 1: Bit 0: 1 CKE1 CKE0 Description* 0 0 Asynchronous mode Synchronous mode 0 1 Asynchronous mode Synchronous mode 1 0 Asynchronous mode Synchronous mode 1 1 Asynchronous mode Synchronous mode Internal clock, SCK pin used for input pin (input signal 2 is ignored) or output pin (output level is undefined)* Internal clock, SCK pin used for synchronous clock *2 output Internal clock, SCK pin used for clock output* 3 Internal clock, SCK pin used for synchronous clock output External clock, SCK pin used for clock input* 4 External clock, SCK pin used for synchronous clock input External clock, SCK pin used for clock input* 4 External clock, SCK pin used for synchronous clock input Notes: *1 The SCK pin is multiplexed with other functions. Use the pin function controller (PFC) to select the SCK function for this pin, as well as the I/O direction. *2 Initial value. *3 The output clock frequency is the same as the bit rate. *4 The input clock frequency is 16 times the bit rate. Rev.2.0, 07/03, page 469 of 960 15.2.7 Serial Status Register (SSR) The serial status register (SSR) is an 8-bit register containing multiprocessor bit values, and status flags that indicate the SCI operating status. The CPU can always read and write to SSR, but cannot write 1 in the status flags (TDRE, RDRF, ORER, PER, and FER). These flags can be cleared to 0 only if they have first been read (after being set to 1). Bits 2 (TEND) and 1 (MPB) are read-only bits that cannot be written. SSR is initialized to H'84 by a power-on reset, and in hardware standby mode and software standby mode. It is not initialized by a manual reset. Bit: 7 TDRE Initial value: R/W: 1 R/(W)* 6 RDRF 0 R/(W)* 5 ORER 0 R/(W)* 4 FER 0 R/(W)* 3 PER 0 R/(W)* 2 TEND 1 R 1 MPB 0 R 0 MPBT 0 R/W Note: * The only value that can be written is a 0 to clear the flag. * Bit 7--Transmit Data Register Empty (TDRE): Indicates that the SCI has loaded transmit data from TDR into TSR and new serial transmit data can be written in TDR. Bit 7: TDRE 0 Description TDR contains valid transmit data [Clearing conditions] * * 1 When 0 is written to TDRE after reading TDRE = 1 When the DMAC writes data in TDR (Initial value) TDR does not contain valid transmit data [Setting conditions] * * * Power-on reset, hardware standby mode, or software standby mode When the TE bit in SCR is 0 When data is transferred from TDR to TSR, enabling new data to be written in TDR Rev.2.0, 07/03, page 470 of 960 * Bit 6--Receive Data Register Full (RDRF): Indicates that RDR contains received data. Bit 6: RDRF 0 Description RDR does not contain valid receive data [Clearing conditions] * * * 1 Power-on reset, hardware standby mode, or software standby mode When 0 is written to RDRF after reading RDRF = 1 When the DMAC reads data from RDR (Initial value) RDR contains valid received data [Setting condition] RDRF is set to 1 when serial data is received normally and transferred from RSR to RDR Note: RDR and RDRF are not affected by detection of receive errors or by clearing of the RE bit to 0 in the serial control register. They retain their previous contents. If RDRF is still set to 1 when reception of the next data ends, an overrun error (ORER) occurs and the receive data is lost. * Bit 5--Overrun Error (ORER): Indicates that data reception ended abnormally due to an overrun error. Bit 5: ORER 0 Description Receiving is in progress or has ended normally (Initial value) Clearing the RE bit to 0 in the serial control register does not affect the ORER bit, which retains its previous value. [Clearing conditions] * * 1 Power-on reset, hardware standby mode, or software standby mode When 0 is written to ORER after reading ORER = 1 A receive overrun error occurred RDR continues to hold the data received before the overrun error, so subsequent receive data is lost. Serial receiving cannot continue while ORER is set to 1. In synchronous mode, serial transmitting is disabled. [Setting condition] ORER is set to 1 if reception of the next serial data ends when RDRF is set to 1 Rev.2.0, 07/03, page 471 of 960 * Bit 4--Framing Error (FER): Indicates that data reception ended abnormally due to a framing error in asynchronous mode. Bit 4: FER 0 Description Receiving is in progress or has ended normally (Initial value) Clearing the RE bit to 0 in the serial control register does not affect the FER bit, which retains its previous value. [Clearing conditions] * * 1 Power-on reset, hardware standby mode, or software standby mode When 0 is written to FER after reading FER = 1 A receive framing error occurred When the stop bit length is two bits, only the first bit is checked to see if it is a 1. The second stop bit is not checked. When a framing error occurs, the SCI transfers the receive data into RDR but does not set RDRF. Serial receiving cannot continue while FER is set to 1. In synchronous mode, serial transmitting is also disabled. [Setting condition] FER is set to 1 if the stop bit at the end of receive data is checked and found to be 0 * Bit 3--Parity Error (PER): Indicates that data reception (with parity) ended abnormally due to a parity error in asynchronous mode. Bit 3: PER 0 Description Receiving is in progress or has ended normally (Initial value) Clearing the RE bit to 0 in the serial control register does not affect the PER bit, which retains its previous value. [Clearing conditions] * * 1 Power-on reset, hardware standby mode, or software standby mode When 0 is written to PER after reading PER = 1 A receive parity error occurred When a parity error occurs, the SCI transfers the receive data into RDR but does not set RDRF. Serial receiving cannot continue while PER is set to 1. [Setting condition] PER is set to 1 if the number of 1s in receive data, including the parity bit, does not match the even or odd parity setting of the parity mode bit (O/E) in the serial mode register (SMR) Rev.2.0, 07/03, page 472 of 960 * Bit 2--Transmit End (TEND): Indicates that when the last bit of a serial character was transmitted, TDR did not contain valid data, so transmission has ended. TEND is a read-only bit and cannot be written. Bit 2: TEND 0 Description Transmission is in progress [Clearing conditions] * * 1 When 0 is written to TDRE after reading TDRE = 1 When the DMAC writes data in TDR (Initial value) End of transmission [Setting conditions] * * * Power-on reset, hardware standby mode, or software standby mode When the TE bit in SCR is 0 If TDRE = 1 when the last bit of a one-byte serial transmit character is transmitted * Bit 1--Multiprocessor Bit (MPB): Stores the value of the multiprocessor bit in receive data when a multiprocessor format is selected for receiving in asynchronous mode. MPB is a readonly bit and cannot be written. Bit 1: MPB 0 Description Multiprocessor bit value in receive data is 0 (Initial value) If RE is cleared to 0 when a multiprocessor format is selected, the MPB retains its previousvalue. 1 Multiprocessor bit value in receive data is 1 * Bit 0--Multiprocessor Bit Transfer (MPBT): Stores the value of the multiprocessor bit added to transmit data when a multiprocessor format is selected for transmitting in asynchronous mode. The MPBT setting is ignored in synchronous mode, when a multiprocessor format is not selected, or when the SCI is not transmitting. Bit 0: MPBT 0 1 Description Multiprocessor bit value in transmit data is 0 Multiprocessor bit value in transmit data is 1 (Initial value) Rev.2.0, 07/03, page 473 of 960 15.2.8 Bit Rate Register (BRR) The bit rate register (BRR) is an 8-bit register that, together with the baud rate generator clock source selected by the CKS1 and CKS0 bits in the serial mode register (SMR), determines the serial transmit/receive bit rate. The CPU can always read and write to BRR. BRR is initialized to H'FF by a power-on reset, and in hardware standby mode and software standby mode. It is not initialized by a manual reset. Each channel has independent baud rate generator control, so different values can be set for each channel. Bit: 7 6 5 4 3 2 1 0 Initial value: R/W: 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W Table 15.3 lists examples of BRR settings in the asynchronous mode; table 15.4 lists examples of BBR settings in the clock synchronous mode. The BRR setting is calculated as follows: Asynchronous mode: N= P 64 x 22n-1 x B x 106 - 1 Synchronous mode: N= P 64 x 22n-1 x B x 106 - 1 B: Bit rate (bits/s) N: Baud rate generator BRR setting (0 N 255) P: Peripheral module operating frequency (MHz) (1/2 of system clock) n: Baud rate generator input clock (n = 0 to 3) (See the following table for the clock sources and value of n.) SMR Settings n 0 1 2 3 Clock Source P P/4 P/16 P/64 CKS1 0 0 1 1 CKS2 0 1 0 1 Rev.2.0, 07/03, page 474 of 960 The bit rate error in asynchronous mode is calculated as follows: P x 106 Error (%) = - 1 x 100 (N + 1) x B x 64 x 22n-1 Table 15.3 Bit Rates and BRR Settings in Asynchronous Mode P (MHz) Bit Rate (Bits/s) 110 150 300 600 1200 2400 4800 9600 14400 19200 28800 31250 38400 10 n 2 2 2 1 1 0 0 0 0 0 0 0 0 N 177 129 64 129 64 129 64 32 21 15 10 9 7 Error (%) -0.25 0.16 0.16 0.16 0.16 0.16 0.16 -1.36 -1.36 1.73 -1.36 0.00 1.73 n 2 2 2 1 1 0 0 0 0 0 0 0 0 N 195 143 71 143 71 143 71 35 23 19 11 10 8 11.0592 Error (%) 0.19 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.54 0.00 n 2 2 2 1 1 0 0 0 0 0 0 0 0 N 212 155 77 155 77 155 77 28 25 19 12 11 9 12 Error (%) 0.03 0.16 0.16 0.16 0.16 0.16 0.16 0.16 0.16 -2.34 0.16 0.00 -2.34 Rev.2.0, 07/03, page 475 of 960 Table 15.3 Bit Rates and BRR Settings in Asynchronous Mode (cont) P (MHz) Bit Rate (Bits/s) 110 150 300 600 1200 2400 4800 9600 14400 19200 28800 31250 38400 12.288 n 2 2 2 1 1 0 0 0 0 0 0 0 0 N 217 159 79 159 79 159 79 39 26 19 12 11 9 Error (%) 0.08 0.00 0.00 0.00 0.00 0.00 0.00 0.00 -1.23 0.00 2.56 2.40 0.00 n 2 2 2 1 1 0 0 0 0 0 0 0 0 N 248 181 90 181 90 181 90 45 29 22 14 13 10 14 Error (%) -0.17 0.16 0.16 0.16 0.16 0.16 0.16 -0.93 1.27 -0.93 1.27 0.00 3.57 n 3 2 2 1 1 0 0 0 0 0 0 0 0 N 64 191 95 191 95 191 95 47 31 23 15 14 11 14.7456 Error (%) 0.70 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 -1.70 0.00 Rev.2.0, 07/03, page 476 of 960 Table 15.3 Bit Rates and BRR Settings in Asynchronous Mode (cont) P (MHz) Bit Rate (Bits/s) 110 150 300 600 1200 2400 4800 9600 14400 19200 28800 31250 38400 16 n 3 2 2 1 1 0 0 0 0 0 0 0 0 N 70 207 103 207 103 207 103 51 34 25 16 15 12 Error (%) 0.03 0.16 0.16 0.16 0.16 0.16 0.16 0.16 -0.79 0.16 2.12 0.00 0.16 n 3 2 2 1 1 0 0 0 0 0 0 0 0 N 75 223 111 223 111 223 111 55 36 27 18 16 13 17.2032 Error (%) 0.48 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.90 0.00 -1.75 1.20 0.00 n 3 2 2 1 1 0 0 0 0 0 0 0 0 N 79 233 116 233 116 233 116 58 38 28 19 17 14 18 Error (%) -0.12 0.16 0.16 0.16 0.16 0.16 0.16 -0.69 0.16 1.02 -2.34 0.00 -2.34 Rev.2.0, 07/03, page 477 of 960 Table 15.3 Bit Rates and BRR Settings in Asynchronous Mode (cont) (MHz) Bit Rate (Bits/s) 110 150 300 600 1200 2400 4800 9600 14400 19200 28800 31250 38400 18.432 n 3 2 2 1 1 0 0 0 0 0 0 0 0 N 81 239 119 239 119 239 119 59 39 29 19 17 14 Error (%) -0.22 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 2.40 0.00 n 3 2 2 1 1 0 0 0 0 0 0 0 0 N 86 255 127 255 127 255 127 63 42 31 20 19 15 19.6608 Error (%) 0.31 0.00 0.00 0.00 0.00 0.00 0.00 0.00 -0.78 0.00 1.59 -1.70 0.00 n 3 3 2 2 1 1 0 0 0 0 0 0 0 N 88 64 129 64 129 64 129 64 42 32 21 19 15 20 Error (%) -0.25 0.16 0.16 0.16 0.16 0.16 0.16 0.16 0.94 -1.36 -1.36 0.00 1.73 Rev.2.0, 07/03, page 478 of 960 Table 15.4 Bit Rates and BRR Settings in Synchronous Mode P (MHz) Bit Rate (Bits/s) 250 500 1k 2.5 k 5k 10 k 25 k 50 k 100 k 250 k 500 k 1M 2.5 M 5M Note: Settings with an error of 1% or less are recommended. Legend Blank: No setting available --: Setting possible, but error occurs *: Continuous transmission/reception not possible 0 0* 10 n -- -- -- 1 1 0 0 0 0 0 0 N -- -- -- 249 124 249 99 49 24 9 4 n 3 3 2 2 1 1 0 0 0 0 0 0 0 12 N 187 93 187 74 149 74 119 59 29 11 5 2 0* n 3 3 2 2 1 1 0 0 0 0 0 0 -- 16 N 249 124 249 99 199 99 159 79 39 15 7 3 -- -- -- 2 2 1 1 0 0 0 0 0 0 0 -- -- 124 249 124 199 99 49 19 9 4 1 0* n 20 N Table 15.5 indicates the maximum bit rates in asynchronous mode when the baud rate generator is being used for various frequencies. Tables 15.6 and 15.7 show the maximum rates for external clock input. Rev.2.0, 07/03, page 479 of 960 Table 15.5 Maximum Bit Rates for Various Frequencies with Baud Rate Generator (Asynchronous Mode) Settings P (MHz) 10 11.0592 12 12.288 14 14.7456 16 17.2032 18 18.432 19.6608 20 Maximum Bit Rate (Bits/s) 312500 345600 375000 384000 437500 460800 500000 537600 562500 576000 614400 625000 n 0 0 0 0 0 0 0 0 0 0 0 0 N 0 0 0 0 0 0 0 0 0 0 0 0 Table 15.6 Maximum Bit Rates during External Clock Input (Asynchronous Mode) P (MHz) 10 11.0592 12 12.288 14 14.7456 16 17.2032 18 18.432 19.6608 20 External Input Clock (MHz) 2.5000 2.7648 3.0000 3.0720 3.5000 3.6864 4.0000 4.3008 4.5000 4.6080 4.9152 5.0000 Maximum Bit Rate (Bits/s) 156250 172800 187500 192000 218750 230400 250000 268800 281250 288000 307200 312500 Rev.2.0, 07/03, page 480 of 960 Table 15.7 Maximum Bit Rates during External Clock Input (Clock Synchronous Mode) P (MHz) 10 12 14 16 18 20 External Input Clock (MHz) 1.6667 2.0000 2.3333 2.6667 3.0000 3.3333 Maximum Bit Rate (Bits/s) 1666666.7 2000000.0 2333333.3 2666666.7 3000000.0 3333333.3 15.2.9 Serial Direction Control Register (SDCR) Bit: 7 -- Initial value: R/W: 1 R 6 -- 1 R 5 -- 1 R 4 -- 1 R 3 DIR 0 R/W 2 -- 0 R 1 -- 1 R 0 -- 0 R The DIR bit in the serial direction control register (SDCR) selects LSB-first or MSB-first transfer. With an 8-bit data length, LSB-first/MSB-first selection is available regardless of the communication mode. With a 7-bit data length, LSB-first transfer must be selected. The description in this section assumes LSB-first transfer. SDCR is initialized to H'F2 by a power-on reset, and in the hardware standby mode and software standby mode. It is not initialized by a manual reset. * Bits 7-4--Reserved: The write value should always be 1. If 0 is written to these bits, correct operation cannot be guaranteed. * Bit 3--Data Transfer Direction (DIR): Selects the serial/parallel conversion format. Valid for an 8-bit transmit/receive format. Bit 3: DIR 0 1 Description TDR contents are transmitted in LSB-first order Receive data is stored in RDR in LSB-first order TDR contents are transmitted in MSB-first order Receive data is stored in RDR in MSB-first order (Initial value) * Bit 2--Reserved: The write value should always be 0. If 1 is written to this bit, correct operation cannot be guaranteed. * Bit 1--Reserved: This bit is always read as 1, and cannot be modified. Rev.2.0, 07/03, page 481 of 960 * Bit 0--Reserved: The write value should always be 0. If 1 is written to this bit, correct operation cannot be guaranteed. 15.2.10 Inversion of SCK Pin Signal The signal input from the SCK pin and the signal output from the SCK pin can be inverted by means of a port control register setting. See section 20, Pin function Controller (PFC), for details. 15.3 15.3.1 Operation Overview For serial communication, the SCI has an asynchronous mode in which characters are synchronized individually, and a synchronous mode in which communication is synchronized with clock pulses. Asynchronous synchronous mode and the transmission format are selected in the serial mode register (SMR), as shown in table 15.8. The SCI clock source is selected by the C/A bit in the serial mode register (SMR) and the CKE1 and CKE0 bits in the serial control register (SCR), as shown in table 15.9. Asynchronous Mode: * Data length is selectable: seven or eight bits. * Parity and multiprocessor bits are selectable, as well as the stop bit length (one or two bits). These selections determine the transmit/receive format and character length. * In receiving, it is possible to detect framing errors (FER), parity errors (PER), overrun errors (ORER), and the break state. * An internal or external clock can be selected as the SCI clock source. When an internal clock is selected, the SCI operates using the on-chip baud rate generator clock, and can output a clock with a frequency matching the bit rate. When an external clock is selected, the external clock input must have a frequency 16 times the bit rate. (The on-chip baud rate generator is not used.) Synchronous Mode: * The communication format has a fixed 8-bit data length. * In receiving, it is possible to detect overrun errors (ORER). * An internal or external clock can be selected as the SCI clock source. When an internal clock is selected, the SCI operates using the on-chip baud rate generator clock, and outputs a serial clock signal to external devices. When an external clock is selected, the SCI operates on the input serial clock. The on-chip baud rate generator is not used. Rev.2.0, 07/03, page 482 of 960 Table 15.8 Serial Mode Register Settings and SCI Communication Formats SMR Settings Mode Asynchronous Bit 7 C/A A 0 Bit 6 CHR 0 Bit 5 PE 0 Bit 2 MP 0 Bit 3 STOP 0 1 1 0 1 1 0 0 1 1 0 1 Asynchronous (multiprocessor format) 0 * * 1 * * Synchronous 1 * * * 1 0 1 0 1 * 8-bit Absent 7-bit 8-bit Absent Present Present 7-bit Absent Present SCI Communication Format Data Length 8-bit Parity Bit Multipro- Stop Bit cessor Bit Length 1 bit 2 bits 1 bit 2 bits 1 bit 2 bits 1 bit 2 bits 1 bit 2 bits 1 bit 2 bits None Absent Absent Note: Asterisks (*) in the table indicate donit-care bits. Table 15.9 SMR and SCR Settings and SCI Clock Source Selection SMR Mode Bit 7 C/A A SCR Settings Bit 1 CKE1 0 Bit 0 CKE0 0 1 1 0 1 Synchronous 1 0 0 1 1 0 1 External Internal External SCI Transmit/Receive Clock Clock Source SCK Pin Function* Internal SCI does not use the SCK pin Outputs a clock with frequency matching the bit rate Inputs a clock with frequency 16 times the bit rate Outputs the serial clock or the inverted serial clock Inputs the serial clock or the inverted serial clock Asynchronous 0 Note: * Select the function in combination with the pin function controller (PFC). Rev.2.0, 07/03, page 483 of 960 15.3.2 Operation in Asynchronous Mode In asynchronous mode, each transmitted or received character begins with a start bit and ends with a stop bit. Serial communication is synchronized one character at a time. The transmitting and receiving sections of the SCI are independent, so full duplex communication is possible. The transmitter and receiver are both double buffered, so data can be written and read while transmitting and receiving are in progress, enabling continuous transmitting and receiving. Figure 15.2 shows the general format of asynchronous serial communication. In asynchronous serial communication, the communication line is normally held in the marking (high) state. The SCI monitors the line and starts serial communication when the line goes to the space (low) state, indicating a start bit. One serial character consists of a start bit (low), data (LSB first), parity bit (high or low), and stop bit (high), in that order. When receiving in asynchronous mode, the SCI synchronizes on the falling edge of the start bit. The SCI samples each data bit on the eighth pulse of a clock with a frequency 16 times the bit rate. Receive data is latched at the center of each bit. Idling (marking) 1 0/1 Parity bit Transmit/receive data 1 bit 7 or 8 bits 1 or no bit 1 or 2 bits 1 Stop bit 1 1 Serial data 0 Start bit (LSB) D0 D1 D2 D3 D4 D5 D6 (MSB) D7 One unit of communication data (character or frame) Figure 15.2 Data Format in Asynchronous Communication (Example: 8-bit Data with Parity and Two Stop Bits) Rev.2.0, 07/03, page 484 of 960 Transmit/Receive Formats: Table 15.10 shows the 12 communication formats that can be selected in asynchronous mode. The format is selected by settings in the serial mode register (SMR). Table 15.10 Serial Communication Formats (Asynchronous Mode) SMR Bits CHR PE 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 0 1 1 -- -- -- -- MP 0 0 0 0 0 0 0 0 1 1 1 1 STOP 0 1 0 1 0 1 0 1 0 1 0 1 1 START START START START START START START START START START START START Serial Transmit/Receive Format and Frame Length 2 3 4 5 6 7 8 9 10 STOP STOP STOP P P STOP STOP STOP P P STOP STOP STOP MPB MPB MPB MPB STOP STOP STOP STOP STOP STOP STOP STOP STOP 11 12 8-bit data 8-bit data 8-bit data 8-bit data 7-bit data 7-bit data 7-bit data 7-bit data 8-bit data 8-bit data 7-bit data 7-bit data --: Don't care bits. Notes: START: Start bit STOP: Stop bit P: Parity bit MPB: Multiprocessor bit Clock: An internal clock generated by the on-chip baud rate generator or an external clock input from the SCK pin can be selected as the SCI transmit/receive clock. The clock source is selected by the C/A bit in the serial mode register (SMR) and bits CKE1 and CKE0 in the serial control register (SCR) (table 15.9). When an external clock is input at the SCK pin, it must have a frequency equal to 16 times the desired bit rate. Rev.2.0, 07/03, page 485 of 960 When the SCI operates on an internal clock, it can output a clock signal at the SCK pin. The frequency of this output clock is equal to the bit rate. The phase is aligned as in figure 15.3 so that the rising edge of the clock occurs at the center of each transmit data bit. 0 D0 D1 D2 D3 D4 D5 D6 D7 0/1 1 1 1 frame Figure 15.3 Output Clock and Communication Data Phase Relationship (Asynchronous Mode) Data Transmit/Receive Operation SCI Initialization (Asynchronous Mode): Before transmitting or receiving, clear the TE and RE bits to 0 in the serial control register (SCR), then initialize the SCI as follows. When changing the operation mode or communication format, always clear the TE and RE bits to 0 before following the procedure given below. Clearing TE to 0 sets TDRE to 1 and initializes the transmit shift register (TSR). Clearing RE to 0, however, does not initialize the RDRF, PER, FER, and ORER flags and receive data register (RDR), which retain their previous contents. When an external clock is used, the clock should not be stopped during initialization or subsequent operation. SCI operation becomes unreliable if the clock is stopped. Figure 15.4 is a sample flowchart for initializing the SCI. The procedure is as follows (the steps correspond to the numbers in the flowchart): 1. Select the clock source in the serial control register (SCR). Leave RIE, TIE, TEIE, MPIE, TE, and RE cleared to 0. If clock output is selected in asynchronous mode, clock output starts immediately after the setting is made in SCR. 2. Select the communication format in the serial mode register (SMR) and serial direction control register (SDCR). 3. Write the value corresponding to the bit rate in the bit rate register (BRR) (unless an external clock is used). 4. Wait for at least the interval required to transmit or receive one bit, then set TE or RE in the serial control register (SCR) to 1.* Also set RIE, TIE, TEIE and MPIE as necessary. Setting TE or RE enables the SCI to use the TxD or RxD pin. Note: * In simultaneous transmit/receive operation, the TE bit and RE bit must be cleared to 0 or set to 1 simultaneously. Rev.2.0, 07/03, page 486 of 960 Initialize Clear TE and RE bits to 0 in SCR Set CKE1 and CKE0 bits in SCR (TE and RE bits are 0) Select transmit/receive format in SMR and SDCR Set value in BRR Wait No 1 2 3 1-bit interval elapsed? Yes Set TE or RE to 1 in SCR; Set RIE, TIE, TEIE, and MPIE as necessary 4 End Figure 15.4 Sample Flowchart for SCI Initialization Transmitting Serial Data (Asynchronous Mode): Figure 15.5 shows a sample flowchart for transmitting serial data. The procedure is as follows (the steps correspond to the numbers in the flowchart): 1. SCI initialization: Set the TxD pin using the PFC. 2. SCI status check and transmit data write: Read the serial status register (SSR), check that the TDRE bit is 1, then write transmit data in the transmit data register (TDR) and clear TDRE to 0. 3. Continue transmitting serial data: Read the TDRE bit to check whether it is safe to write (if it reads 1); if so, write data in TDR, then clear TDRE to 0. When the DMAC is started by a transmit-data-empty interrupt request (TXI) in order to write data in TDR, the TDRE bit is checked and cleared automatically. 4. To output a break at the end of serial transmission, first clear the port data register (DR) to 0, then clear the TE bit to 0 in SCR and use the PFC to establish the TxD pin as an output port. Rev.2.0, 07/03, page 487 of 960 Initialization Start of transmission 1 Read TDRE bit in SSR 2 No TDRE = 1? Yes Write transmit data to TDR and clear TDRE bit in SSR to 0 3 All data transmitted? Yes Read TEND bit in SSR No TEND = 1? Yes Output break signal? 4 Yes Clear port DR to 0 Clear TE bit in SCR to 0; select theTxD pin as an output port with the PFC No No End of transmission Figure 15.5 Sample Flowchart for Transmitting Serial Data Rev.2.0, 07/03, page 488 of 960 In transmitting serial data, the SCI operates as follows: 1. The SCI monitors the TDRE bit in SSR. When TDRE is cleared to 0, the SCI recognizes that the transmit data register (TDR) contains new data, and loads this data from TDR into the transmit shift register (TSR). 2. After loading the data from TDR into TSR, the SCI sets the TDRE bit to 1 and starts transmitting. If the transmit-data-empty interrupt enable bit (TIE) is set to 1 in SCR, the SCI requests a transmit-data-empty interrupt (TXI) at this time. Serial transmit data is transmitted in the following order from the TxD pin: a. Start bit: one 0-bit is output. b. Transmit data: seven or eight bits of data are output, LSB first. c. Parity bit or multiprocessor bit: one parity bit (even or odd parity) or one multiprocessor bit is output. Formats in which neither a parity bit nor a multiprocessor bit is output can also be selected. d. Stop bit: one or two 1-bits (stop bits) are output. e. Marking: output of 1-bits continues until the start bit of the next transmit data. 3. The SCI checks the TDRE bit when it outputs the stop bit. If TDRE is 0, the SCI loads new data from TDR into TSR, outputs the stop bit, then begins serial transmission of the next frame. If TDRE is 1, the SCI sets the TEND bit to 1 in SSR, outputs the stop bit, then continues output of 1-bits (marking). If the transmit-end interrupt enable bit (TEIE) in SCR is set to 1, a transmit-end interrupt (TEI) is requested. Figure 15.6 shows an example of SCI transmit operation in asynchronous mode. Rev.2.0, 07/03, page 489 of 960 1 Serial data Start bit 0 D0 D1 Data D7 Parity Stop Start bit bit bit 0/1 1 0 D0 Data D1 Parity Stop bit bit D7 0/1 1 1 Idling (marking) TDRE TEND TXI TXI interrupt interrupt handler writes request data in TDR and clears TDRE to 0 1 frame TXI interrupt request TEI interrupt request Figure 15.6 SCI Transmit Operation in Asynchronous Mode (Example: 8-Bit Data with Parity and One Stop Bit) Receiving Serial Data (Asynchronous Mode): Figures 15.7 and 15.8 show a sample flowchart for receiving serial data. The procedure is as follows (the steps correspond to the numbers in the flowchart). 1. SCI initialization: Set the RxD pin using the PFC. 2. Receive error handling and break detection: If a receive error occurs, read the ORER, PER, and FER bits of SSR to identify the error. After executing the necessary error handling, clear ORER, PER, and FER all to 0. Receiving cannot resume if ORER, PER or FER remain set to 1. When a framing error occurs, the RxD pin can be read to detect the break state. 3. SCI status check and receive-data read: Read the serial status register (SSR), check that RDRF is set to 1, then read receive data from the receive data register (RDR) and clear RDRF to 0. The RXI interrupt can also be used to determine if the RDRF bit has changed from 0 to 1. 4. Continue receiving serial data: Read RDR and the RDRF bit and clear RDRF to 0 before the stop bit of the current frame is received. If the DMAC is started by a receive-data-full interrupt (RXI) to read RDR, the RDRF bit is cleared automatically so this step is unnecessary. Rev.2.0, 07/03, page 490 of 960 Initialization 1 Start of reception Read ORER, PER, and FER bits in SSR PER, FER, ORER = 1? No Read RDRF bit in SSR Yes 2 Error handling 3 No RDRF = 1? Yes Read receive data in RDR and clear RDRF bit in SSR to 0 4 No All data received? Yes Clear RE bit in SCR to 0 End of reception Figure 15.7 Sample Flowchart for Receiving Serial Data (1) Rev.2.0, 07/03, page 491 of 960 Error handling No ORER = 1? Yes Overrun error handling No FER = 1? Yes Break? No Framing error handling Clear RE bit in SCR to 0 Yes No PER = 1? Yes Parity error handling Clear ORER, PER, and FER to 0 in SSR End Figure 15.8 Sample Flowchart for Receiving Serial Data (2) Rev.2.0, 07/03, page 492 of 960 In receiving, the SCI operates as follows: 1. The SCI monitors the communication line. When it detects a start bit (0), the SCI synchronizes internally and starts receiving. 2. Receive data is shifted into RSR in order from the LSB to the MSB. 3. The parity bit and stop bit are received. After receiving these bits, the SCI makes the following checks: a. Parity check. The number of 1s in the receive data must match the even or odd parity setting of the O/E bit in SMR. b. Stop bit check. The stop bit value must be 1. If there are two stop bits, only the first stop bit is checked. c. Status check. RDRF must be 0 so that receive data can be loaded from RSR into RDR. If the data passes these checks, the SCI sets RDRF to 1 and stores the receive data in RDR. If one of the checks fails (receive error), the SCI operates as indicated in table 15.11. Note: When a receive error occurs, further receiving is disabled. While receiving, the RDRF bit is not set to 1, so be sure to clear the error flags. 4. After setting RDRF to 1, if the receive-data-full interrupt enable bit (RIE) is set to 1 in SCR, the SCI requests a receive-data-full interrupt (RXI). If one of the error flags (ORER, PER, or FER) is set to 1 and the receive-data-full interrupt enable bit (RIE) in SCR is also set to 1, the SCI requests a receive-error interrupt (ERI). Table 15.11 Receive Error Conditions and SCI Operation Receive Error Overrun error Framing error Parity error Abbreviation ORER FER PER Condition Receiving of next data ends while RDRF is still set to 1 in SSR Stop bit is 0 Parity of receive data differs from even/odd parity setting in SMR Data Transfer Receive data not loaded from RSR into RDR Receive data loaded from RSR into RDR Receive data loaded from RSR into RDR Figure 15.9 shows an example of SCI receive operation in asynchronous mode. Rev.2.0, 07/03, page 493 of 960 1 Serial data Start bit 0 D0 D1 Data D7 Parity Stop Start bit bit bit 0/1 1 0 D0 Data D1 Parity Stop bit bit D7 0/1 1 1 Idling (marking) TDRF RXI interrupt request FER 1 frame RXI interrupt handler reads data in RDR and clears RDRF to 0. Framing error generates ERI interrupt request. Figure 15.9 SCI Receive Operation (Example: 8-Bit Data with Parity and One Stop Bit) 15.3.3 Multiprocessor Communication The multiprocessor communication function enables several processors to share a single serial communication line for sending and receiving data. The processors communicate in the asynchronous mode using a format with an additional multiprocessor bit (multiprocessor format). In multiprocessor communication, each receiving processor is addressed by a unique ID. A serial communication cycle consists of an ID-sending cycle that identifies the receiving processor, and a data-sending cycle. The multiprocessor bit distinguishes ID-sending cycles from data-sending cycles. The transmitting processor starts by sending the ID of the receiving processor with which it wants to communicate as data with the multiprocessor bit set to 1. Next the transmitting processor sends transmit data with the multiprocessor bit cleared to 0. Receiving processors skip incoming data until they receive data with the multiprocessor bit set to 1. When they receive data with the multiprocessor bit set to 1, receiving processors compare the data with their IDs. The receiving processor with a matching ID continues to receive further incoming data. Processors with IDs not matching the received data skip further incoming data until they again receive data with the multiprocessor bit set to 1. Multiple processors can send and receive data in this way. Figure 15.10 shows an example of communication among processors using the multiprocessor format. Rev.2.0, 07/03, page 494 of 960 Communication Formats: Four formats are available. Parity-bit settings are ignored when the multiprocessor format is selected. For details see table 15.8. Clock: See the description in the asynchronous mode section. Transmitting processor Serial communication line Receiving processor A (ID = 01) Receiving processor B (ID = 02) Receiving processor C (ID = 03) Receiving processor D (ID = 04) Serial data H'01 (MPB = 1) ID-transmit cycle: receiving processor address H'AA (MPB = 0) Data-transmit cycle: data sent to receiving processor specified by ID MPB: Multiprocessor bit Figure 15.10 Communication among Processors Using Multiprocessor Format (Example: Sending Data H'AA to Receiving Processor A) Data Transmit/Receive Operation Transmitting Multiprocessor Serial Data: Figure 15.11 shows a sample flowchart for transmitting multiprocessor serial data. The procedure is as follows (the steps correspond to the numbers in the flowchart): 1. SCI initialization: Set the TxD pin using the PFC. 2. SCI status check and transmit data write: Read the serial status register (SSR), check that the TDRE bit is 1, then write transmit data in the transmit data register (TDR). Also set MPBT (multiprocessor bit transfer) to 0 or 1 in SSR. Finally, clear TDRE to 0. 3. Continue transmitting serial data: Read the TDRE bit to check whether it is safe to write (if it reads 1); if so, write data in TDR, then clear TDRE to 0. When the DMAC is started by a transmit-data-empty interrupt request (TXI) to write data in TDR, the TDRE bit is checked and cleared automatically. 4. Output a break at the end of serial transmission: Set the data register (DR) of the port to 0, then clear TE to 0 in SCR and set the TxD pin function as output port with the PFC. Rev.2.0, 07/03, page 495 of 960 Initialization Start of transmission Read TDRE bit in SSR 1 2 No TDRE = 1? Yes Write transmit data in TDR and set MPBT in SSR Clear TDRE bit to 0 All data transmitted? Yes Read TEND bit in SSR No 3 TEND = 1? Yes Output break signal? Yes Clear port DR to 0 Clear TE bit in SCR to 0; select theTxD pin function as an output port with the PFC No No 4 End of transmission Figure 15.11 Sample Flowchart for Transmitting Multiprocessor Serial Data Rev.2.0, 07/03, page 496 of 960 In transmitting serial data, the SCI operates as follows: 1. The SCI monitors the TDRE bit in SSR. When TDRE is cleared to 0 the SCI recognizes that the transmit data register (TDR) contains new data, and loads this data from TDR into the transmit shift register (TSR). 2. After loading the data from TDR into TSR, the SCI sets the TDRE bit to 1 and starts transmitting. If the transmit-data-empty interrupt enable bit (TIE) in SCR is set to 1, the SCI requests a transmit-data-empty interrupt (TXI) at this time. Serial transmit data is transmitted in the following order from the TxD pin: a. Start bit: one 0-bit is output. b. Transmit data: seven or eight bits are output, LSB first. c. Multiprocessor bit: one multiprocessor bit (MPBT value) is output. d. Stop bit: one or two 1-bits (stop bits) are output. e. Marking: output of 1-bits continues until the start bit of the next transmit data. 3. The SCI checks the TDRE bit when it outputs the stop bit. If TDRE is 0, the SCI loads data from TDR into TSR, outputs the stop bit, then begins serial transmission of the next frame. If TDRE is 1, the SCI sets the TEND bit in SSR to 1, outputs the stop bit, then continues output of 1-bits in the marking state. If the transmit-end interrupt enable bit (TEIE) in SCR is set to 1, a transmit-end interrupt (TEI) is requested at this time. Figure 15.12 shows an example of SCI receive operation in the multiprocessor format. Multiprocessor bit Stop Start Data bit bit D0 D1 D7 0/1 1 0 D0 Multiprocessor bit Stop Data bit D1 D7 0/1 1 1 Serial data Start bit 0 1 Idling (marking) TDRE TEND TXI interrupt request TXI interrupt handler writes data in TDR and clears TDRE to 0 1 frame TXI interrupt request TEI interrupt request Figure 15.12 SCI Multiprocessor Transmit Operation (Example: 8-Bit Data with Multiprocessor Bit and One Stop Bit) Rev.2.0, 07/03, page 497 of 960 Receiving Multiprocessor Serial Data: Figure 15.13 shows a sample flowchart for receiving multiprocessor serial data. The procedure for receiving multiprocessor serial data is as follows (the steps correspond to the numbers in the flowchart): 1. SCI initialization: Set the RxD pin using the PFC. 2. ID receive cycle: Set the MPIE bit in the serial control register (SCR) to 1. 3. SCI status check and compare to ID reception: Read the serial status register (SSR), check that RDRF is set to 1, then read data from the receive data register (RDR) and compare with the processor's own ID. If the ID does not match the receive data, set MPIE to 1 again and clear RDRF to 0. If the ID matches the receive data, clear RDRF to 0. 4. Receive error handling and break detection: If a receive error occurs, read the ORER and FER bits in SSR to identify the error. After executing the necessary error handling, clear both ORER and FER to 0. Receiving cannot resume if ORER or FER remain set to 1. When a framing error occurs, the RxD pin can be read to detect the break state. 5. SCI status check and data receiving: Read SSR, check that RDRF is set to 1, then read data from the receive data register (RDR). Rev.2.0, 07/03, page 498 of 960 Initialization Start of reception Set MPIE bit in SCR to 1 Read ORER and FER bits in SSR FER = 1? or ORER =1? No Read RDRF bit in SSR No 1 2 Yes 3 RDRF = 1? Yes Read receive data from RDR No Is ID the station's ID? Yes Read ORER and FER bits in SSR FER = 1? or ORER =1? No Read RDRF bit in SSR RDRF = 1? Yes Read receive data from RDR 4 5 No Yes No All data received? Yes Clear RE bit in SCR to 0 End of reception Error handling Figure 15.13 Sample Flowchart for Receiving Multiprocessor Serial Data (1) Rev.2.0, 07/03, page 499 of 960 Error handling No ORER = 1? Yes Overrun error handling No FER = 1? Yes Break? No Framing error handling Clear RE bit in SCR to 0 Yes Clear ORER and FER bits in SSR to 0 End Figure 15.14 Sample Flowchart for Receiving Multiprocessor Serial Data (2) Rev.2.0, 07/03, page 500 of 960 Figures 15.15 and 15.16 show examples of SCI receive operation using a multiprocessor format. Start bit 0 Data (ID1) D0 D1 D7 Stop Start Data bit (data 1) MPB bit 1 1 0 D0 D1 D7 Stop MPB bit 0 1 1 Serial data 1 Idling (marking) MPB MPIE RDRF RDR value RXI interrupt request (multiprocessor interrupt), MPIE = 0 RXI interrupt handler reads data in RDR and clears RDRF to 0 ID1 Not station's ID, so MPIE is set to 1 again No RXI interrupt, RDR maintains state Figure 15.15 SCI Receive Operation (ID Does Not Match) (Example: 8-Bit Data with Multiprocessor Bit and One Stop Bit) Rev.2.0, 07/03, page 501 of 960 1 Serial data Start bit 0 Data (ID2) D0 D1 D7 Stop Start Data MPB bit bit (data 2) 1 1 0 D0 D1 D7 Stop MPB bit 0 1 1 Idling (marking) MPB MPIE RDRF RDR value ID1 ID2 Data 2 RXI interrupt request (multiprocessor interrupt), MPIE = 0 RXI interrupt handler reads data in RDR and clears RDRF to 0 Station's ID, so receiving MPIE continues, with data bit is again received by the RXI set to 1 interrupt processing routine Figure 15.16 Example of SCI Receive Operation (ID Matches) (Example: 8-Bit Data with Multiprocessor Bit and One Stop Bit) 15.3.4 Synchronous Operation In synchronous mode, the SCI transmits and receives data in synchronization with clock pulses. This mode is suitable for high-speed serial communication. The SCI transmitter and receiver are independent, so full duplex communication is possible while sharing the same clock. The transmitter and receiver are also double buffered, so continuous transmitting or receiving is possible by reading or writing data while transmitting or receiving is in progress. Figure 15.17 shows the general format in synchronous serial communication. Rev.2.0, 07/03, page 502 of 960 Transfer direction One unit (character or frame) of communication data * Serial clock LSB Serial data Bit 0 Bit 1 Bit 2 Bit 3 Bit 4 Bit 5 Bit 6 MSB Bit 7 * Note: * High except in continuous transmitting or receiving. Figure 15.17 Data Format in Synchronous Communication In synchronous serial communication, each data bit is output on the communication line from one falling edge of the serial clock to the next. Data is guaranteed valid at the rising edge of the serial clock. In each character, the serial data bits are transmitted in order from the LSB (first) to the MSB (last). After output of the MSB, the communication line remains in the state of the MSB. In synchronous mode, the SCI transmits or receives data by synchronizing with the rise of the serial clock. Communication Format: The data length is fixed at eight bits. No parity bit or multiprocessor bit can be added. Clock: An internal clock generated by the on-chip baud rate generator or an external clock input from the SCK pin can be selected as the SCI transmit/receive clock. The clock source is selected by the C/A bit in the serial mode register (SMR) and bits CKE1 and CKE0 in the serial control register (SCR). See table 15.9. When the SCI operates on an internal clock, it outputs the clock signal at the SCK pin. Eight clock pulses are output per transmitted or received character. When the SCI is not transmitting or receiving, the clock signal remains in the high state. An overrun error occurs only during the receive operation, and the serial clock is output until the RE bit is cleared to 0. To perform a receive operation in one-character units, select an external clock for the clock source. Rev.2.0, 07/03, page 503 of 960 Transmitting and Receiving Data SCI Initialization (Synchronous Mode): Before transmitting or receiving, software must clear the TE and RE bits to 0 in the serial control register (SCR), then initialize the SCI as follows. When changing the mode or communication format, always clear the TE and RE bits to 0 before following the procedure given below. Clearing TE to 0 sets TDRE to 1 and initializes the transmit shift register (TSR). Clearing RE to 0, however, does not initialize the RDRF, PER, FER, and ORER flags and receive data register (RDR), which retain their previous contents. Figure 15.18 is a sample flowchart for initializing the SCI. 1. Select the clock source in the serial control register (SCR). Leave RIE, TIE, TEIE, MPIE, TE, and RE cleared to 0. 2. Select the communication format in the serial mode register (SMR) and serial direction control register (SDCR). 3. Write the value corresponding to the bit rate in the bit rate register (BRR) (unless an external clock is used). 4. Wait for at least the interval required to transmit or receive one bit, then set TE or RE in the serial control register (SCR) to 1.* Also set RIE, TIE, TEIE, and MPIE. The TxD, RxD pins becomes usable in response to the PFC corresponding bits and the TE, RE bit settings. Note: * In simultaneous transmit/receive operation, the TE bit and RE bit must be cleared to 0 or set to 1 simultaneously. Rev.2.0, 07/03, page 504 of 960 Start of initialization Clear TE and RE bits to 0 in SCR Set CKE1 and CKE0 bits in SCR (RIE, TIE, TEIE, MPIE,TE, and RE are 0) 1 Select transmit/receive format in SMR and SDCR 2 Set value in BRR Wait 1-bit interval elapsed? Yes Set TE and RE to 1 in SCR; Set RIE, TIE, TEIE, and MPIE bits No 3 4 End of initialization Figure 15.18 Sample Flowchart for SCI Initialization Transmitting Serial Data (Synchronous Mode): Figure 15.19 shows a sample flowchart for transmitting serial data. The procedure is as follows (the steps correspond to the numbers in the flowchart): 1. SCI initialization: Set the TxD pin function with the PFC. 2. SCI status check and transmit data write: Read SSR, check that the TDRE flag is 1, then write transmit data in TDR and clear the TDRE flag to 0. 3. To continue transmitting serial data: After checking that the TDRE flag is 1, indicating that data can be written, write data in TDR, then clear the TDRE flag to 0. When the DMAC is activated by a transmit-data-empty interrupt request (TXI) to write data in TDR, the TDRE flag is checked and cleared automatically. Rev.2.0, 07/03, page 505 of 960 Initialization 1 Start of transmission Read TDRE flag in SSR 2 No TDRE = 1? Yes Write transmit data in TDR and clear TDRE flag to 0 in SSR No All data transmitted? 3 Yes Read TEND flag in SSR TEND = 1? Yes Clear TE bit to 0 in SCR No End Figure 15.19 Sample Flowchart for Serial Transmitting Rev.2.0, 07/03, page 506 of 960 Figure 15.20 shows an example of SCI transmit operation. Transfer direction Serial clock LSB Serial data Bit 0 Bit 1 MSB Bit 7 Bit 0 Bit 1 Bit 6 Bit 7 TDRE TEND TXI interrupt request TXI interrupt TXI interrupt handler writes request data in TDR and clears TDRE to 0 1 frame TEI interrupt request Figure 15.20 Example of SCI Transmit Operation SCI serial transmission operates as follows. 1. The SCI monitors the TDRE bit in SSR. When TDRE is cleared to 0 the SCI recognizes that the transmit data register (TDR) contains new data and loads this data from TDR into the transmit shift register (TSR). 2. After loading the data from TDR into TSR, the SCI sets the TDRE bit to 1 and starts transmitting. If the transmit-data-empty interrupt enable bit (TIE) in SCR is set to 1, the SCI requests a transmit-data-empty interrupt (TXI) at this time. If clock output mode is selected, the SCI outputs eight serial clock pulses. If an external clock source is selected, the SCI outputs data in synchronization with the input clock. Data is output from the TxD pin in order from the LSB (bit 0) to the MSB (bit 7). 3. The SCI checks the TDRE bit when it outputs the MSB (bit 7). If TDRE is 0, the SCI loads data from TDR into TSR, then begins serial transmission of the next frame. If TDRE is 1, the SCI sets the TEND bit in SSR to 1, transmits the MSB, then holds the transmit data pin (TxD) in the MSB state. If the transmit-end interrupt enable bit (TEIE) in SCR is set to 1, a transmitend interrupt (TEI) is requested at this time. 4. After the end of serial transmission, the SCK pin is held in the high state. Rev.2.0, 07/03, page 507 of 960 Receiving Serial Data (Synchronous Mode): Figures 15.21 and 15.22 show a sample flowchart for receiving serial data. When switching from asynchronous mode to synchronous mode, make sure that ORER, PER, and FER are cleared to 0. If PER or FER is set to 1, the RDRF bit will not be set and both transmitting and receiving will be disabled. The procedure for receiving serial data is as follows (the steps correspond to the numbers in the flowchart): 1. SCI initialization: Set the RxD pin using the PFC. 2. Receive error handling: If a receive error occurs, read the ORER bit in SSR to identify the error. After executing the necessary error handling, clear ORER to 0. Transmitting/receiving cannot resume if ORER remains set to 1. 3. SCI status check and receive data read: Read the serial status register (SSR), check that RDRF is set to 1, then read receive data from the receive data register (RDR) and clear RDRF to 0. The RXI interrupt can also be used to determine if the RDRF bit has changed from 0 to 1. 4. Continue receiving serial data: Read RDR, and clear RDRF to 0 before the MSB (bit 7) of the current frame is received. If the DMAC is started by a receive-data-full interrupt (RXI) to read RDR, the RDRF bit is cleared automatically so this step is unnecessary. Rev.2.0, 07/03, page 508 of 960 Initialization 1 Start of reception Read ORER bit in SSR Yes ORER = 1? No Read RDRF bit in SSR No 3 2 Error handling RDRF = 1? Yes Read receive data from RDR and clear RDRF bit in SSR to 0 4 No All data received? Yes Clear RE bit in SCR to 0 End of reception Figure 15.21 Sample Flowchart for Serial Receiving (1) Rev.2.0, 07/03, page 509 of 960 Error handling Overrun error handling Clear ORER bit in SSR to 0 End Figure 15.22 Sample Flowchart for Serial Receiving (2) Figure 15.23 shows an example of the SCI receive operation. Transfer direction Serial clock Serial data Bit 7 Bit 0 Bit 7 Bit 0 Bit 1 Bit 6 Bit 7 RDRF ORER RXI interrupt request Read data with RXI interrupt processing routine and clear RDRF bit to 0 1 frame RXI interrupt request ERI interrupt request generated by overrun error Figure 15.23 Example of SCI Receive Operation In receiving, the SCI operates as follows: 1. The SCI synchronizes with serial clock input or output and initializes internally. 2. Receive data is shifted into RSR in order from the LSB to the MSB. After receiving the data, the SCI checks that RDRF is 0 so that receive data can be loaded from RSR into RDR. If this check passes, the SCI sets RDRF to 1 and stores the receive data in RDR. If the check does not pass (receive error), the SCI operates as indicated in table 15.11 and no further transmission or Rev.2.0, 07/03, page 510 of 960 reception is possible. If the error flag is set to 1, the RDRF bit is not set to 1 during reception, even if the RDRF bit is 0 cleared. When restarting reception, be sure to clear the error flag. 3. After setting RDRF to 1, if the receive-data-full interrupt enable bit (RIE) is set to 1 in SCR, the SCI requests a receive-data-full interrupt (RXI). If the ORER bit is set to 1 and the receivedata-full interrupt enable bit (RIE) in SCR is also set to 1, the SCI requests a receive-error interrupt (ERI). Transmitting and Receiving Serial Data Simultaneously (Synchronous Mode): Figure 15.24 shows a sample flowchart for transmitting and receiving serial data simultaneously. The procedure is as follows (the steps correspond to the numbers in the flowchart): 1. SCI initialization: Set the TxD and RxD pins using the PFC. 2. SCI status check and transmit data write: Read the serial status register (SSR), check that the TDRE bit is 1, then write transmit data in the transmit data register (TDR) and clear TDRE to 0. The TXI interrupt can also be used to determine if the TDRE bit has changed from 0 to 1. 3. Receive error handling: If a receive error occurs, read the ORER bit in SSR to identify the error. After executing the necessary error handling, clear ORER to 0. Transmitting/receiving cannot resume if ORER remains set to 1. 4. SCI status check and receive data read: Read the serial status register (SSR), check that RDRF is set to 1, then read receive data from the receive data register (RDR) and clear RDRF to 0. The RXI interrupt can also be used to determine if the RDRF bit has changed from 0 to 1. 5. Continue transmitting and receiving serial data: Read the RDRF bit and RDR, and clear RDRF to 0 before the MSB (bit 7) of the current frame is received. Also read the TDRE bit to check whether it is safe to write (if it reads 1); if so, write data in TDR, then clear TDRE to 0 before the MSB (bit 7) of the current frame is transmitted. When the DMAC is started by a transmitdata-empty interrupt request (TXI) to write data in TDR, the TDRE bit is checked and cleared automatically. When the DMAC is started by a receive-data-full interrupt (RXI) to read RDR, the RDRF bit is cleared automatically. Note: In switching from transmitting or receiving to simultaneous transmitting and receiving, clear both TE and RE to 0, then set both TE and RE to 1 simultaneously. Rev.2.0, 07/03, page 511 of 960 Initialization Start of transmission/reception 1 Read TDRE bit in SSR No 2 TDRE = 1? Yes Write transmit data in TDR and clear TDRE bit in SSR to 0 Read ORER bit in SSR Yes 3 Error handling 4 ORER = 1? No Read RDRF bit in SSR No RDRF = 1? Yes Read receive data in RDR, and clear RDRF bit in SSR to 0 All data transmitted/ received? Yes Clear TE and RE bits in SCR to 0 End of transmission/reception 5 No Figure 15.24 Sample Flowchart for Serial Transmission and Reception Rev.2.0, 07/03, page 512 of 960 15.4 SCI Interrupt Sources and the DMAC The SCI has four interrupt sources: transmit-end (TEI), receive-error (ERI), receive-data-full (RXI), and transmit-data-empty (TXI). Table 15.12 lists the interrupt sources and indicates their priority. These interrupts can be enabled and disabled by the TIE, RIE, and TEIE bits in the serial control register (SCR). Each interrupt request is sent separately to the interrupt controller. TXI is requested when the TDRE bit in SSR is set to 1. TXI can start the direct memory access controller (DMAC) to transfer data. TDRE is automatically cleared to 0 when the DMAC writes data in the transmit data register (TDR). RXI is requested when the RDRF bit in SSR is set to 1. RXI can start the DMAC to transfer data. RDRF is automatically cleared to 0 when the DMAC reads the receive data register (RDR). ERI is requested when the ORER, PER, or FER bit in SSR is set to 1. ERI cannot start the DMAC. TEI is requested when the TEND bit in SSR is set to 1. TEI cannot start the DMAC. Where the TXI interrupt indicates that transmit data writing is enabled, the TEI interrupt indicates that the transmit operation is complete. Table 15.12 SCI Interrupt Sources Interrupt Source ERI RXI TXI TEI Description Receive error (ORER, PER, or FER) Receive data full (RDRF) Transmit data empty (TDRE) Transmit end (TEND) DMAC Activation No Yes Yes No Low Priority High Rev.2.0, 07/03, page 513 of 960 15.5 Usage Notes Sections 15.5.1 through 15.5.9 provide information concerning use of the SCI. 15.5.1 TDR Write and TDRE Flag The TDRE bit in the serial status register (SSR) is a status flag indicating loading of transmit data from TDR into TSR. The SCI sets TDRE to 1 when it transfers data from TDR to TSR. Data can be written to TDR regardless of the TDRE bit status. If new data is written in TDR when TDRE is 0, however, the old data stored in TDR will be lost because the data has not yet been transferred to TSR. Before writing transmit data to TDR, be sure to check that TDRE is set to 1. 15.5.2 Simultaneous Multiple Receive Errors Table 15.13 indicates the state of the SSR status flags when multiple receive errors occur simultaneously. When an overrun error occurs, the RSR contents cannot be transferred to RDR, so receive data is lost. Table 15.13 SSR Status Flags and Transfer of Receive Data SSR Status Flags Receive Error Status Overrun error Framing error Parity error Overrun error + framing error Overrun error + parity error Framing error + parity error Overrun error + framing error + parity error RDRF 1 0 0 1 1 0 1 ORER 1 0 0 1 1 0 1 FER 0 1 0 1 0 1 1 PER 0 0 1 0 1 1 1 Receive Data Transfer RSR RDR X O O X X O X Notes: O: Receive data is transferred from RSR to RDR. X: Receive data is not transferred from RSR to RDR. Rev.2.0, 07/03, page 514 of 960 15.5.3 Break Detection and Processing Break signals can be detected by reading the RxD pin directly when a framing error (FER) is detected. In the break state, the input from the RxD pin consists of all 0s, so FER is set and the parity error flag (PER) may also be set. In the break state, the SCI receiver continues to operate, so if the FER bit is cleared to 0, it will be set to 1 again. 15.5.4 Sending a Break Signal The TxD pin becomes a general I/O pin with the I/O direction and level determined by the I/O port data register (DR) and pin function controller (PFC) control register (CR). These conditions allow break signals to be sent. The DR value is substituted for the marking status until the PFC is set. Consequently, the output port is set to initially output a 1. To send a break in serial transmission, first clear the DR to 0, then establish the TxD pin as an output port using the PFC. When TE is cleared to 0, the transmission section is initialized regardless of the present transmission status. 15.5.5 Receive Error Flags and Transmitter Operation (Synchronous Mode Only) When a receive error flag (ORER, PER, or FER) is set to 1, the SCI will not start transmitting even if TDRE is set to 1. Be sure to clear the receive error flags to 0 before starting to transmit. Note that clearing RE to 0 does not clear the receive error flags. 15.5.6 Receive Data Sampling Timing and Receive Margin in Asynchronous Mode In asynchronous mode, the SCI operates on a base clock with a frequency of 16 times the transfer rate. In receiving, the SCI synchronizes internally with the falling edge of the start bit, which it samples on the base clock. Receive data is latched on the rising edge of the eighth base clock pulse (figure 15.25). Rev.2.0, 07/03, page 515 of 960 16 clocks 8 clocks 0 Base clock -7.5 clocks Receive data (RxD) Synchronization sampling timing Data sampling timing Start bit +7.5 clocks D0 D1 78 15 0 78 15 0 5 Figure 15.25 Receive Data Sampling Timing in Asynchronous Mode The receive margin in asynchronous mode can therefore be expressed as: M = 0.5 - 1 D - 0.5 (1 + F) x 100% - (L - 0.5) F - 2N N M : Receive margin (%) N : Ratio of clock frequency to bit rate (N = 16) D : Clock duty cycle (D = 0-1.0) L : Frame length (L = 9-12) F : Absolute deviation of clock frequency From the equation above, if F = 0 and D = 0.5 the receive margin is 46.875%: D = 0.5, F = 0 M = (0.5 - 1/(2 x 16)) x 100% = 46.875% This is a theoretical value. A reasonable margin to allow in system designs is 20-30%. 15.5.7 Constraints on DMAC Use * When using an external clock source for the serial clock, update TDR with the DMAC, and then after the elapse of five peripheral clocks (P) or more, input a transmit clock. If a transmit clock is input in the first four P clocks after TDR is written, an error may occur (figure 15.26). * Before reading the receive data register (RDR) with the DMAC, select the receive-data-full (RXI) interrupt of the SCI as a start-up source. Rev.2.0, 07/03, page 516 of 960 SCK t TDRE D0 D1 D2 D3 D4 D5 D6 D7 Note: During external clock operation, an error may occur if t is 4 P clocks or less. Figure 15.26 Example of Synchronous Transmission with DMAC 15.5.8 Cautions on Synchronous External Clock Mode * Set TE = RE = 1 only when external clock SCK is 1. * Do not set TE = RE = 1 until at least four P clocks after external clock SCK has changed from 0 to 1. * When receiving, RDRF is 1 when RE is cleared to zero 2.5-3.5 P clocks after the rising edge of the RxD D7 bit SCK input, but copying to RDR is not possible. 15.5.9 Caution on Synchronous Internal Clock Mode When receiving, RDRF is 1 when RE is cleared to zero 1.5 P clocks after the rising edge of the RxD D7 bit SCK output, but copying to RDR is not possible. Rev.2.0, 07/03, page 517 of 960 Rev.2.0, 07/03, page 518 of 960 Section 16 Controller Area Network (HCAN) 16.1 Overview The HCAN is a module for controlling a controller area network (CAN) for realtime communication in vehicular and industrial equipment systems, etc. The SH7055SF has a 2channel on-chip HCAN module. Reference: Bosch CAN Specification Version 2.0 1991, Robert Bosch GmbH 16.1.1 Features The HCAN has the following features: * CAN version: Bosch 2.0B active compatible Communication systems: NRZ (Non-Return to Zero) system (with bit-stuffing function) Broadcast communication system Transmission path: Bidirectional 2-wire serial communication Communication speed: Max. 1 Mbps (at 40 MHz operation) Data length: 0 to 8 bytes * Number of channels: 2 (HCAN0, HCAN1) * Data buffers: 16 per channel (one receive-only buffer and 15 buffers settable for transmission/reception) * Data transmission: Choice of two methods: Mailbox (buffer) number order (low-to-high) Message priority (identifier) high-to-low order * Data reception: Two methods: Message identifier match (transmit/receive-setting buffers) Reception with message identifier masked (receive-only) * CPU interrupts: Four independent interrupt vectors per channel: Error interrupt Reset processing interrupt Message reception interrupt Message transmission interrupt * HCAN operating modes: Support for various modes: Hardware reset Software reset Normal status (error-active, error-passive) Rev.2.0, 07/03, page 519 of 960 Bus off status HCAN configuration mode HCAN sleep mode HCAN halt mode * HCAN connection methods: Choice of two methods of use: Two-channel 16-buffer HCANs (two transmit pins, two receive pins) One-channel 32-buffer HCAN (wired-AND) (one transmit pin, one receive pin) * Other features: DMAC can be activated by message reception mailbox (HCAN0 mailbox 0 only) Rev.2.0, 07/03, page 520 of 960 16.1.2 Block Diagram Figure 16.1 shows a block diagram of the HCAN. HCAN0 MBI Message buffer interface Mailboxes Message control Message data MC0-MC15, MD0-MD15 LAFM (CDLC) CAN Data Link Controller Bosch CAN 2.0B active HTxD0 Tx buffer MPI Microprocessor interface Rx buffer HRxD0 Peripheral address bus Peripheral data bus CPU interface Control register Status register HCAN1 MBI Message buffer interface Mailboxes Message control Message data MC0-MC15, MD0-MD15 (CDLC) CAN Data Link Controller Bosch CAN 2.0B active HTxD1 LAFM Tx buffer MPI Microprocessor interface CPU interface Control register Status register Rx buffer HRxD1 Figure 16.1 HCAN Block Diagram Message Buffer Interface (MBI): The MBI, consisting of mailboxes and a local acceptance filter mask (LAFM), stores CAN transmit/receive messages (identifiers, data, etc.). Transmit messages are written by the CPU. For receive messages, the data received by the CDLC is stored automatically. Microprocessor Interface (MPI): The MPI, consisting of a bus interface, control register, status register, etc., controls HCAN internal data, statuses, and so forth. CAN Data Link Controller (CDLC): The CDLC performs transmission and reception of messages conforming to the Bosch CAN Ver. 2.0B active standard (data frames, remote frames, Rev.2.0, 07/03, page 521 of 960 error frames, overload frames, inter-frame spacing), as well as CRC checking, bus arbitration, and other functions. 16.1.3 Pin Configuration Table 16.1 shows the HCAN's pins. When using the functions of these external pins, the pin function controller (PFC) must also be set in line with the HCAN settings. When using HCAN pins, settings must be made in the HCAN configuration mode (during initialization: MCR0 = 1 and GSR3 = 1). Table 16.1 HCAN Pins Channel 0 Name HCAN transmit data pin 0 HCAN receive data pin 0 1 HCAN transmit data pin 1 HCAN receive data pin 1 Abbreviation HTxD0 HRxD0 HTxD1 HRxD1 Input/Output Output Input Output Input Function Channel 0 CAN bus transmission pin Channel 0 CAN bus reception pin Channel 1 CAN bus transmission pin Channel 1 CAN bus reception pin A bus transceiver IC is necessary between the pins and the CAN bus. A Philips PCA82C250 compatible model is recommended. These pins are multiplexed, and can be set in either of the following ways. * Setting each channel as an independent 16-message-buffer HCAN (two HCAN channels: two transmit pins and two receive pins) * Setting one HCAN channel, using wired-AND connection of the pins for the two channels (one 32-message-buffer HCAN channel: one transmit pin and one receive pin) See section 16.3, Operation, for details. The pin numbers of the pins that can be set for each channel are shown in table 16.2. Table 16.2 Pin Numbers of Pins Settable as HCAN Pins HCAN0 16 Message Buffers HTxD HRxD 6,157,228 158,170,229 HCAN1 16 Message Buffers 6,228 170,229 HCAN0,1 (Wired AND) 32 Message Buffers 228 229 Rev.2.0, 07/03, page 522 of 960 16.1.4 Register Configuration Table 16.3 lists the HCAN's registers. Table 16.3 HCAN Registers Channel Name 0 Master control register General status register Bit configuration register Mailbox configuration register Transmit wait register Transmit wait cancel register Transmit acknowledge register Abort acknowledge register Receive complete register Remote request register Interrupt register Mailbox interrupt mask register Interrupt mask register Receive error counter Transmit error counter Unread message status register Local acceptance filter mask L Local acceptance filter mask H Abbreviation MCR GSR BCR MBCR TXPR TXCR TXACK ABACK RXPR RFPR IRR MBIMR IMR REC TEC UMSR LAFML LAFMH R/W R/W R R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R R R/W R/W R/W Initial Value H'01 H'0C H'0000 H'0100 H'0000 H'0000 H'0000 H'0000 H'0000 H'0000 H'0100 H'FFFF H'FEFF H'00 H'00 H'0000 H'0000 H'0000 Address Access Size H'FFFF E400 8 bits 16 bits H'FFFF E401 8 bits H'FFFF E402 8/16 bits H'FFFF E404 8/16 bits H'FFFF E406 8/16 bits H'FFFF E408 8/16 bits H'FFFF E40A 8/16 bits H'FFFF E40C 8/16 bits H'FFFF E40E 8/16 bits H'FFFF E410 8/16 bits H'FFFF E412 8/16 bits H'FFFF E414 8/16 bits H'FFFF E416 8/16 bits H'FFFF E418 8 bits 16 bits H'FFFF E419 8 bits H'FFFF E41A 8/16 bits H'FFFF E41C 8/16 bits H'FFFF E41E 8/16 bits Rev.2.0, 07/03, page 523 of 960 Table 16.3 HCAN Registers (cont) Channel Name 0 Message control 0 [1:8] Message control 1 [1:8] Message control 2 [1:8] Message control 3 [1:8] Message control 4 [1:8] Message control 5 [1:8] Message control 6 [1:8] Message control 7 [1:8] Message control 8 [1:8] Message control 9 [1:8] Message control 10 [1:8] Message control 11 [1:8] Message control 12 [1:8] Message control 13 [1:8] Message control 14 [1:8] Message control 15 [1:8] Message data 0 [1:8] Message data 1 [1:8] Message data 2 [1:8] Message data 3 [1:8] Message data 4 [1:8] Message data 5 [1:8] Message data 6 [1:8] Message data 7 [1:8] Message data 8 [1:8] Message data 9 [1:8] Message data 10 [1:8] Message data 11 [1:8] Message data 12 [1:8] Message data 13 [1:8] Message data 14 [1:8] Message data 15 [1:8] Abbreviation MC0 [1:8] MC1 [1:8] MC2 [1:8] MC3 [1:8] MC4 [1:8] MC5 [1:8] MC6 [1:8] MC7 [1:8] MC8 [1:8] MC9 [1:8] R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Initial Value Address Access Size Undefined H'FFFF E420 8/16 bits Undefined H'FFFF E428 8/16 bits Undefined H'FFFF E430 8/16 bits Undefined H'FFFF E438 8/16 bits Undefined H'FFFF E440 8/16 bits Undefined H'FFFF E448 8/16 bits Undefined H'FFFF E450 8/16 bits Undefined H'FFFF E458 8/16 bits Undefined H'FFFF E460 8/16 bits Undefined H'FFFF E468 8/16 bits Undefined H'FFFF E470 8/16 bits Undefined H'FFFF E478 8/16 bits Undefined H'FFFF E480 8/16 bits Undefined H'FFFF E488 8/16 bits Undefined H'FFFF E490 8/16 bits Undefined H'FFFF E498 8/16 bits Undefined H'FFFF E4B0 8/16 bits Undefined H'FFFF E4B8 8/16 bits Undefined H'FFFF E4C0 8/16 bits Undefined H'FFFF E4C8 8/16 bits Undefined H'FFFF E4D0 8/16 bits Undefined H'FFFF E4D8 8/16 bits Undefined H'FFFF E4E0 8/16 bits Undefined H'FFFF E4E8 8/16 bits Undefined H'FFFF E4F0 8/16 bits Undefined H'FFFF E4F8 8/16 bits Undefined H'FFFF E500 8/16 bits Undefined H'FFFF E508 8/16 bits Undefined H'FFFF E510 8/16 bits Undefined H'FFFF E518 8/16 bits Undefined H'FFFF E520 8/16 bits Undefined H'FFFF E528 8/16 bits MC10 [1:8] R/W MC11 [1:8] R/W MC12 [1:8] R/W MC13 [1:8] R/W MC14 [1:8] R/W MC15 [1:8] R/W MD0 [1:8] MD1 [1:8] MD2 [1:8] MD3 [1:8] MD4 [1:8] MD5 [1:8] MD6 [1:8] MD7 [1:8] MD8 [1:8] MD9 [1:8] R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W MD10 [1:8] R/W MD11 [1:8] R/W MD12 [1:8] R/W MD13 [1:8] R/W MD14 [1:8] R/W MD15 [1:8] R/W Rev.2.0, 07/03, page 524 of 960 Table 16.3 HCAN Registers (cont) Channel Name 1 Master control register General status register Bit configuration register Mailbox configuration register Transmit wait register Transmit wait cancel register Transmit acknowledge register Abort acknowledge register Receive complete register Remote request register Interrupt register Mailbox interrupt mask register Interrupt mask register Receive error counter Transmit error counter Unread message status register Local acceptance filter mask L Local acceptance filter mask H Abbreviation MCR GSR BCR MBCR TXPR TXCR TXACK ABACK RXPR RFPR IRR MBIMR IMR REC TEC UMSR LAFML LAFMH R/W R/W R R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R R R/W R/W R/W Initial Value H'01 H'0C H'0000 H'0100 H'0000 H'0000 H'0000 H'0000 H'0000 H'0000 H'0100 H'FFFF H'FEFF H'00 H'00 H'0000 H'0000 H'0000 Address Access Size H'FFFF E600 8 bits 16 bits H'FFFF E601 8 bits H'FFFF E602 8/16 bits H'FFFF E604 8/16 bits H'FFFF E606 8/16 bits H'FFFF E608 8/16 bits H'FFFF E60A 8/16 bits H'FFFF E60C 8/16 bits H'FFFF E60E 8/16 bits H'FFFF E610 8/16 bits H'FFFF E612 8/16 bits H'FFFF E614 8/16 bits H'FFFF E616 8/16 bits H'FFFF E618 8 bits 16 bits H'FFFF E619 8 bits H'FFFF E61A 8/16 bits H'FFFF E61C 8/16 bits H'FFFF E61E 8/16 bits Rev.2.0, 07/03, page 525 of 960 Table 16.3 HCAN Registers (cont) Channel Name 1 Message control 0 [1:8] Message control 1 [1:8] Message control 2 [1:8] Message control 3 [1:8] Message control 4 [1:8] Message control 5 [1:8] Message control 6 [1:8] Message control 7 [1:8] Message control 8 [1:8] Message control 9 [1:8] Message control 10 [1:8] Message control 11 [1:8] Message control 12 [1:8] Message control 13 [1:8] Message control 14 [1:8] Message control 15 [1:8] Message data 0 [1:8] Message data 1 [1:8] Message data 2 [1:8] Message data 3 [1:8] Message data 4 [1:8] Message data 5 [1:8] Message data 6 [1:8] Message data 7 [1:8] Message data 8 [1:8] Message data 9 [1:8] Message data 10 [1:8] Message data 11 [1:8] Message data 12 [1:8] Message data 13 [1:8] Message data 14 [1:8] Message data 15 [1:8] Abbreviation MC0 [1:8] MC1 [1:8] MC2 [1:8] MC3 [1:8] MC4 [1:8] MC5 [1:8] MC6 [1:8] MC7 [1:8] MC8 [1:8] MC9 [1:8] R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Initial Value Address Access Size Undefined H'FFFF E620 8/16 bits Undefined H'FFFF E628 8/16 bits Undefined H'FFFF E630 8/16 bits Undefined H'FFFF E638 8/16 bits Undefined H'FFFF E640 8/16 bits Undefined H'FFFF E648 8/16 bits Undefined H'FFFF E650 8/16 bits Undefined H'FFFF E658 8/16 bits Undefined H'FFFF E660 8/16 bits Undefined H'FFFF E668 8/16 bits Undefined H'FFFF E670 8/16 bits Undefined H'FFFF E678 8/16 bits Undefined H'FFFF E680 8/16 bits Undefined H'FFFF E688 8/16 bits Undefined H'FFFF E690 8/16 bits Undefined H'FFFF E698 8/16 bits Undefined H'FFFF E6B0 8/16 bits Undefined H'FFFF E6B8 8/16 bits Undefined H'FFFF E6C0 8/16 bits Undefined H'FFFF E6C8 8/16 bits Undefined H'FFFF E6D0 8/16 bits Undefined H'FFFF E6D8 8/16 bits Undefined H'FFFF E6E0 8/16 bits Undefined H'FFFF E6E8 8/16 bits Undefined H'FFFF E6F0 8/16 bits Undefined H'FFFF E6F8 8/16 bits Undefined H'FFFF E700 8/16 bits Undefined H'FFFF E708 8/16 bits Undefined H'FFFF E710 8/16 bits Undefined H'FFFF E718 8/16 bits Undefined H'FFFF E720 8/16 bits Undefined H'FFFF E728 8/16 bits MC10 [1:8] R/W MC11 [1:8] R/W MC12 [1:8] R/W MC13 [1:8] R/W MC14 [1:8] R/W MC15 [1:8] R/W MD0 [1:8] MD1 [1:8] MD2 [1:8] MD3 [1:8] MD4 [1:8] MD5 [1:8] MD6 [1:8] MD7 [1:8] MD8 [1:8] MD9 [1:8] R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W MD10 [1:8] R/W MD11 [1:8] R/W MD12 [1:8] R/W MD13 [1:8] R/W MD14 [1:8] R/W MD15 [1:8] R/W Rev.2.0, 07/03, page 526 of 960 16.2 16.2.1 Register Descriptions Master Control Register (MCR) The master control register (MCR) is an 8-bit readable/writable register that controls the CAN interface. Bit: 7 MCR7 Initial value: R/W: 0 R/W 6 -- 0 R 5 MCR5 0 R/W 4 -- 0 R 3 -- 0 R 2 MCR2 0 R/W 1 MCR1 0 R/W 0 MCR0 1 R/W * Bit 7--HCAN Sleep Mode Release (MCR7): Enables or disables HCAN sleep mode release by bus operation. Bit 7: MCR7 0 1 Description HCAN sleep mode release by CAN bus operation disabled HCAN sleep mode release by CAN bus operation enabled (Initial value) * Bit 6--Reserved: This bit is always read as 0. The write value should always be 0. * Bit 5--HCAN Sleep Mode (MCR5): Enables or disables HCAN sleep mode transition. Bit 5: MCR5 0 1 Description HCAN sleep mode released Transition to HCAN sleep mode enabled (Initial value) * Bits 4 and 3--Reserved: These bits are always read as 0. The write value should always be 0. * Bit 2--Message Transmission Method (MCR2): Selects the transmission method for transmit messages. Bit 2: MCR2 0 1 Description Transmission order determined by message identifier priority (Initial value) Transmission order determined by mailbox (buffer) number priority (TXPR1 > TXPR15) Rev.2.0, 07/03, page 527 of 960 * Bit 1--Halt Request (MCR1): Controls halting of the HCAN module. Bit 1: MCR1 0 1 Description Normal operating mode Halt mode transition request (Initial value) * Bit 0--Reset Request (MCR0): Controls resetting of the HCAN module. Bit 0: MCR0 0 Description Normal operating mode (MCR0 = 0 and GSR3 = 0) [Setting condition] When 0 is written after an HCAN reset 1 Reset mode transition request (Initial value) In order for GSR3 to change from 1 to 0 after 0 is written to MCR0, time is required before the HCAN is internally reset. There is consequently a delay before GSR3 is cleared to 0 after MCR0 is cleared to 0. 16.2.2 General Status Register (GSR) The general status register (GSR) is an 8-bit readable register that indicates the status of the CAN bus. Bit: 7 -- Initial value: R/W: 0 R 6 -- 0 R 5 -- 0 R 4 -- 0 R 3 GSR3 1 R 2 GSR2 1 R 1 GSR1 0 R 0 GSR0 0 R * Bits 7 to 4--Reserved: These bits are always read as 0. The write value should always be 0. * Bit 3--Reset Status Bit (GSR3): Indicates whether the HCAN module is in the normal operating state or the reset state. This bit cannot be modified. Bit 3: GSR3 0 Description Normal operating state [Setting condition] After an HCAN internal reset 1 Configuration mode [Reset condition] MCR0-initiated reset state or sleep mode (Initial value) Rev.2.0, 07/03, page 528 of 960 * Bit 2--Message Transmission Status Flag (GSR2): Flag that indicates whether the module is currently in the message transmission period. The "message transmission period" is the period from the start of message transmission (SOF) until the end of a 3-bit intermission interval after EOF (End of Frame). This bit cannot be modified. Bit 2: GSR2 0 1 Description Transmission in progress [Reset condition] Idle period (Initial value) * Bit 1--Transmit/Receive Warning Flag (GSR1): Flag that indicates an error warning. This bit cannot be modified. it 1: GSR1 0 1 Description [Reset condition] When TEC < 96 and REC < 96 or TEC 256 When TEC 96 or REC 96 (Initial value) * Bit 0--Bus Off Flag (GSR0): Flag that indicates the bus off state. This bit cannot be modified. Bit 0: GSR0 0 1 Description [Reset condition] Recovery from bus off state When TEC 256 (bus off state) (Initial value) 16.2.3 Bit Configuration Register (BCR) The bit configuration register (BCR) is a 16-bit readable/writable register that is used to set CAN bit timing parameters and the baud rate prescaler. Bit: 15 BCR7 Initial value: R/W: Bit: 0 R/W 7 BCR15 Initial value: R/W: 0 R/W 14 BCR6 0 R/W 6 BCR14 0 R/W 13 BCR5 0 R/W 5 BCR13 0 R/W 12 BCR4 0 R/W 4 BCR12 0 R/W 11 BCR3 0 R/W 3 BCR11 0 R/W 10 BCR2 0 R/W 2 BCR10 0 R/W 9 BCR1 0 R/W 1 BCR9 0 R/W 8 BCR0 0 R/W 0 BCR8 0 R/W Rev.2.0, 07/03, page 529 of 960 * Bits 15 and 14--Re-synchronization Jump Width (SJW): These bits set the maximum bit synchronization range. Bit 15: BCR7 0 Bit 14: BCR6 0 1 1 0 1 Description Maximum bit synchronization width = 1 time quantum Maximum bit synchronization width = 2 time quanta Maximum bit synchronization width = 3 time quanta Maximum bit synchronization width = 4 time quanta * Bits 13 to 8--Baud Rate Prescaler (BRP): These bits are used to set the CAN bus baud rate. Bit 13: BCR5 0 0 0 1 Bit 12: BCR4 0 0 0 1 Bit 11: BCR3 0 0 0 1 Bit 10: BCR2 0 0 0 1 Bit 9: BCR1 0 0 1 1 Bit 8: BCR0 0 1 0 1 Description 2 x system clock 4 x system clock 6 x system clock 128 x system clock (Initial value) 1-bit time 1-bit time (8-25 time quanta) SYNC_SEG PRSEG PHSEG1 PHSEG2 TSEG2 (time segment 2)* Quantum 2-8 1 TSEG1 (time segment 1)* 2-16 SYNC_SEG: Segment for establishing synchronization of nodes on the CAN bus. (Normal bit edge transitions occur in this segment.) PRSEG: Segment for compensating for physical delay between networks. PHSEG1: Buffer segment for correcting phase drift (positive). (This segment is extended when synchronization (re-synchronization) is established.) PHSEG2: Buffer segment for correcting phase drift (negative). (This segment is shortened when synchronization (re-synchronization) is established.) Note: * The time quanta value for TSEG1 and TSEG2 is the TSEG value + 1. Figure 16.2 Detailed Description of One Bit Rev.2.0, 07/03, page 530 of 960 HCAN bit rate calculation: Bit rate [b/s] = fCLK 2 x (BRP + 1) x (3 + TSEG1 + TSEG2) Note: fCLK = P (peripheral clock (/2)) The BCR values are used for BRP, TSEG1, and TSEG2. BCR Setting Constraints TSEG1 > TSEG2 = SJW (SJW = 1 to 4) 3 + TSEG1 + TSEG2 = 8 to 25 time quanta TSEG2 > B'001 (BRP = B'000000) TSEG2 > B'000 (BRP > B'000000) These constraints allow the setting range shown in table 16.4 for TSEG1 and TSEG2 in BCR. Table 16.4 Setting Range for TSEG1 and TSEG2 in BCR TSEG2 (BCR [14:12]) 001 TSEG1 (BCR [11:8]) 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 No Yes* Yes* Yes* Yes* Yes* Yes* Yes* Yes* Yes* Yes* Yes* Yes* 010 Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes 011 No Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes 100 No No Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes 101 No No No Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes 110 No No No No Yes Yes Yes Yes Yes Yes Yes Yes Yes 111 No No No No No Yes Yes Yes Yes Yes Yes Yes Yes Notes: The time quanta value for TSEG1 and TSEG2 is the TSEG value + 1. * Setting is enabled except when BRP[13:8] = B'000000. Rev.2.0, 07/03, page 531 of 960 * Bit 7--Bit Sample Point (BSP): Sets the point at which data is sampled. Bit 7: BCR15 0 1 Description Bit sampling at one point (end of time segment 1 (TSEG1)) (Initial value) Bit sampling at three points (end of time segment 1 (TSEG1), and 1 time quantum before and after) * Bits 6 to 4--Time Segment 2 (TSEG2): These bits are used to set the segment for correcting 1bit time error. A value from 2 to 8 can be set. Bit 6: BCR14 0 Bit 5: BCR13 0 Bit 4: BCR12 0 1 1 0 1 1 0 0 1 1 0 1 Description Setting prohibited TSEG2 (PHSEG2) = 2 time quanta TSEG2 (PHSEG2) = 3 time quanta TSEG2 (PHSEG2) = 4 time quanta TSEG2 (PHSEG2) = 5 time quanta TSEG2 (PHSEG2) = 6 time quanta TSEG2 (PHSEG2) = 7 time quanta TSEG2 (PHSEG2) = 8 time quanta (Initial value) * Bits 3 to 0--Time Segment 1 (TSEG1): These bits are used to set the segment for absorbing output buffer, CAN bus, and input buffer delay. A value from 4 to 16 can be set. Bit 3: BCR11 0 0 0 0 0 1 Bit 2: BCR10 0 0 0 0 1 1 Bit 1: BCR9 0 0 1 1 0 1 Bit 0: BCR8 0 1 0 1 0 1 Description Setting prohibited Setting prohibited Setting prohibited TSEG1 (PRSEG + PHSEG1) = 4 time quanta TSEG1 (PRSEG + PHSEG1) = 5 time quanta TSEG1 (PRSEG + PHSEG1) = 16 time quanta (Initial value) Rev.2.0, 07/03, page 532 of 960 16.2.4 Mailbox Configuration Register (MBCR) The mailbox configuration register (MBCR) is a 16-bit readable/writable register that is used to set mailbox (buffer) transmission/reception. Bit: 15 MBCR7 14 MBCR6 13 MBCR5 12 MBCR4 11 MBCR3 10 MBCR2 9 MBCR1 8 -- 1 R 0 MBCR8 Initial value: R/W: Bit: 0 R/W 7 0 R/W 6 0 R/W 5 0 R/W 4 0 R/W 3 0 R/W 2 0 R/W 1 MBCR9 MBCR15 MBCR14 MBCR13 MBCR12 MBCR11 MBCR10 Initial value: R/W: 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W * Bits 15 to 9 and 7 to 0--Mailbox Setting Register (MBCR7 to 1, MBCR15 to 8): These bits set the polarity of the corresponding mailboxes. Bit x: MBCRx 0 1 Description Corresponding mailbox is set for transmission Corresponding mailbox is set for reception (Initial value) * Bit 8--Reserved: This bit always reads 1. The write value should always be 1. 16.2.5 Transmit Wait Register (TXPR) The transmit wait register (TXPR) is a 16-bit readable/writable register that is used to set a transmit wait after a transmit message is stored in a mailbox (buffer) (CAN bus arbitration wait). Bit: 15 TXPR7 Initial value: R/W: Bit: 0 R/W 7 14 TXPR6 0 R/W 6 13 TXPR5 0 R/W 5 12 TXPR4 0 R/W 4 11 TXPR3 0 R/W 3 10 TXPR2 0 R/W 2 9 TXPR1 0 R/W 1 8 -- 0 R 0 TXPR8 0 R/W TXPR15 TXPR14 TXPR13 TXPR12 TXPR11 TXPR10 TXPR9 Initial value: R/W: 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W Rev.2.0, 07/03, page 533 of 960 * Bits 15 to 9 and 7 to 0--Transmit Wait Register (TXPR7 to 1, TXPR15 to 8): These bits set a CAN bus arbitration wait for the corresponding mailboxes. Bit x: TXPRx 0 Description Transmit message idle state in corresponding mailbox [Clearing condition] Message transmission completion and cancellation completion 1 Transmit message transmit wait in corresponding mailbox (CAN bus arbitration) x = 1 to 15 (Initial value) * Bit 8--Reserved: This bit always reads 0. The write value should always be 0. 16.2.6 Transmit Wait Cancel Register (TXCR) The transmit wait cancel register (TXCR) is a 16-bit readable/writable register that controls cancellation of transmit wait messages in mailboxes (buffers). Bit: 15 TXCR7 Initial value: R/W: Bit: 0 R/W 7 14 TXCR6 0 R/W 6 13 TXCR5 0 R/W 5 12 TXCR4 0 R/W 4 11 TXCR3 0 R/W 3 10 TXCR2 0 R/W 2 9 TXCR1 0 R/W 1 8 -- 0 R 0 TXCR8 0 R/W TXCR15 TXCR14 TXCR13 TXCR12 TXCR11 TXCR10 TXCR9 Initial value: R/W: 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W * Bits 15 to 9 and 7 to 0--Transmit Wait Cancel Register (TXCR7 to 1, TXCR15 to 8): These bits control cancellation of transmit wait messages in the corresponding HCAN mailboxes. Bit x: TXCRx 0 Description Transmit message cancellation idle state in corresponding mailbox (Initial value) [Clearing condition] Completion of TXPR clearing (when transmit message is canceled normally) 1 TXPR cleared for corresponding mailbox (transmit message cancellation) * Bit 8--Reserved: This bit always reads 0. The write value should always be 0. Rev.2.0, 07/03, page 534 of 960 16.2.7 Transmit Acknowledge Register (TXACK) The transmit acknowledge register (TXACK) is a 16-bit readable/writable register containing status flags that indicate normal completion of mailbox (buffer) message transmission. Bit: 15 TXACK7 14 TXACK6 13 TXACK5 12 TXACK4 11 TXACK3 10 TXACK2 9 TXACK1 8 -- 0 R 0 TXACK8 Initial value: R/W: Bit: 0 R/W 7 0 R/W 6 0 R/W 5 0 R/W 4 0 R/W 3 0 R/W 2 0 R/W 1 TXACK15 TXACK14 TXACK13 TXACK12 TXACK11 TXACK10 TXACK9 Initial value: R/W: 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W * Bits 15 to 9 and 7 to 0--Transmit Acknowledge Register (TXACK7 to 1, TXACK15 to 8): These bits indicate that transmission of a message in the corresponding HCAN mailbox has been completed normally. Bit x: TXACKx 0 1 Description [Clearing condition] Writing 1 (Initial value) Completion of message transmission for corresponding mailbox * Bit 8--Reserved: This bit is always read as 0. The write value should always be 0. Rev.2.0, 07/03, page 535 of 960 16.2.8 Abort Acknowledge Register (ABACK) The abort acknowledge register (ABACK) is a 16-bit readable/writable register containing status flags that indicate normal cancellation (aborting) of a mailbox (buffer) transmit messages. Bit: 15 14 13 12 11 10 9 8 -- 0 R 0 ABACK7 ABACK6 ABACK5 ABACK4 ABACK3 ABACK2 ABACK1 Initial value: R/W: Bit: 0 R/W 7 0 R/W 6 0 R/W 5 0 R/W 4 0 R/W 3 0 R/W 2 0 R/W 1 ABACK15 ABACK14 ABACK13 ABACK12 ABACK11 ABACK10 ABACK9 ABACK8 Initial value: R/W: 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W * Bits 15 to 9 and 7 to 0--Abort Acknowledge Register (ABACK7 to 1, ABACK15 to 8): These bits indicate that a transmit message in the corresponding mailbox has been canceled (aborted) normally. Bit x: ABACKx 0 1 Description [Clearing condition] Writing 1 (Initial value) Completion of transmit message cancellation for corresponding mailbox * Bit 8--Reserved: This bit is always read as 0. The write value should always be 0. Rev.2.0, 07/03, page 536 of 960 16.2.9 Receive Complete Register (RXPR) The receive complete register (RXPR) is a 16-bit readable/writable register containing status flags that indicate normal reception of messages (data frames or remote frames) in mailboxes (buffers). In the case of remote frame reception, the corresponding bit in the remote request register (RFPR) is also set. Bit: 15 RXPR7 Initial value: R/W: Bit: 0 R/W 7 14 RXPR6 0 R/W 6 13 RXPR5 0 R/W 5 12 RXPR4 0 R/W 4 11 RXPR3 0 R/W 3 10 RXPR2 0 R/W 2 9 RXPR1 0 R/W 1 8 RXPR0 0 R/W 0 RXPR8 0 R/W RXPR15 RXPR14 RXPR13 RXPR12 RXPR11 RXPR10 RXPR9 Initial value: R/W: 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W * Bits 15 to 0--Receive Complete Register (RXPR7 to 0, RXPR15 to 8): These bits indicate that a receive message has been received normally in the corresponding mailbox. Bit x: RXPRx 0 1 Description [Clearing condition] Writing 1 (Initial value) Completion of message (data frame or remote frame) reception in corresponding mailbox Rev.2.0, 07/03, page 537 of 960 16.2.10 Remote Request Register (RFPR) The remote request register (RFPR) is a 16-bit readable/writable register containing status flags that indicate normal reception of remote frames in mailboxes (buffers). When a bit in this register is set, the corresponding bit in the receive complete register (RXPR) is also set. Bit: 15 RFPR7 Initial value: R/W: Bit: 0 R/W 7 14 RFPR6 0 R/W 6 13 RFPR5 0 R/W 5 12 RFPR4 0 R/W 4 11 RFPR3 0 R/W 3 10 RFPR2 0 R/W 2 9 RFPR1 0 R/W 1 8 RFPR0 0 R/W 0 RFPR8 0 R/W RFPR15 RFPR14 RFPR13 RFPR12 RFPR11 RFPR10 RFPR9 Initial value: R/W: 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W * Bits 15 to 0--Remote Request Register (RFPR7 to 0, RFPR15 to 8): These bits indicate that a remote frame has been received normally in the corresponding mailbox. Bit x: RFPRx 0 1 Description [Clearing condition] Writing 1 (Initial value) Completion of remote frame reception in corresponding mailbox 16.2.11 Interrupt Register (IRR) The interrupt register (IRR) is a 16-bit readable/writable register containing status flags for the various interrupt sources. Bit: 15 IRR7 Initial value: R/W: Bit: 0 R/W 7 -- Initial value: R/W: 0 R 14 IRR6 0 R/W 6 -- 0 R 13 IRR5 0 R/W 5 -- 0 R 12 IRR4 0 R/W 4 IRR12 0 R/W 11 IRR3 0 R/W 3 -- 0 R 10 IRR2 0 R 2 -- 0 R 9 IRR1 0 R 1 IRR9 0 R 8 IRR0 1 R/W 0 IRR8 0 R/W Rev.2.0, 07/03, page 538 of 960 * Bit 15--Overload Frame Interrupt Flag (IRR7): Status flag indicating that the HCAN has transmitted an overload frame. Bit 15: IRR7 0 1 Description [Clearing condition] Writing 1 Overload frame transmission [Setting conditions] Error active/error passive state * When overload frame is transmitted (Initial value) * Bit 14--Bus Off Interrupt Flag (IRR6): Status flag indicating the bus off state caused by the transmit error counter. Bit 14: IRR6 0 1 Description [Clearing condition] Writing 1 Bus off state caused by transmit error [Setting condition] When TEC 256 (Initial value) * Bit 13--Error Passive Interrupt Flag (IRR5): Status flag indicating the error passive state caused by the transmit/receive error counter. Bit 13: IRR5 0 1 Description [Clearing condition] Writing 1 Error passive state caused by transmit/receive error [Setting condition] When TEC 128 or REC 128 (Initial value) * Bit 12--Receive Overload Warning Interrupt Flag (IRR4): Status flag indicating the error warning state caused by the receive error counter. Bit 12: IRR4 0 1 Description [Clearing condition] Writing 1 Error warning state caused by receive error [Setting condition] When REC 96 (Initial value) Rev.2.0, 07/03, page 539 of 960 * Bit 11--Transmit Overload Warning Interrupt Flag (IRR3): Status flag indicating the error warning state caused by the transmit error counter. Bit 11: IRR3 0 1 Description [Clearing condition] Writing 1 Error warning state caused by transmit error [Setting condition] When TEC 96 (Initial value) * Bit 10--Remote Frame Request Interrupt Flag (IRR2): Status flag indicating that a remote frame has been received in a mailbox. Bit 10: IRR2 0 1 Description [Clearing condition] Clearing of all bits in RFPR (remote request wait register) Remote frame received and stored in mailbox [Setting conditions] When remote frame reception is completed. When corresponding MBIMR = 0. (Initial value) * Bit 9--Receive Message Interrupt Flag (IRR1): Status flag indicating that a mailbox receive message has been received normally. Bit 9: IRR1 0 Description [Clearing condition] Clearing of all bits in RXPR (receive complete register) when MBIMR is 0 (Initial value) Data frame or remote frame received and stored in mailbox [Setting conditions] When data frame or remote frame reception is completed. When corresponding MBIMR = 0. 1 Rev.2.0, 07/03, page 540 of 960 * Bit 8--Reset Interrupt Flag (IRR0): Status flag indicating that the HCAN module has been reset. This bit cannot be masked in the interrupt mask register (IMR). If this bit is not cleared after a power-on reset or recovery from software standby mode, interrupt processing will be executed immediately when interrupts are enabled by the interrupt controller. Bit 8: IRR0 0 1 Description [Clearing condition] Writing 1 Interrupt request (OVR) due to power-on reset or transition to software standby mode (Initial value) [Setting condition] When reset processing is completed after power-on reset or software standby mode transition * Bits 7 to 5, 3, and 2--Reserved: These bits always read 0. The write value should always be 0. * Bit 4--Bus Operation Interrupt Flag (IRR12): Status flag indicating detection of a dominant bit due to bus operation when the HCAN module is in HCAN sleep mode. Bit 4: IRR12 0 Description CAN bus idle state [Clearing condition] Writing 1 1 CAN bus operation in HCAN sleep mode [Setting condition] Bus operation (dominant bit detection) in HCAN sleep mode (Initial value) * Bit 1--Unread Interrupt Flag (IRR9): Status flag indicating that a receive message has been overwritten while still unread. Bit 1: IRR9 0 1 Description [Clearing condition] Clearing of all bits in UMSR (unread message status register) (Initial value) Unread message overwrite [Setting condition] When UMSR (unread message status register) is set Rev.2.0, 07/03, page 541 of 960 * Bit 0--Mailbox Empty Interrupt Flag (IRR8): Status flag indicating that the next transmit message can be stored in the mailbox. Bit 0: IRR8 0 1 Description [Clearing condition] Writing 1 (Initial value) Transmit message has been transmitted or aborted, and new message can be stored [Setting condition] When TXPR (transmit wait register) is cleared by completion of transmission or completion of transmission abort 16.2.12 Mailbox Interrupt Mask Register (MBIMR) The mailbox interrupt mask register (MBIMR) is a 16-bit readable/writable register containing flags that enable or disable individual mailbox (buffer) interrupt requests. Bit: 15 MBIMR7 14 MBIMR6 13 MBIMR5 12 MBIMR4 11 MBIMR3 10 MBIMR2 9 MBIMR1 8 MBIMR0 Initial value: R/W: Bit: 1 R/W 7 1 R/W 6 1 R/W 5 1 R/W 4 1 R/W 3 1 R/W 2 1 R/W 1 1 R/W 0 MBIMR8 MBIMR15 MBIMR14 MBIMR13 MBIMR12 MBIMR11 MBIMR10 MBIMR9 Initial value: R/W: 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W * Bits 15 to 0--Mailbox Interrupt Mask (MBIMR7 to 0, MBIMR15 to 8): Flags that enable or disable individual mailbox interrupt requests. Bit x: MBIMRx 0 Description [Transmitting] Interrupt request to CPU due to TXPR clearing [Receiving] Interrupt request to CPU due to RXPR setting 1 Interrupt requests to CPU disabled (Initial value) Rev.2.0, 07/03, page 542 of 960 16.2.13 Interrupt Mask Register (IMR) The interrupt mask register (IMR) is a 16-bit readable/writable register containing flags that enable or disable requests by individual interrupt sources. Bit: 15 IMR7 Initial value: R/W: Bit: 1 R/W 7 -- Initial value: R/W: 1 R 14 IMR6 1 R/W 6 -- 1 R 13 IMR5 1 R/W 5 -- 1 R 12 IMR4 1 R/W 4 IMR12 1 R/W 11 IMR3 1 R/W 3 -- 1 R 10 IMR2 1 R/W 2 -- 1 R 9 IMR1 1 R/W 1 IMR9 1 R/W 8 -- 0 -- 0 IMR8 1 R/W * Bit 15--Overload Frame Interrupt Mask (IMR7): Enables or disables overload frame interrupt requests. Bit 15: IMR7 0 1 Description Overload frame interrupt request (OVR) to CPU by IRR7 enabled Overload frame interrupt request (OVR) to CPU by IRR7 disabled (Initial value) * Bit 14--Bus Off Interrupt Mask (IMR6): Enables or disables bus off interrupt requests caused by the transmit error counter. Bit 14: IMR6 0 1 Description Bus off interrupt request (ERS) to CPU by IRR6 enabled Bus off interrupt request (ERS) to CPU by IRR6 disabled (Initial value) * Bit 13--Error Passive Interrupt Mask (IMR5): Enables or disables error passive interrupt requests caused by the transmit/receive error counter. Bit 13: IMR5 0 1 Description Error passive interrupt request (ERS) to CPU by IRR5 enabled Error passive interrupt request (ERS) to CPU by IRR5 disabled (Initial value) Rev.2.0, 07/03, page 543 of 960 * Bit 12--Receive Overload Warning Interrupt Mask (IMR4): Enables or disables error warning interrupt requests caused by the receive error counter. Bit 12: IMR4 0 1 Description REC error warning interrupt request (OVR) to CPU by IRR4 enabled REC error warning interrupt request (OVR) to CPU by IRR4 disabled (Initial value) * Bit 11--Transmit Overload Warning Interrupt Mask (IMR3): Enables or disables error warning interrupt requests caused by the transmit error counter. Bit 11: IMR3 0 1 Description TEC error warning interrupt request (OVR) to CPU by IRR3 enabled TEC error warning interrupt request (OVR) to CPU by IRR3 disabled (Initial value) * Bit 10--Remote Frame Request Interrupt Mask (IMR2): Enables or disables remote frame reception interrupt requests. Bit 10: IMR2 0 1 Description Remote frame reception interrupt request (OVR) to CPU by IRR2 enabled Remote frame reception interrupt request (OVR) to CPU by IRR2 disabled (Initial value) * Bit 9--Receive Message Interrupt Mask (IMR1): Enables or disables message reception interrupt requests. Bit 9: IMR1 0 1 Description Message reception interrupt request (RM) to CPU by IRR1 enabled Message reception interrupt request (RM) to CPU by IRR1 disabled (Initial value) * Bit 8--Reserved: This bit is always read as 0. The write value should always be 0. * Bits 7 to 5, 3, and 2--Reserved: These bits are always read as 1. The write value should always be 1. Rev.2.0, 07/03, page 544 of 960 * Bit 4--Bus Operation Interrupt Mask (IMR12): Enables or disables interrupt requests due to bus operation in sleep mode. Bit 4: IMR12 0 1 Description Bus operation interrupt request (OVR) to CPU by IRR12 enabled Bus operation interrupt request (OVR) to CPU by IRR12 disabled (Initial value) * Bit 1--Unread Interrupt Mask (IMR9): Enables or disables unread receive message overwrite interrupt requests. Bit 1: IMR9 0 1 Description Unread message overwrite interrupt request (OVR) to CPU by IRR9 enabled Unread message overwrite interrupt request (OVR) to CPU by IRR9 disabled (Initial value) * Bit 0--Mailbox Empty Interrupt Mask (IMR8): Enables or disables mailbox empty interrupt requests. Bit 0: IMR8 0 1 Description Mailbox empty interrupt request (SLE) to CPU by IRR8 enabled Mailbox empty interrupt request (SLE) to CPU by IRR8 disabled (Initial value) 16.2.14 Receive Error Counter (REC) The receive error counter (REC) is an 8-bit read-only register that functions as a counter indicating the number of receive message errors on the CAN bus. The count value is stipulated in the CAN protocol. This register cannot be modified. Bit: 7 6 5 4 3 2 1 0 Initial value: R/W: 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R Rev.2.0, 07/03, page 545 of 960 16.2.15 Transmit Error Counter (TEC) The transmit error counter (TEC) is an 8-bit read-only register that functions as a counter indicating the number of transmit message errors on the CAN bus. The count value is stipulated in the CAN protocol. This register cannot be modified. Bit: 7 6 5 4 3 2 1 0 Initial value: R/W: 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 16.2.16 Unread Message Status Register (UMSR) The unread message status register (UMSR) is a 16-bit readable/writable register containing status flags that indicate, for individual mailboxes (buffers), that a received message has been overwritten by a new receive message before being read. Bit: 15 UMSR7 14 UMSR6 13 UMSR5 12 UMSR4 11 UMSR3 10 UMSR2 9 UMSR1 8 UMSR0 Initial value: R/W: Bit: 0 R/W 7 0 R/W 6 0 R/W 5 0 R/W 4 0 R/W 3 0 R/W 2 0 R/W 1 UMSR9 0 R/W 0 UMSR8 UMSR15 UMSR14 UMSR13 UMSR12 UMSR11 UMSR10 Initial value: R/W: 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W * Bits 15 to 0--Unread Message Status Flags (UMSR7 to 0, UMSR15 to 8): Status flags indicating that an unread receive message has been overwritten. When an unread receive message is overwritten by a new receive message, the old data is lost. Bit x: UMSRx 0 1 Description [Clearing condition] Writing 1 Unread receive message is overwritten by a new message [Setting condition] When a new message is received before RXPR is cleared x = 0 to 15 (Initial value) Rev.2.0, 07/03, page 546 of 960 16.2.17 Local Acceptance Filter Masks (LAFML, LAFMH) The local acceptance filter masks (LAFML, LAFMH) are 16-bit readable/writable registers that filter receive messages to be stored in the receive-only mailbox (MC0, MD0) according to the identifier. In these registers, consist of LAFMH15: MSB to LAFMH5: LSB are 11 standard/extended identifier bits, and LAFMH1: MSB to LAFML0: LSB are 18 extended identifier bits. LAFML Bit: 15 LAFML7 14 LAFML6 13 LAFML5 12 LAFML4 11 LAFML3 10 LAFML2 9 LAFML1 8 LAFML0 Initial value: R/W: Bit: 0 R/W 7 0 R/W 6 0 R/W 5 0 R/W 4 0 R/W 3 0 R/W 2 0 R/W 1 0 R/W 0 LAFML8 LAFML15 LAFML14 LAFML13 LAFML12 LAFML11 LAFML10 LAFML9 Initial value: R/W: LAFMH Bit: 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 15 14 13 12 -- 0 R 4 11 -- 0 R 3 10 -- 0 R 2 9 8 LAFMH7 LAFMH6 LAFMH5 LAFMH1 LAFMH0 Initial value: R/W: Bit: 0 R/W 7 0 R/W 6 0 R/W 5 0 R/W 1 0 R/W 0 LAFMH15 LAFMH14 LAFMH13 LAFMH12 LAFMH11 LAFMH10 LAFMH9 LAFMH8 Initial value: R/W: 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W Rev.2.0, 07/03, page 547 of 960 * LAFMH Bits 7 to 0 and 15 to 13-11-Bit Identifier Filter (LAFMH7 to 5, LAFMH15 to 8): Filter mask bits for the first 11 bits of the receive message identifier (for both standard and extended identifiers). Bit x: LAFMHx 0 1 Description Stored in MC0, MD0 (receive-only mailbox) depending on bit match between MC0 message identifier and receive message identifier (Initial value) Stored in MC0, MD0 (receive-only mailbox) regardless of bit match between MC0 message identifier and receive message identifier * LAFMH Bits 12 to 10--Reserved: These bits are always read as 0. The write value should always be 0. * LAFMH Bits 9 and 8, LAFML bits 15 to 0-18-Bit Identifier Filter (LAFMH1, 0, LAFML7 to 0, LAFML15 to 8): Filter mask bits for the 18 bits of the receive message identifier (extended). Bit x: LAFMHx LAFMLx 0 1 Description Stored in MC0 (receive-only mailbox) depending on bit match between MC0 message identifier and receive message identifier (Initial value) Stored in MC0 (receive-only mailbox) regardless of bit match between MC0 message identifier and receive message identifier Rev.2.0, 07/03, page 548 of 960 16.2.18 Message Control (MC0 to MC15) The message control register sets (MC0 to MC15) consist of eight 8-bit readable/writable registers (MCx[1] to MCx[8]). The HCAN has 16 sets of these registers (MC0 to MC15). The initial value of these registers is undefined, so they must be initialized (by writing 0 or 1). MCx [1] Bit: 7 6 5 4 3 DLC3 Initial value: R/W: MCx [2] Bit: 7 6 5 4 3 2 1 0 -- R/W -- R/W -- R/W -- R/W -- R/W 2 DLC2 -- R/W 1 DLC1 -- R/W 0 DLC0 -- R/W Initial value: R/W: MCx [3] Bit: -- R/W -- R/W -- R/W -- R/W -- R/W -- R/W -- R/W -- R/W 7 6 5 4 3 2 1 0 Initial value: R/W: MCx [4] Bit: -- R/W -- R/W -- R/W -- R/W -- R/W -- R/W -- R/W -- R/W 7 6 5 4 3 2 1 0 Initial value: R/W: MCx [5] Bit: -- R/W -- R/W -- R/W -- R/W -- R/W -- R/W -- R/W -- R/W 7 6 5 4 RTR 3 IDE 2 1 0 STD_ID2 STD_ID1 STD_ID0 EXD_ID17 EXD_ID16 Initial value: R/W: -- R/W -- R/W -- R/W -- R/W -- R/W -- R/W -- R/W -- R/W Rev.2.0, 07/03, page 549 of 960 MCx [6] Bit: 7 6 5 4 3 2 1 0 STD_ID10 STD_ID9 STD_ID8 STD_ID7 STD_ID6 STD_ID5 STD_ID4 STD_ID3 Initial value: R/W: MCx [7] Bit: -- R/W -- R/W -- R/W -- R/W -- R/W -- R/W -- R/W -- R/W 7 6 5 4 3 2 1 0 EXD_ID7 EXD_ID6 EXD_ID5 EXD_ID4 EXD_ID3 EXD_ID2 EXD_ID1 EXD_ID0 Initial value: R/W: MCx [8] Bit: -- R/W -- R/W -- R/W -- R/W -- R/W -- R/W -- R/W -- R/W 7 6 5 4 3 2 1 0 EXD_ID15 EXD_ID14 EXD_ID13 EXD_ID12 EXD_ID11 EXD_ID10 EXD_ID9 EXD_ID8 Initial value: R/W: -- R/W -- R/W -- R/W -- R/W -- R/W -- R/W -- R/W -- R/W * MCx[1] Bits 7 to 4--Reserved: The initial value of these bits is undefined; they must be initialized (by writing 0 or 1). * MCx[1] Bits 3 to 0: Data Length Code (DLC3 to 0): These bits indicate the required length of data frames and remote frames. Bit 3: DLC3 0 Bit 2: DLC2 0 Bit 1: DLC1 0 Bit 0: DLC0 0 1 1 0 1 1 0 0 1 1 0 1 1 * * * Description Data length = 0 bytes Data length = 1 byte Data length = 2 bytes Data length = 3 bytes Data length = 4 bytes Data length = 5 bytes Data length = 6 bytes Data length = 7 bytes Data length = 8 bytes *: Don't care * MCx[2] Bits 7 to 0--Reserved: The initial value of these bits is undefined; they must be initialized (by writing 0 or 1). Rev.2.0, 07/03, page 550 of 960 * MCx[3] Bits 7 to 0--Reserved: The initial value of these bits is undefined; they must be initialized (by writing 0 or 1). * MCx[4] Bits 7 to 0--Reserved: The initial value of these bits is undefined; they must be initialized (by writing 0 or 1). * MCx[6] Bits 7 to 0: Standard Identifier (STD_ID10 to STD_ID3) MCx[5] Bits 7 to 5: Standard Identifier (STD_ID2 to STD_ID0) These bits set the identifier (standard identifier) of data frames and remote frames. Standard identifier SOF ID10 ID9 ID8 ID7 ID6 ID5 ID4 ID3 ID2 ID1 ID0 RTR SRR IDE STD_IDxx Figure 16.3 Standard Identifier * MCx[5] Bit 4: Remote Transmission Request (RTR): Used to distinguish between data frames and remote frames. Bit 4: RTR 0 1 Description Data frame Remote frame * MCx[5] Bit 3: Identifier Extension (IDE): Used to distinguish between the standard format and extended format of data frames and remote frames. Bit 3: IDE 0 1 Description Standard format Extended format * MCx[5] Bit 2--Reserved: The initial value of this bit is undefined; it must be initialized (by writing 0 or 1). * MCx[5] Bits 1 and 0: Extended Identifier (EXD_ID17, EXD_ID16) MCx[8] Bits 7 to 0: Extended Identifier (EXD_ID15 to EXD_ID8) MCx[7] Bits 7 to 0: Extended Identifier (EXD_ID7 to EXD_ID0) These bits set the identifier (extended identifier) of data frames and remote frames. Rev.2.0, 07/03, page 551 of 960 Extended Identifier IDE ID17 ID16 ID15 ID14 ID13 ID12 ID11 ID10 ID9 ID8 ID7 ID6 ID5 EXD_IDxx ID4 ID3 ID2 ID1 ID0 RTR R1 EXD_IDxx Figure 16.4 Extended Identifier 16.2.19 Message Data (MD0 to MD15) The message data register sets (MD0 to MD15) consist of eight 8-bit readable/writable registers (MDx[1] to MDx[8]). The HCAN has 16 sets of these registers (MD0 to MD15). The initial value of these registers is undefined, so they must be initialized (by writing 0 or 1). MDx[1] Message Data 1 Bit: 7 6 5 4 3 2 1 0 Initial value: R/W: -- R/W -- R/W -- R/W -- R/W -- R/W -- R/W -- R/W -- R/W MDx[2] Message Data 2 Bit: 7 6 5 4 3 2 1 0 Initial value: R/W: -- R/W -- R/W -- R/W -- R/W -- R/W -- R/W -- R/W -- R/W MDx[3] Message Data 3 Bit: 7 6 5 4 3 2 1 0 Initial value: R/W: -- R/W -- R/W -- R/W -- R/W -- R/W -- R/W -- R/W -- R/W Rev.2.0, 07/03, page 552 of 960 MDx[4] Message Data 4 Bit: 7 6 5 4 3 2 1 0 Initial value: R/W: -- R/W -- R/W -- R/W -- R/W -- R/W -- R/W -- R/W -- R/W MDx[5] Message Data 5 Bit: 7 6 5 4 3 2 1 0 Initial value: R/W: -- R/W -- R/W -- R/W -- R/W -- R/W -- R/W -- R/W -- R/W MDx[6] Message Data 6 Bit: 7 6 5 4 3 2 1 0 Initial value: R/W: -- R/W -- R/W -- R/W -- R/W -- R/W -- R/W -- R/W -- R/W MDx[7] Message Data 7 Bit: 7 6 5 4 3 2 1 0 Initial value: R/W: -- R/W -- R/W -- R/W -- R/W -- R/W -- R/W -- R/W -- R/W MDx[8] Message Data 8 Bit: 7 6 5 4 3 2 1 0 Initial value: R/W: -- R/W -- R/W -- R/W -- R/W -- R/W -- R/W -- R/W -- R/W Rev.2.0, 07/03, page 553 of 960 16.3 Operation The SH7055SF has an on-chip HCAN module with two channels, each of which can be controlled independently. Except for pin states, both channels have identical specifications, and so control should be carried out in the same way for both. 16.3.1 Hardware Reset and Software Reset There are two ways of resetting the HCAN: Hardware reset and software reset. Hardware Reset (Power-on Reset or Hardware/Software Standby): The MCR reset request bit (MCR0) in MCR and the reset state bit (GSR3) in GSR within the HCAN are automatically set and initialized (hardware reset). At the same time, all internal registers are initialized. However mailbox (RAM) contents are not initialized. A flowchart of this reset is shown in figure 16.5. Software Reset (Write to MCR0): In normal operation HCAN is initialized by setting the MCR reset request bit (MCR0) in MCR (software reset). With this kind of reset, if the CAN controller is performing a communication operation (transmission or reception), the initialization state is not entered until the message has been completed. During initialization, the reset state bit (GSR3) in GSR is set. In this kind of initialization, the error counters (TEC and REC) are initialized but other registers and RAM are not. A flowchart of this reset is shown in figure 16.6. Rev.2.0, 07/03, page 554 of 960 Hardware reset MCR0 = 1 (automatic) IRR0 = 1 (automatic) GSR3 = 1 (automatic) Initialization of HCAN module Bit configuration mode Period in which BCR, MBCR, etc., are initialized Clear IRR0 HCAN port setting BCR setting MBCR setting Mailbox initialization Message transmission method initialization MCR0 = 0 GSR3 = 0? Yes IMR setting (interrupt mask setting) NBIMR setting (interrupt mask setting) MC[x] setting (receive identifier setting) LAFM setting (receive identifier mask setting) No GSR3 = 0 & 11 recessive bits received? Yes CAN bus communication enabled No : Settings by user : Processing by hardware Figure 16.5 Hardware Reset Flowchart Rev.2.0, 07/03, page 555 of 960 MCR0 = 1 Bus idle? Yes GSR3 = 1 (automatic) No Initialization of REC and TEC only Clear IRR0 HCAN port setting BCR setting MBCR setting Mailbox initialization Message transmission method initialization OK? Yes MCR0 = 0 Correction No GSR3 = 0? Yes No IMR setting NBIMR setting MC[x] setting LAFM setting OK? Yes Correction No GSR3 = 0 & 11 recessive bits received? Yes CAN bus communication enabled No : Settings by user : Processing by hardware Figure 16.6 Software Reset Flowchart Rev.2.0, 07/03, page 556 of 960 16.3.2 Initialization after a Hardware Reset After a hardware reset, the following initialization processing should be carried out: 1. Clearing of IRR0 bit in interrupt register (IRR) 2. HCAN pin port settings 3. Bit rate setting 4. Mailbox transmit/receive settings 5. Mailbox (buffer) initialization 6. Message transmission method setting These initial settings must be made while the HCAN is in bit configuration mode. Configuration mode is a state in which the reset request bit (MCR0) in the master control register (MCR) is 1 and the reset status bit in the general status register (GSR) is also 1 (GSR3 = 1). Configuration mode is exited by clearing the reset request bit in MCR to 0; when MCR0 is cleared to 0, the HCAN automatically clears the reset state bit (GSR3) in the general status register (GSR). The power-up sequence then begins, and communication with the CAN bus is possible as soon as the sequence ends. The power-up sequence consists of the detection of 11 consecutive recessive bits. IRR0 Clearing: The reset interrupt flag (IRR0) is always set after a power-on reset or recovery from software standby mode. As an HCAN interrupt is initiated immediately when interrupts are enabled, IRR0 should be cleared. HCAN Pin Port Settings: HCAN pin port settings must be made during or before bit configuration. Refer to the section 20, Pin Function Controller (PFC), for details of the setting method. The SH7055SF has two on-chip HCAN channels, which can be used in either of the following ways: 1. Two-channel 16-buffer HCAN 2. One-channel 32-buffer HCAN An example of 2-channel/16-buffer independent use is shown in figure 16.7, and an example of 2channel/32-buffer use in figure 16.8. Rev.2.0, 07/03, page 557 of 960 HTxD0 HCAN0 (16 buffers) HRxD0 PB10/TxD4/HTxD0/TO8G PB11/RxD4/HRxD0/TO8H HTxD1 HCAN1 (16 buffers) HRxD1 PL10/HTxD0/HTxD1/HTxD0 & HTxD1 PL10/HRxD0/HRxD1/HTxD0 & HRxD1 Figure 16.7 Example of 2-Channel/16-Buffer Independent Use HTxD0 HCAN0 (16 buffers) HRxD0 HTxD1 HCAN1 (16 buffers) HRxD1 PL10/HTxD0/HTxD1/HTxD0&HTxD1 PL10/HRxD0/HRxD1/HRxD0&HRxD1 Figure 16.8 Example of 1-Channel/32-Buffer Use Rev.2.0, 07/03, page 558 of 960 Bit Rate Settings: As bit rate settings, a baud rate setting and bit timing setting must be made each time a CAN node begins communication. The baud rate and bit timing settings are made in the bit configuration register (BCR). Notes: 1. BCR can be written to at all times, but should only be modified in configuration mode. 2. Settings should be made so that all CAN controllers connected to the CAN bus have the same baud rate and bit width. 3. Limits for the settable variables (TSEG1, TSEG2, BRP, sample point, and SJW) are shown in table 16.5. Table 16.5 BCR Setting Limits Name Time segment 1 Time segment 2 Baud rate prescaler Sample point Re-synchronization jump width Abbreviation TSEG1 TSEG2 BRP SAM SJW Min. Value 4 2 2 1 1 Max. Value 16 8 128 3 4 Unit TQ TQ System clock Point TQ Settable Variable Limits * The bit width consists of the total of the settable time quanta (TQ). TQ (number of system clocks) is determined by the baud rate prescaler (BRP). TQ = (2 x (BRP + 1))/(fCLK/2) fCLK = P * The minimum value of SJW is stipulated in the CAN specifications. 4 SJW 1 * The minimum value of TSEG1 is stipulated in the CAN specifications. TSEG1 TSEG2 * The minimum value of TSEG2 is stipulated in the CAN specifications. TSEG2 (1 + SJW) The following formula is used to calculate the baud rate. Bit rate [b/s] = fCLK 2 x (BRP + 1) x (3 + TSEG1 + TSEG2) Note: fCLK = P (peripheral clock: /2] The BCR values are used for BRP, TSEG1, and TSEG2. Example: With a 1 Mb/s baud rate and a 40 MHz input clock: Rev.2.0, 07/03, page 559 of 960 1 Mb/s = 20 MHz 2 x (0 + 1) x (3 + 4 + 3) Set Values fCLK BRP TSEG1 TSEG2 40 MHz/2 0 (B'000000) 4 (B'0100) 3 (B'011) Actual Values -- System clock x 2 5TQ 4TQ Mailbox Transmit/Receive Settings: HCAN0 and HCAN1 each have 16 mailboxes. Mailbox 0 is receive-only, while mailboxes 1 to 15 can be set for transmission or reception. Mailboxes that can be set for transmission or reception must be designated either for transmission use or for reception use before communication begins. The Initial status of mailboxes 1 to 15 is for transmission (while mailbox 0 is for reception only). Mailbox transmit/receive settings are not initialized by a software reset. * Setting for transmission Transmit mailbox setting (mailboxes 1 to 15) Clearing a bit to 0 in the mailbox configuration register (MBCR) designates the corresponding mailbox for transmission use. After a reset, mailboxes are initialized for transmission use, so this setting is not necessary. * Setting for reception Transmit/receive mailbox setting (mailboxes 1 to 15) Setting a bit to 1 in the mailbox configuration register (MBCR) designates the corresponding mailbox for reception use. When setting mailboxes for reception, to improve message transmission efficiency, high-priority messages should be set in low-to-high mailbox order (priority order: mailbox 1 (MCx[1]) > mailbox 15 (MCx[15])). * Receive-only mailbox (mailbox 0) No setting is necessary, as this mailbox is always used for reception. Mailbox (Message Control/Data (MCx[x], MDx[x]) Initial Settings: After power is supplied, all registers and RAM (message control/data, control registers, status registers, etc.) are initialized. Message control/data (MCx[x], MDx[x]) only are in RAM, and so their values are undefined. Initial values must therefore be set in all the mailboxes (by writing 0s or 1s). Setting the Message Transmission Method: Either of the following message transmission methods can be selected with the message transmission method bit (MCR2) in the master control register (MCR): 1. Transmission order determined by message identifier priority 2. Transmission order determined by mailbox number priority Rev.2.0, 07/03, page 560 of 960 When the message identifier priority method is selected, if a number of messages are designated as waiting for transmission (TXPR = 1), messages are stored in the transmit buffer in low-to-high mailbox order (priority order: mailbox 1 > 15). CAN bus arbitration is then carried out for the messages in the transmit buffer, and message transmission is performed when the bus is acquired. When the mailbox number priority method is selected, if a number of messages are designated as waiting for transmission (TXPR = 1), the message with the highest priority set in the message identifier (MCx[5]-MCx[8]) is stored in the transmit buffer. CAN bus arbitration is then carried out for the message in the transmit buffer, and message transmission is performed when the transmission right is acquired. When the TXPR bit is set, internal arbitration is performed again, and the highest-priority message is found and stored in the transmit buffer. 16.3.3 Transmit Mode Message transmission is performed using mailboxes 1 to 15. The transmission procedure is described below, and a transmission flowchart is shown in figure 16.9. 1. Initialization (after hardware reset only) a. Clearing of IRR0 bit in interrupt register (IRR) b. HCAN pin port settings c. Bit rate settings d. Mailbox transmit/receive settings e. Mailbox initialization f. Message transmission method setting 2. Interrupt and transmit data settings a. Interrupt setting b. Arbitration field setting c. Control field setting d. Data field setting 3. Message transmission and interrupts a. Message transmission wait b. Message transmission completion and interrupt c. Message transmission abort d. Message retransmission Rev.2.0, 07/03, page 561 of 960 Initialization (after Hardware Reset Only): These settings should be made while the HCAN is in bit configuration mode. 1. IRR0 clearing The reset interrupt flag (IRR0) is always set after a power-on reset or recovery from software standby mode. As an HCAN interrupt is initiated immediately when interrupts are enabled, IRR0 should be cleared. 2. HCAN pin port settings To prevent erroneous identification of CAN bus data, HCAN pin port settings should be made first. See HCAN Pin Port Settings in section 16.3.2, Initialization after a Hardware Reset, and section 20, Pin Function Controller, for details. 3. Bit rate settings Set values relating to the CAN bus communication speed and re-synchronization. See Bit Rate Settings in section 16.3.2, Initialization after a Hardware Reset, for details. 4. Mailbox transmit/receive settings Mailbox transmit/receive settings should be made in advance. A total of 30 mailbox can be set for transmission or reception (mailboxes 1 to 15 in HCAN0 and HCAN1). To set a mailbox for transmission, clear the corresponding bit to 0 in the mailbox configuration register (MBCR). See Mailbox Transmit/Receive Settings in section 16.3.2, Initialization after a Hardware Reset, for details. 5. Mailbox initialization As message control/data registers (MCx[x], MDx[x]) are configured in RAM, their initial values after powering on are undefined, and so bit initialization is necessary. Write 0s or 1s to the mailboxes. See Mailbox (Message Control/Data (MCx[x], MDx[x]) Initial Settings in section 16.3.2, Initialization after a Hardware Reset, for details. 6. Message transmission method setting Set the transmission method for mailboxes designated for transmission. The following two transmission methods can be used. See Setting the Message Transmission Method in section 16.3.2, Initialization after a Hardware Reset, for details. a. Transmission order determined by message identifier priority b. Transmission order determined by mailbox number priority Rev.2.0, 07/03, page 562 of 960 Initialization (after hardware reset only) IRR0 clearing HCAN port setting BCR setting MBCR setting Mailbox initialization Message transmission method setting Interrupt settings Transmit data setting Arbitration field setting Control field setting Data field setting Message transmission wait TXPR setting Bus idle? Yes Message transmission GSR2 = 0 (during transmission only) No Transmission completed? Yes IMR8 = 1? No Interrupt to CPU No Yes No TXACK = 1? Yes Clear TXACK Clear IRR8 : Settings by user End of transmission : Processing by hardware Figure 16.9 Transmission Flowchart Rev.2.0, 07/03, page 563 of 960 Interrupt and Transmit Data Settings: When mailbox initialization is finished, CPU interrupt source settings and data settings must be made. Interrupt source settings are made in the mailbox interrupt mask register (MBIMR) and interrupt mask register (IMR), while transmit data settings are made by writing the necessary data in 2, 3, and 4 below to the message control registers (MCx[1] to MCx[8]) and message data registers (MDx[1] to MDx[8]). 1. CPU interrupt source settings Transmission acknowledge and transmission abort acknowledge interrupts can be masked for individual mailboxes in the mailbox interrupt mask register (MBIMR). Interrupt register (IRR) interrupts can be masked in the interrupt mask register (IMR). 2. Arbitration field In the arbitration field, the 11-bit identifier (STD_ID0 to STD_ID10) and RTR bit (standard format) or 29-bit identifier (STD_ID0 to STD_ID10, EXT_ID0 to EXT_ID17) and IDE.RTR bit (extended format) are set. The registers to be set are MCx[5] to MCx[8]. 3. Control field In the control field, the byte length of the data to be transmitted is set in DLC0 to DLC3. The register to be set is MCx[1]. 4. Data field In the data field, the data to be transmitted is set in byte units in the range of 0 to 8 bytes. The registers to be set are MDx[1] to MDx[8]. The number of bytes in the data actually transmitted depends on the data length code (DLC) in the control field. If a value exceeding the value set in DLC is set in the data field, only the number of bytes set in DLC will actually be transmitted. Message Transmission and Interrupts 1. Message transmission wait If message transmission is to be performed after completion of the message control (MCx[1] to MCx[8]) and message data (MDx[1] to MDx[8]).settings, transmission is started by setting the corresponding mailbox transmit wait bit (TXPR1 to TXPR15) to 1 in the transmit wait register (TXPR). The following two transmission methods can be used: a. Transmission order determined by message identifier priority b. Transmission order determined by mailbox number priority When the message identifier priority method is selected, if a number of messages are designated as waiting for transmission (TXPR = 1), the message with the highest priority set in the message identifier (MCx[5] to MCx[8]) is stored in the transmit buffer. CAN bus arbitration is then carried out for the message in the transmit buffer, and message transmission is performed when the transmission right is acquired. When the TXPR bit is set, internal arbitration is performed again, the highest-priority message is found and stored in the transmit buffer, CAN bus arbitration is carried out in the same way, and message transmission is performed when the transmission right is acquired. Rev.2.0, 07/03, page 564 of 960 When the mailbox number priority method is selected, if a number of messages are designated as waiting for transmission (TXPR = 1), messages are stored in the transmit buffer in low-tohigh mailbox order (priority order: mailbox 1 > mailbox 15). CAN bus arbitration is then carried out for the messages in the transmit buffer, and message transmission is performed when the bus is acquired. 2. Message transmission completion and interrupt When a message is transmitted normally using the above procedure, the corresponding acknowledge bit (TXACK1 to TXACK15) in the transmit acknowledge register (TXACK) and transmit wait bit (TXPR1 to TXPR15) in the transmit wait register (TXPR) are automatically initialized. If the corresponding bit (MBIMR1 to MBIMR15) in the mailbox interrupt mask register (MBIMR) and the mailbox empty interrupt bit (IRR8) in the interrupt mask register (IMR) are set to the interrupt enable value at this time, an interrupt can be sent to the CPU. 3. Message transmission cancellation Transmission cancellation can be specified for a message stored in a mailbox as a transmit wait message. A transmit wait message is canceled by setting the bit for the corresponding mailbox (TXCR1 to TXCR15) to 1 in the transmit cancel register (TXCR). When cancellation is executed, the transmit wait register (TXPR) is automatically reset, and the corresponding bit is set to 1 in the abort acknowledge register (ABACK). An interrupt to the CPU can be requested. If the corresponding bit (MBIMR1 to MBIMR15) in the mailbox interrupt mask register (MBIMR) and the mailbox empty interrupt bit (IRR8) in the interrupt mask register (IMR) are set to the interrupt enable value at this time, an interrupt can be sent to the CPU. However, a transmit wait message cannot be canceled at the following times: a. During internal arbitration or CAN bus arbitration b. During data frame or remote frame transmission Also, transmission cannot be canceled by clearing the transmit wait register (TXPR). Figure 16.10 shows a flowchart of transmit message cancellation. 4. Message retransmission If transmission of a transmit message is aborted in the following cases, the message is retransmitted automatically: a. CAN bus arbitration failure (failure to acquire the bus) b. Error during transmission (bit error, stuff error, CRC error, frame error, ACK error) Rev.2.0, 07/03, page 565 of 960 Message transmit wait TXPR setting Set TXCR bit corresponding to message to be canceled Cancellation possible? Yes Message not sent Clear TXCR, TXPR ABACK = 1 IRR8 = 1 No Completion of message transmission TXACK = 1 Clear TXCR, TXPR IRR8 = 1 IMR8 = 1? No Interrupt to CPU Yes Clear TXACK Clear ABACK Clear IRR8 : Settings by user End of transmission/transmission cancellation : Processing by hardware Figure 16.10 Transmit Message Cancellation Flowchart Rev.2.0, 07/03, page 566 of 960 16.3.4 Receive Mode Message reception is performed using mailboxes 0 and 1 to 15. The reception procedure is described below, and a reception flowchart is shown in figure 16.11. 1. Initialization (after hardware reset only) a. Clearing of IRR0 bit in interrupt register (IRR) b. HCAN pin port settings c. Bit rate settings d. Mailbox transmit/receive settings e. Mailbox initialization 2. Interrupt and receive message settings a. Interrupt setting b. Arbitration field setting c. Local acceptance filter mask (LAFM) settings 3. Message reception and interrupts a. Message reception CRC check b. Data frame reception c. Remote frame reception d. Unread message reception Initialization (after Hardware Reset Only): These settings should be made while the HCAN is in bit configuration mode. 1. IRR0 clearing The reset interrupt flag (IRR0) is always set after a power-on reset or recovery from software standby mode. As an HCAN interrupt is initiated immediately when interrupts are enabled, IRR0 should be cleared. 2. HCAN pin port settings To prevent erroneous identification of CAN bus data, HCAN pin port settings should be made first. See HCAN Pin Port Settings in section 16.3.2, Initialization after a Hardware Reset, and section 20, Pin Function Controller (PFC), for details. 3. Bit rate settings Set values relating to the CAN bus communication speed and re-synchronization. See Bit Rate Settings in section 16.3.2, Initialization after a Hardware Reset, for details. 4. Mailbox transmit/receive settings Each channel has one receive-only mailbox (mailbox 0) and 15 mailboxes that can be set for reception. Thus a total of 32 mailboxes can be used for reception. To set a mailbox for reception, set the corresponding bit to 1 in the mailbox configuration register (MBCR). The Rev.2.0, 07/03, page 567 of 960 initial setting for mailboxes is 0, designating transmission use. See Mailbox Transmit/Receive Settings in section 16.3.2, Initialization after a Hardware Reset, for details. 5. Mailbox (RAM) initialization As message control/data registers (MCx[x], MDx[x]) are configured in RAM, their initial values after powering on are undefined, and so bit initialization is necessary. Write 0s or 1s to the mailboxes. See Mailbox (Message Control/Data (MCx[x], MDx[x]) Initial Settings in section 16.3.2, Initialization after a Hardware Reset, for details. Rev.2.0, 07/03, page 568 of 960 Initialization IRR0 clearing HCAN port setting BCR setting MBCR setting Mailbox (RAM) initialization : Settings by user : Processing by hardware Interrupt settings Receive data setting Arbitration field setting Local acceptance filter settings Message reception (Match of identifier in mailbox?) Yes No Same RXPR = 1? No Yes Unread message No Data frame? Yes RXPR IRR1 = 1 RXPR, RFPR = 1 IRR2 = 1, IRR1 = 1 IMR1 = 1? No Yes IMR2 = 1? No No Yes RXPR = 1? Interrupt to CPU Yes RXPR = 1? Interrupt to CPU Yes No Message control read Message data read Message control read Message data read Clear RXPR Clear RXPR, RFPR Transmission of data frame corresponding to remote frame End of reception Figure 16.11 Reception Flowchart Rev.2.0, 07/03, page 569 of 960 Interrupt and Receive Message Settings: When mailbox initialization is finished, CPU interrupt source settings and receive message specifications must be made. Interrupt source are set in the mailbox interrupt mask register (MBIMR) and interrupt mask register (IMR). To receive a message, the identifier must be set in advance in the message control (MCx[1] to MCx[8]) for the receiving mailbox. When a message is received, all the bits in the receive message identifier are compared, and if a 100% match is found, the message is stored in the matching mailbox. Mailbox 0 (MC0[x], MD0[x]) has a local acceptance filter mask (LAFM) that allows Don't Care settings to be made. 1. CPU interrupt source settings When transmitting, transmission acknowledge and transmission abort acknowledge interrupts can be masked for individual mailboxes in the mailbox interrupt mask register (MBIMR). When receiving, data frame and remote frame receive wait interrupts can be masked. Interrupt register (IRR) interrupts can be masked in the interrupt mask register (IMR). 2. Arbitration field setting In the arbitration field, the identifier (STD_ID0 to STD_ID10, EXT_ID0 to EXT_ID17) of the message to be received is set. If all the bits in the set identifier do not match, the message is not stored in a mailbox. Example: Mailbox 1 Identifier 1: 010_1010_1010 (standard identifier) 010_1010_1010 Only one kind of message identifier can be received by MB1 3. Local acceptance filter mask (LAFM) setting The local acceptance filter mask is provided for mailbox 0 (MC0[x], MD0[x]) only, enabling a Don't Care specification to be made for all bits in the received identifier. This allows various kinds of messages to be received. Example: Mailbox 0 LAFM Identifier 1: Identifier 2: Identifier 3: Identifier 4: 010_1010_1010 (standard identifier) 000_0000_0011 (0: Care, 1: Don't Care) 010_1010_1000 010_1010_1001 010_1010_1010 010_1010_1011 A total of four kinds of message identifiers can be received by MB0 Rev.2.0, 07/03, page 570 of 960 Message Reception and Interrupts 1. Message reception CRC check When a message is received, a CRC check is performed automatically (by hardware). If the result of the CRC check is normal, ACK is transmitted in the ACK field irrespective of whether or not the message can be received. 2. Data frame reception If the received message is confirmed to be error-free by the CRC check, etc., the identifier in the mailbox (and also LAFM in the case of mailbox 0 only) and the identifier of the receive message are compared, and if a complete match is found, the message is stored in the mailbox. The message identifier comparison is carried out on each mailbox in turn, starting with mailbox 0 and ending with mailbox 15. If a complete match is found, the comparison ends at that point, the message is stored in the matching mailbox, and the corresponding receive complete bit (RXPR0 to RXPR15) is set in the receive complete register (RXPR). However, if the identifier matches when a comparison with the mailbox 0 LAFM is carried out, the mailbox comparison sequence does not end at that point, but continues with mailbox 1 and then the remaining mailboxes. It is therefore possible for a message matching mailbox 0 to be received by another mailbox (however, the same message cannot be stored in more than one of mailboxes 1 to 15). If the corresponding bit (MBIMR0 to MBIMR15) in the mailbox interrupt mask register (MBIMR) and the receive message interrupt mask (IMR1) in the interrupt mask register (IMR) are set to the interrupt enable value at this time, an interrupt can be sent to the CPU. 3. Remote frame reception Two kinds of messages--data frames and remote frames--can be stored in mailboxes. A remote frame differs from a data frame in that the remote reception request bit (RTR) in the message control register (MC[x]5) and the data field are 0 bytes. The data length to be returned in a data frame must be stored in the data length code (DLC) in the control field. When a remote frame (RTR = recessive) is received, the corresponding bit is set in the remote request wait register (RFPR). If the corresponding bit (MBIMR0 to MBIMR15) in the mailbox interrupt mask register (MBIMR) and the remote frame request interrupt mask (IRR2) in the interrupt mask register (IMR) are set to the interrupt enable value at this time, an interrupt can be sent to the CPU. 4. Unread message reception When a received message matches the identifier in a mailbox, the message is stored in the mailbox. If a message overwrite occurs before the CPU reads the message, the corresponding bit (UMSR0 to UMSR15) is set in the unread message register (UMSR). In overwriting of an unread message, when a new message is received before the corresponding bit in the receive complete register (RXPR) has been cleared, the unread message register (UMSR) is set. If the unread interrupt flag (IRR9) in the interrupt mask register (IMR) is set to the interrupt enable value at this time, an interrupt can be sent to the CPU. Figure 16.12 shows a flowchart of unread message overwriting. Rev.2.0, 07/03, page 571 of 960 Unread message overwrite UMSR = 1 IRR9 = 1 IMR9 = 1? No Interrupt to CPU Yes Clear IRR9 Message control/message data read : Settings by user End : Processing by hardware Figure 16.12 Unread Message Overwrite Flowchart Rev.2.0, 07/03, page 572 of 960 16.3.5 HCAN Sleep Mode The HCAN is provided with an HCAN sleep mode that places the HCAN module in the sleep state to reduce current dissipation. Figure 16.13 shows a flowchart of the HCAN sleep mode. MCR5 = 1 Bus idle? Yes Initialize TEC and REC No Bus operation? Yes IRR12 = 1 No IMR12 = 1? Yes No CPU interrupt Sleep mode clearing method MCR7 = 0? Yes (manual) MCR5 = 0 No (automatic) Clear sleep mode? Yes CPU interrupt No 11 recessive bits? Yes CAN bus communication possible No : Settings by user : Processing by hardware Figure 16.13 HCAN Sleep Mode Flowchart Rev.2.0, 07/03, page 573 of 960 HCAN sleep mode is entered by setting the HCAN sleep mode bit (MCR5) to 1 in the master control register (MCR). If the CAN bus is operating, the transition to HCAN sleep mode is delayed until the bus becomes idle. Either of the following methods of clearing HCAN sleep mode can be selected by making a setting in the MCR7 bit. 1. Clearing by software 2. Clearing by CAN bus operation Eleven recessive bits must be received after HCAN sleep mode is cleared before CAN bus communication is enabled again. Clearing by Software: Clearing by software is performed by having the CPU write 0 to MCR5. Clearing by CAN Bus Operation: Clearing by CAN bus operation occurs automatically when the CAN bus performs an operation and this change is detected. In this case, the first message is not received in the message box; normal reception starts with the second message. When a change is detected on the CAN bus in HCAN sleep mode, the bus operation interrupt flag (IRR12) is set in the interrupt register (IRR). If the bus interrupt mask (IMR12) in the interrupt mask register (IMR) is set to the interrupt enable value at this time, an interrupt can be sent to the CPU. Rev.2.0, 07/03, page 574 of 960 16.3.6 HCAN Halt Mode The HCAN halt mode is provided to enable mailbox settings to be changed without performing an HCAN hardware or software reset. Figure 16.14 shows a flowchart of the HCAN halt mode. MCR1 = 1 GSR2 = 1? (Wait until transmission is completed if in progress) Bus idle? Yes MBCR setting No MCR1 = 0 : Settings by user CAN bus communication possible : Processing by hardware Figure 16.14 HCAN Halt Mode Flowchart HCAN halt mode is entered by setting the halt request bit (MCR1) to 1 in the master control register (MCR). If the CAN bus is operating, the transition to HCAN halt mode is delayed until the bus becomes idle. HCAN halt mode is cleared by clearing MCR1 to 0. 16.3.7 Interrupt Interface There are 12 interrupt sources for each HCAN channel. Four independent interrupt vectors are assigned to each channel. Table 16.6 lists the HCAN interrupt sources. With the exception of the power-on reset processing vector (IRR0), these sources can be masked. Masking is implemented using the mailbox interrupt mask register (MBIMR) and interrupt mask register (IMR). Rev.2.0, 07/03, page 575 of 960 Table 16.6 HCAN Interrupt Sources Channel HCAN0 IPR Bits IPRL (11-8) Interrupt priority level 0 to 15 (Initial value: 0) OVR0 221 Vector ERS0 Vector Number IRR Bit 220 IRR5 IRR6 IRR0 IRR2 IRR3 IRR4 IRR7 IRR9 IRR12 RM0 222 IRR1 IRR1 SLE0 HCAN1 IPRL (3-0) Interrupt priority level 0 to 15 (Initial value: 0) OVR1 229 ERS1 223 228 IRR8 IRR5 IRR6 IRR0 IRR2 IRR3 IRR4 IRR7 IRR9 IRR12 RM1 230 IRR1 IRR1 SLE1 231 IRR8 Description Error passive interrupt (TEC 128 or REC 128) Bus off interrupt (TEC 256) Power-on reset processing interrupt Remote frame reception interrupt Error warning interrupt (TEC 96) Error warning interrupt (REC 96) Overload frame transmission interrupt Unread message overwrite interrupt HCAN sleep mode CAN bus operation interrupt Mailbox 0 message reception interrupt Mailbox 1 to 15 message reception interrupt Message transmission/cancellation interrupt Error passive interrupt (TEC 128 or REC 128) Bus off interrupt (TEC 256) Power-on reset processing interrupt Remote frame reception interrupt Error warning interrupt (TEC 96) Error warning interrupt (REC 96) Overload frame transmission interrupt Unread message overwrite interrupt HCAN sleep mode CAN bus operation interrupt Mailbox 0 message reception interrupt Mailbox 1 to 15 message reception interrupt Message transmission/cancellation interrupt 16.3.8 DMAC Interface The DMAC can be activated by reception of a message in HCAN0's mailbox 0. When DMAC transfer ends after DMAC activation has been set, the RXPR0 and RFPR0 flags are acknowledge signal automatically. An interrupt request due to a receive interrupt from the HCAN cannot be sent to the CPU in this case. Figure 16.15 shows a DMAC transfer flowchart. Rev.2.0, 07/03, page 576 of 960 DMAC initialization Activation Source Setting Source/destination address settings Transfer count setting Interrupt setting Message reception in HCAN0's mailbox 0 DMAC activation End of DMAC transfer? Yes DMAC transfer end bit setting RXPR and RFPR clearing No DMAC interrupt enabled? Yes Interrupt to CPU No Clear DMAC interrupt flag : Settings by user End : Processing by hardware Figure 16.15 DMAC Transfer Flowchart Rev.2.0, 07/03, page 577 of 960 16.4 CAN Bus Interface A bus transceiver IC is necessary to connect the SH7055SF chip to a CAN bus. A Philips PCA82C250 transceiver IC, or compatible device, is recommended. Figure 16.16 shows a sample connection diagram. 124 Vcc PCA82C250 RS HRxDx HTxDx N.C. Vcc CAN bus SH7055SF RxD CANH TxD CANL Vref GND 124 Figure 16.16 Example of High-Speed Interface Using PCA82C250 Rev.2.0, 07/03, page 578 of 960 16.5 Usage Notes Reset: The HCAN is reset by a power-on reset, and in hardware standby mode and software standby mode. All the registers are initialized in a reset, but mailboxes (message control (MCx[x])/message data (MDx[x]) are not. However, after powering on, mailboxes (message control (MCx[x])/message data (MDx[x]) are initialized, and their values are undefined. Therefore, mailbox initialization must always be carried out after a power-on reset or a transition to hardware standby mode or software standby mode. The reset interrupt flag (IRR0) is always set after a power-on reset or recovery from software standby mode. As this bit cannot be masked in the interrupt mask register (IMR), if HCAN interrupt enabling is set in the interrupt controller without clearing the flag, an HCAN interrupt will be initiated immediately. IRR0 should therefore be cleared during initialization. HCAN Sleep Mode: The bus operation interrupt flag (IRR12) in the interrupt register (IRR) is set by bus operation in HCAN sleep mode. Therefore, this flag is not used by the HCAN to indicate sleep mode release. Also note that the reset status bit (GSR3) in the general status register (GSR) is set in sleep mode. Port Settings: Port settings must be made with the PFC before the HCAN begins CAN bus communication. When using the two HCAN pins in a 2-channel/32-buffer configuration (wired-AND), set the other two HCAN pin locations as non-HCAN. DMAC Activation: When the DMAC is activated automatically by reception of a message in HCAN0's mailbox 0 (receive-only mailbox), an interrupt request signal is not sent to the INTC. Interrupts: When the mailbox interrupt mask register (MBIMR) is set, the interrupt register (IRR8, 2, 1) is not set by reception completion, transmission completion, or transmission cancellation for the set mailboxes. Error Counters: In the case of error active and error passive, REC and TEC normally count up and down. In the bus off state, 11-bit recessive sequences are counted (REC + 1) using REC. If REC reaches 96 during the count, IRR4 and GSR1 are set, and if REC reaches 128, IRR7 is set. Register Access: Byte or word access can be used on all HCAN registers. Longword access cannot be used. Register Initialization in Standby Modes: All HCAN registers are initialized in hardware standby mode and software standby mode. Differences from the HD64F7005: Rev.2.0, 07/03, page 579 of 960 (a) The operation of the HCAN in the case of the CAN bus short The conventional HD64F7055 does not comply with the CAN specifications if the receive pin (HRxD) is fixed to 1 as a result of faults such as the CAN bus short during message transmission or reception in the HCAN error active state. The HD64F7055S operation always meets the CAN specifications. (1) When the CAN bus is shorted (the CAN bus is fixed to 1) during transmission If the CAN bus is shorted while the HCAN is transmitting messages in the error active state, the conventional HD64F7055 outputs 0s consecutively during the error passive state until the transition to bus off state. In the same case, however, the HD64F7055S outputs 1s consecutively. For details, see figure 16.17. Error active Active error flag Error passive Passive error flag Bus off HTxD HRxD Operations not complying with the CAN specifications HD64F7055 HD64F7055S Message Error warning CAN bus short interrupt (Fixed to 1) (TEC>=96) Error passive interrupt (TEC>=128) Bus off interrupt (TEC>=256) Figure 16.17 HCAN Operation while the CAN Bus is Fixed to 1 during Transmission (2) When the CAN bus is shorted (the CAN bus is fixed to 1) during reception If the CAN bus is shorted while the HCAN is receiving messages in the error active state, the conventional HD64F7055 outputs 0s consecutively during the error passive state. In the same case, however, the HD64F7055S outputs 1s consecutively. For details, see figure 16.18. Rev.2.0, 07/03, page 580 of 960 Error active Active error flag Error passive Passive error flag HTxD HRxD Operations not complying with the CAN specifications Error warning CAN bus short interrupt (Fixed to 1) (TEC>=96) Error passive interrupt (TEC>=128) Message HD64F7055 HD64F7055S Figure 16.18 HCAN Operation while the CAN Bus is Fixed to 1 during Reception (b) The contents of the interrupt register after recovery from the bus off state The conventional HD64F7055 sets the interrupt register (IRR7) at the recovery of the HCAN from bus off state, while the HD64F7055S does not set the interrupt register (IRR7). Rev.2.0, 07/03, page 581 of 960 Rev.2.0, 07/03, page 582 of 960 Section 17 A/D Converter 17.1 Overview The SH7055SF includes a 10-bit successive-approximation A/D converter, with software selection of up to 32 analog input channels. The A/D converter is composed of three independent modules, A/D, A/D1, and A/D2. A/D0 and A/D1 each comprise three groups, while A/D2 comprises two groups. Module A/D0 Analog Groups Analog group 0 Analog group 1 Analog group 2 A/D1 Analog group 3 Analog group 4 Analog group 5 A/D2 Analog group 6 Analog group 7 Channels AN0-AN3 AN4-AN7 AN8-AN11 AN12-AN15 AN16-AN19 AN20-AN23 AN24-AN27 AN28-AN31 17.1.1 Features The features of the A/D converter are summarized below. * 10-bit resolution 32 input channels (A/D0: 12 channels, A/D1: 12 channels, A/D2: 8 channels) * High-speed conversion Conversion time: minimum 13.4 s per channel (when = 40 MHz) * Two conversion modes Single mode: A/D conversion on one channel Scan mode: cotinuous scan mode, single-cycle scan mode (AN0-AN3, AN4-AN7, AN8- AN11, AN12-AN15, AN16-AN19, AN20-AN23, AN24-AN27, AN28-AN31) Continuous conversion on 1 to 12 channels (A/D0) Continuous conversion on 1 to 12 channels (A/D1) Continuous conversion on 1 to 8 channels (A/D2) * Thirty-two 10-bit A/D data registers A/D conversion results are transferred for storage into data registers corresponding to the channels. Rev.2.0, 07/03, page 583 of 960 * Three sample-and-hold circuits A sample-and-hold circuit is built into each A/D converter module (AD/0, AD/1, and AD/2), simplifying the configuration of external analog input circuitry. * A/D conversion interrupts and DMA function supported An A/D conversion interrupt request (ADI) can be sent to the CPU at the end of A/D conversion (ADI0: A/D0 interrupt request; ADI1: A/D1 interrupt request; ADI2: A/D2 interrupt request). Also, the DMAC can be activated by an ADI interrupt request. * Two kinds of conversion activation Software or external trigger (ADTER0, ATU-II (ITVRR2A)) can be selected (A/D0) Software or external trigger (ADTGR0, ATU-II (ITVRR2B)) can be selected (A/D1) Software or external trigger (ADTGR1, ATU-II (ITVRR1)) can be selected (A/D2) * ADEND output Conversion timing can be monitored with the ADEND output pin when using channel 31 in scan mode. 17.1.2 Block Diagram Figure 17.1 shows a block diagram of the A/D converter. Rev.2.0, 07/03, page 584 of 960 A/D0 Bus interface Module data bus Successiveapproximation register Internal data bus ADCSR0 10-bit D/A ADDR0-ADDR11 AVss AN0 AN1 AN2 AN3 AN4 AN5 AN6 AN7 AN8 AN9 AN10 AN11 ATU0 Analog multiplexer Sample-andhold circuit + - Comparator A/D conversion control circuit ADCR0 AVcc AVref ADTRGR0 ADI0 interrupt signal A/D1 Module data bus Successiveapproximation register Bus interface Internal data bus 10-bit D/A ADDR12-ADDR23 AN12 AN13 AN14 AN15 AN16 AN17 AN18 AN19 AN20 AN21 AN22 AN23 ATU0 Analog multiplexer Sample-andhold circuit + - Comparator A/D conversion control circuit ADTRGR1 ADCSR1 ADCR1 ADI1 interrupt signal A/D2 Bus interface Module data bus Successiveapproximation register Internal data bus 10-bit D/A ADDR24- ADDR31 ADTRGR2 ADCSR2 ADCR2 ADEND AN24 AN25 AN26 AN27 AN28 AN29 AN30 AN31 ATU0 Analog multiplexer Sample-andhold circuit + - Comparator A/D conversion control circuit ADI2 interrupt signal ADCR0, ADCR1, ADCR2: A/D control registers 0 to 2 ADCSR0, ADCSR1, ADCSR2: A/D control/status registers 0 to 2 ADDR0 to ADDR31: A/D data registers 0 to 31 ADTRGR0, ADTRGR1, ADTRGR2: A/D trigger registers 0 to 2 Figure 17.1 A/D Converter Block Diagram Rev.2.0, 07/03, page 585 of 960 17.1.3 Pin Configuration Table 17.1 summarizes the A/D converter's input pins. There are 32 analog input pins, AN0 to AN31. The 12 pins AN0 to AN11 are A/D0 analog inputs, divided into three groups: AN0 to AN3 (group 0), AN4 to AN7 (group 1), and AN8 to AN11 (group 2). The 12 pins AN12 to AN23 are A/D1 analog inputs, divided into three groups: AN12 to AN15 (group 3), AN16 to AN19 (group 4), and AN20 to AN23 (group 5). The 8 pins AN24 to AN31 are A/D2 analog inputs, divided into two groups: AN24 to AN27 (group 6), and AN28 to AN31 (group 7). The ADTRG0 and ADTRG1 pins are used to provide A/D conversion start timing from off-chip. When a low level is applied to one of these pins, A/D0, A/D1, or A/D2 starts conversion. The ADEND pin is an output used to monitor conversion timing when channel 31 is used in scan mode. The AVCC and AVSS pins are power supply voltage pins for the analog section in A/D converter modules A/D0 to A/D2. The AVref pin is the A/D converter module A/D0 to A/D2 reference voltage pin. To maintain chip reliability, ensure that AVCC = 5 V 0.5 V and AVSS = VSS during normal operation, and never leave the AVCC and AVSS pins open, even when the A/D converter is not being used. The voltage applied to the analog input pins should be in the range AVSS = ANn = AVref. Rev.2.0, 07/03, page 586 of 960 Table 17.1 A/D Converter Pins Pin Name Analog power supply pin Analog ground pin Analog reference power supply pin Analog input pin 0 Analog input pin 1 Analog input pin 2 Analog input pin 3 Analog input pin 4 Analog input pin 5 Analog input pin 6 Analog input pin 7 Analog input pin 8 Analog input pin 9 Analog input pin 10 Analog input pin 11 Analog input pin 12 Analog input pin 13 Analog input pin 14 Analog input pin 15 Analog input pin 16 Analog input pin 17 Analog input pin 18 Analog input pin 19 Analog input pin 20 Analog input pin 21 Analog input pin 22 Analog input pin 23 Abbreviation AVCC AVSS AVref AN0 AN1 AN2 AN3 AN4 AN5 AN6 AN7 AN8 AN9 AN10 AN11 AN12 AN13 AN14 AN15 AN16 AN17 AN18 AN19 AN20 AN21 AN22 AN23 I/O Input Input Input Input Input Input Input Input Input Input Input Input Input Input Input Input Input Input Input Input Input Input Input Input Input Input Input A/D1 analog inputs 20 to 23 (analog group 5) A/D1 analog inputs 16 to 19 (analog group 4) A/D1 analog inputs 12 to 15 (analog group 3) A/D0 analog inputs 8 to 11 (analog group 2) A/D0 analog inputs 4 to 7 (analog group 1) Function A/D0-A/D2 analog section power supply A/D0-A/D2 analog section ground and referencevoltage A/D0-A/D2 analog section reference voltage A/D0 analog inputs 0 to 3 (analog group 0) Rev.2.0, 07/03, page 587 of 960 Table 17.1 A/D Converter Pins (cont) Pin Name Analog input pin 24 Analog input pin 25 Analog input pin 26 Analog input pin 27 Analog input pin 28 Analog input pin 29 Analog input pin 30 Analog input pin 31 A/D conversion trigger input pin 0 A/D conversion trigger input pin 1 ADEND output pin Abbreviation AN24 AN25 AN26 AN27 AN28 AN29 AN30 AN31 ADTRG0 ADTRG1 ADEND I/O Input Input Input Input Input Input Input Input Input Input A/D0 and A/D1 A/D conversion trigger input A/D2 A/D conversion trigger input A/D2 analog inputs 28 to 31 (analog group 7) Function A/D2 analog inputs 24 to 27 (analog group 6) Output A/D2 channel 31 conversion timing monitor output Rev.2.0, 07/03, page 588 of 960 17.1.4 Register Configuration Table 17.2 summarizes the A/D converter's registers. Table 17.2 A/D Converter Registers Name A/D data register 0 (H/L) A/D data register 1 (H/L) A/D data register 2 (H/L) A/D data register 3 (H/L) A/D data register 4 (H/L) A/D data register 5 (H/L) A/D data register 6 (H/L) A/D data register 7 (H/L) A/D data register 8 (H/L) A/D data register 9 (H/L) A/D data register 10 (H/L) A/D data register 11 (H/L) A/D data register 12 (H/L) A/D data register 13 (H/L) A/D data register 14 (H/L) A/D data register 15 (H/L) A/D data register 16 (H/L) A/D data register 17 (H/L) A/D data register 18 (H/L) A/D data register 19 (H/L) A/D data register 20 (H/L) A/D data register 21 (H/L) A/D data register 22 (H/L) A/D data register 23 (H/L) A/D data register 24 (H/L) A/D data register 25 (H/L) A/D data register 26 (H/L) Abbreviation ADDR0 (H/L) ADDR1 (H/L) ADDR2 (H/L) ADDR3 (H/L) ADDR4 (H/L) ADDR5 (H/L) ADDR6 (H/L) ADDR7 (H/L) ADDR8 (H/L) ADDR9 (H/L) ADDR10 (H/L) ADDR11 (H/L) ADDR12 (H/L) ADDR13 (H/L) ADDR14 (H/L) ADDR15 (H/L) ADDR16 (H/L) ADDR17 (H/L) ADDR18 (H/L) ADDR19 (H/L) ADDR20 (H/L) ADDR21 (H/L) ADDR22 (H/L) ADDR23 (H/L) ADDR24 (H/L) ADDR25 (H/L) ADDR26 (H/L) R/W R R R R R R R R R R R R R R R R R R R R R R R R R R R Initial Value H'0000 H'0000 H'0000 H'0000 H'0000 H'0000 H'0000 H'0000 H'0000 H'0000 H'0000 H'0000 H'0000 H'0000 H'0000 H'0000 H'0000 H'0000 H'0000 H'0000 H'0000 H'0000 H'0000 H'0000 H'0000 H'0000 H'0000 Address H'FFFFF800 H'FFFFF802 H'FFFFF804 H'FFFFF806 H'FFFFF808 H'FFFFF80A H'FFFFF80C H'FFFFF80E H'FFFFF810 H'FFFFF812 H'FFFFF814 H'FFFFF816 H'FFFFF820 H'FFFFF822 H'FFFFF824 H'FFFFF826 H'FFFFF828 H'FFFFF82A H'FFFFF82C H'FFFFF82E H'FFFFF830 H'FFFFF832 H'FFFFF834 H'FFFFF836 H'FFFFF840 H'FFFFF842 H'FFFFF844 Access 1 Size* 8, 16 8, 16 8, 16 8, 16 8, 16 8, 16 8, 16 8, 16 8, 16 8, 16 8, 16 8, 16 8, 16 8, 16 8, 16 8, 16 8, 16 8, 16 8, 16 8, 16 8, 16 8, 16 8, 16 8, 16 8, 16 8, 16 8, 16 Rev.2.0, 07/03, page 589 of 960 Table 17.2 A/D Converter Registers (cont) Name A/D data register 27 (H/L) A/D data register 28 (H/L) A/D data register 29 (H/L) A/D data register 30 (H/L) A/D data register 31 (H/L) A/D control/status register 0 A/D control register 0 A/D trigger register 0 A/D control/status register 1 A/D control register 1 A/D trigger register 1 A/D control/status register 2 A/D control register 2 A/D trigger register 2 Abbreviation ADDR27 (H/L) ADDR28 (H/L) ADDR29 (H/L) ADDR30 (H/L) ADDR31 (H/L) ADCSR0 ADCR0 ADTRGR0 ADCSR1 ADCR1 ADTRGR1 ADCSR2 ADCR2 ADTRGR2 R/W R R R R R R/(W)* R/W R/W R/(W)* R/W R/W R/(W)* R/W R/W 2 2 2 Initial Value H'0000 H'0000 H'0000 H'0000 H'0000 H'00 H'0F H'FF H'00 H'0F H'FF H'08 H'0F H'FF Address H'FFFFF846 H'FFFFF848 H'FFFFF84A H'FFFFF84C H'FFFFF84E H'FFFFF818 H'FFFFF819 H'FFFFF76E H'FFFFF838 H'FFFFF839 H'FFFFF72E H'FFFFF858 H'FFFFF859 H'FFFFF72F Access 1 Size* 8, 16 8, 16 8, 16 8, 16 8, 16 8, 16 8, 16 8 8, 16 8, 16 8 8, 16 8, 16 8 Notes: Register accesses consist of 6 or 7 cycles for byte access and 12 or 13 cycles for word access. *1 A 16-bit access must be made on a word boundary. *2 Only 0 can be written to bit 7 to clear the flag. Rev.2.0, 07/03, page 590 of 960 17.2 17.2.1 Register Descriptions A/D Data Registers 0 to 31 (ADDR0 to ADDR31) A/D data registers 0 to 31 (ADDR0 to ADDR31) are 16-bit read-only registers that store the results of A/D conversion. There are 31 registers, corresponding to analog inputs 0 to 31 (AN0 to AN31). The ADDR registers are initialized to H'0000 by a power-on reset, and in hardware standby mode and software standby mode. Bit: ADDRnH (upper byte) Initial value: R/W: Bit: ADDRnL (lower byte) Initial value: R/W: (n = 0 to 31) 7 AD9 0 R 7 AD1 0 R 6 AD8 0 R 6 AD0 0 R 5 AD7 0 R 5 -- 0 R 4 AD6 0 R 4 -- 0 R 3 AD5 0 R 3 -- 0 R 2 ADR 0 R 2 -- 0 R 1 AD3 0 R 1 -- 0 R 0 AD2 0 R 0 -- 0 R The A/D converter converts analog input to a 10-bit digital value. The upper 8 bits of this data are stored in the upper byte of the ADDR corresponding to the selected channel, and the lower 2 bits in the lower byte of that ADDR. Only the most significant 2 bits of the ADDR lower byte data are valid. Table 17.3 shows correspondence between the analog input channels and A/D data registers. Rev.2.0, 07/03, page 591 of 960 Table 17.3 Analog Input Channels and A/D Data Registers Analog Input Channel AN0 AN1 AN2 AN3 AN4 AN5 AN6 AN7 A/D Data Register ADDR0 ADDR1 ADDR2 ADDR3 ADDR4 ADDR5 ADDR6 ADDR7 Analog Input Channel AN8 AN9 AN10 AN11 AN12 AN13 AN14 AN15 A/D Data Register ADDR8 ADDR9 ADDR10 ADDR11 ADDR12 ADDR13 ADDR14 ADDR15 Analog Input Channel AN16 AN17 AN18 AN19 AN20 AN21 AN22 AN23 A/D Data Register ADDR16 ADDR17 ADDR18 ADDR19 ADDR20 ADDR21 ADDR22 ADDR23 Analog Input Channel AN24 AN25 AN26 AN27 AN28 AN29 AN30 AN31 A/D Data Register ADDR24 ADDR25 ADDR26 ADDR27 ADDR28 ADDR29 ADDR30 ADDR31 17.2.2 A/D Control/Status Registers 0 and 1 (ADCSR0, ADCSR1) A/D control/status registers 0 and 1 (ADCSR0, ADCSR1) are 8-bit readable/writable registers whose functions include selection of the A/D conversion mode for A/D0 and A/D1. ADCSR0 and ADCSR1 are initialized to H'00 by a power-on reset, and in hardware standby mode and software standby mode. Bit: 7 ADF Initial value: R/W: 0 R/(W)* 6 ADIE 0 R/W 5 ADM1 0 R/W 4 ADM0 0 R/W 3 CH3 0 R/W 2 CH2 0 R/W 1 CH1 0 R/W 0 CH0 0 R/W Note: * Only 0 can be written to clear the flag. Rev.2.0, 07/03, page 592 of 960 * Bit 7--A/D End Flag (ADF): Indicates the end of A/D conversion. Bit 7: ADF 0 Description Indicates that A/D0 or A/D1 is performing A/D conversion, or is in the idle state (Initial value) [Clearing conditions] * * 1 When ADF is read while set to 1, then 0 is written to ADF When the DMAC is activated by ADI0 or ADI1 Indicates that A/D0 or A/D1 has finished A/D conversion, and the digital value has been transferred to ADDR [Setting conditions] * * Single mode: When A/D conversion ends Scan mode: When all set A/D conversions end The operation of the A/D converter after ADF is set to 1 differs between single mode and scan mode. In single mode, after the A/D converter transfers the digit value to ADDR, ADF is set to 1 and the A/D converter enters the idle state. In scan mode, ADF is set to 1 after all the set conversions end. For example, in the case of 12-channel scanning, ADF is set to 1 immediately after the end of conversion for AN8 to AN11 (group 2) or AN20 to AN23 (group 5). After ADF is set to 1, conversion continues in the case of continuous scanning, and ends in the case of single-cycle scanning. Note that 1 cannot be written to ADF. * Bit 6--A/D Interrupt Enable (ADIE): Enables or disables the A/D interrupt (ADI). To prevent incorrect operation, ensure that the ADST bit in A/D control registers 0 and 1 (ADCR0, ADCR1) is cleared to 0 before switching the operating mode. Bit 6: ADIE 0 1 Description A/D interrupt (ADI0, ADI1) is disabled A/D interrupt (ADI0, ADI1) is enabled (Initial value) When A/D conversion ends and the ADF bit is set to 1, an A/D0 or A/D1 A/D interrupt (ADI0, ADI1) will be generated If the ADIE bit is 1. ADI0 and ADI1 are cleared by clearing ADF or ADIE to 0. Rev.2.0, 07/03, page 593 of 960 * Bits 5 and 4: A/D Mode 1 and 0 (ADM1, ADM0): These bits select the A/D conversion mode from single mode, 4-channel scan mode, 8-channel scan mode, and 12-channel scan mode. To prevent incorrect operation, ensure that the ADST bit in A/D control registers 1 and 0 (ADCR1, ADCR0) is cleared to 0 before switching the operating mode. Bit 5: ADM1 0 Bit 4: ADM0 0 1 1 0 1 Description Single mode 4-channel scan mode (analog groups 0, 1, 2, 3, 4, 5) 8-channel scan mode (analog groups 0, 1, 3, 4) 12-channel scan mode (analog groups 0, 1, 2, 3, 4, 5) (Initial value) When ADM1 and ADM0 are set to 00, single mode is set. In single mode, operation ends after A/D conversion has been performed once on the analog channels selected with bits CH3 to CH0 in ADCSR. When ADM1 and ADM0 are set to 01, 4-channel scan mode is set. In scan mode, A/D conversion is performed continuously on a number of channels. The channels on which A/D conversion is to be performed in scan mode are set with bits CH3 to CH0 in ADCSR1 and ADCSR0. In 4-channel scan mode, conversion is performed continuously on the channels in one of analog groups 0 (AN0 to AN3), 1 (AN4 to AN7), 2 (AN8 to AN11), 3 (AN12 to AN15, 4 (AN16 to AN19), or 5 (AN20 to AN23). When the ADCS bit is cleared to 0, selecting scanning of all channels within the group (AN0 to AN3, AN4 to AN7, AN8 to AN11, or AN12 to AN15, AN16 to AN19, AN20 to AN23), conversion is performed continuously, once only for each channel within the group, and operation stops on completion of conversion for the last (highest-numbered) channel. When ADM1 and ADM0 are set to 10, 8-channel scan mode is set. In 8-channel scan mode, conversion is performed continuously on the 8 channels in analog groups 0 (AN0 to AN3) and 1 (AN4 to AN7) or analog groups 3 (AN12 to AN15) and 4 (AN16 to AN19). When the ADCS bit is cleared to 0, selecting scanning of all channels within the groups (AN0 to AN7 or AN12 to AN19), conversion is performed continuously, once only for each channel within the groups, and operation stops on completion of conversion for the last (highest-numbered) channel. When ADM1 and ADM0 are set to 11, 12-channel scan mode is set. In 12-channel scan mode, conversion is performed continuously on the 12 channels in analog groups 0 (AN0 to AN3), 1 (AN4 to AN7), and 2 (AN8 to AN11) or analog groups 3 (AN12 to AN15), 4 (AN16 to AN19), and 5 (AN20 to AN23). When the ADCS bit is cleared to 0, selecting scanning of all channels within the groups (AN0 to AN11 or AN12 to AN19), conversion is performed continuously, once only for each channel within the groups, and operation stops on completion of conversion for the last (highest-numbered) channel. For details of the operation in single mode and scan mode, see section 17.4, Operation. Rev.2.0, 07/03, page 594 of 960 * Bits 3 to 0--Channel Select 3 to 0 (CH3 to CH0): These bits, together with the ADM1 and ADM0 bits, select the analog input channels. To prevent incorrect operation, ensure that the ADST bit in A/D control registers 1 and 0 (ADCR1, ADCR0) is cleared to 0 before changing the analog input channel selection. Analog Input Channels Bit 3: CH3 0 Bit 2: CH2 0 Bit 1: CH1 0 Bit 0: CH0 0 1 1 0 1 1 0 0 1 1 0 1 1 0* 0 0 1 1 0 1 Note: * Must be cleared to 0. Single Mode A/D0 A/D1 4-Channel Scan Mode A/D0 AN0 AN0, AN1 AN0-AN2 AN0-AN3 AN4 AN4, AN5 AN4-AN6 AN4-AN7 AN8 AN8, AN9 AN8-AN10 AN8-AN11 A/D1 AN12 AN12, AN13 AN12-AN14 AN12-AN15 AN16 AN16, AN17 AN16-AN18 AN16-AN19 AN20 AN20, AN21 AN20-AN22 AN20-AN23 AN0 AN12 (Initial value) (Initial value) AN1 AN2 AN3 AN4 AN5 AN6 AN7 AN8 AN9 AN10 AN11 AN13 AN14 AN15 AN16 AN17 AN18 AN19 AN20 AN21 AN22 AN23 Rev.2.0, 07/03, page 595 of 960 Analog Input Channels 8-Channel Scan Mode Bit 3: Bit 2: Bit 1: Bit 0: CH3 CH2 CH1 CH0 A/D0 A/D1 0 0 0 0 1 1 0 AN0, AN4 AN0, AN1, AN4, AN5 AN0-AN2, AN4-AN6 AN0-AN7 AN0, AN4 AN0, AN1, AN4, AN5 AN0-AN2, AN4-AN6 AN0-AN7 Reserved* 2 12-Channel Scan Mode A/D0 AN0, AN4, AN8 AN0, AN1, AN4, AN5, AN8, AN9 AN0-AN2, AN4-AN6, AN8-AN10 AN0-AN11 AN0, AN4, AN8 AN0, AN1, AN4, AN5, AN8, AN9 AN0-AN2, AN4-AN6, AN8-AN10 AN0-AN11 AN0, AN4, AN8 AN0, AN1, AN4, AN5, AN8, AN9 AN0-AN2, AN4-AN6, AN8-AN10 AN0-AN11 A/D1 ANAN12, AN16, AN20 AN12, AN13, AN16, AN17, AN20, AN21 AN12-AN14, AN16-AN18, AN20-AN22 AN12-AN23 AN12, AN16, AN20 AN12, AN13, AN16, AN17, AN20, AN21 AN12-AN14, AN16-AN18, AN20-AN22 AN12-AN23 AN12, AN16, AN20 AN12, AN13, AN16, AN17, AN20, AN21 AN12-AN14, AN16-AN18, AN20-AN22 AN12-AN23 AN12, AN16 AN12, AN13, AN16, AN17 AN12-AN14, AN16-AN18 AN12-AN19 AN12, AN16 AN12, AN13, AN16, AN17 AN12-AN14, AN16-AN18 AN12-AN19 Reserved* 2 1 1 0 0 1 1 0 1 1 0* 1 0 0 1 1 0 1 Notes: *1 Must be cleared to 0. *2 These modes are provided for future expansion, and cannot be used at present. Rev.2.0, 07/03, page 596 of 960 17.2.3 A/D Control Registers 0 to 2 (ADCR0 to ADCR2) A/D control registers 0 to 2 (ADCR0 to ADCR2) are 8-bit readable/writable registers that control the start of A/D conversion and selects the operating clock for A/D0 to A/D2. ADCR0 to ADCR2 are initialized to H'0F by a power-on reset, and in hardware standby mode and software standby mode. Bits 3 to 0 of ADCR0 to ADCR2 are reserved. These bits cannot be modified. These bits are always read as 1. Bit: 7 TRGE Initial value: R/W: 0 R/W 6 CKS 0 R/W 5 ADST 0 R/W 4 ADCS 0 R/W 3 -- 1 R 2 -- 1 R 1 -- 1 R 0 -- 1 R * Bit 7--Trigger Enable (TRGE): Enables or disables triggering of A/D conversion by external input or the ATU-II. Bit 7: TRGE 0 1 Description A/D conversion triggering by external input or ATU-II is disabled A/D conversion triggering by external input or ATU-II is enabled (Initial value) For details of external or ATU-II trigger selection, see section 17.2.5, A/D Trigger Registers 0 to 2 (ADTRGR0 to ADTRGR2). When ATU triggering is selected, clear bit 7 of registers ADTRGR0 to ADTRGR2 to 0. When external triggering is selected, upon input of a low level to the ADTRG0 or ADTRG1 pin after TRGE has been set to 1, the A/D converter detects the low level and sets the ADST bit to 1 in ADCR. The same operation is subsequently performed when 1 is written in the ADST bit by software. External triggering of A/D conversion is only enabled when the ADST bit is cleared to 0. When external triggering is used, the low level input to the ADTRG0 or ADTRG1 pin must be at least 1.5 P clock cycles in width. For details, see section 17.4.4, External Triggering of A/D Conversion. Rev.2.0, 07/03, page 597 of 960 * Bit 6--Clock Select (CKS): Selects the A/D conversion time. A/D conversion is executed in a maximum of 532 states when CKS is 0, and a maximum of 268 states when 1. To prevent incorrect operation, ensure that the ADST bit A/D control registers 0 to 2 (ADCR0 to ADCR2) is cleared to 0 before changing the A/D conversion time. For details, see section 17.4.3, Analog Input Sampling and A/D Conversion Time. Bit 6: CKS 0 1 Description Conversion time = 532 states (maximum) Conversion time = 268 states (maximum) (Initial value) * Bit 5--A/D Start (ADST): Starts or stops A/D conversion. A/D conversion is started when ADST is set to 1, and stopped when ADST is cleared to 0. Bit 5: ADST 0 1 Description A/D conversion is stopped A/D conversion is being executed [Clearing conditions] * * Single mode: Automatically cleared to 0 when A/D conversion ends Scan mode: Automatically cleared to 0 on completion of one round of conversion on all set channels (single-cycle scan) (Initial value) Note that the operation of the ADST bit differs between single mode and scan mode. In single mode, ADST is automatically cleared to 0 when A/D conversion ends on one channel. In scan mode (continuous scan), when all conversions have ended for the selected analog inputs, ADST remains set to 1 in order to start A/D conversion again for all the channels. Therefore, in scan mode (continuous scan), the ADST bit must be cleared to 0, stopping A/D conversion, before changing the conversion time or the analog input channel selection. However, in scan mode (single-cycle scan), the ADST bit is automatically cleared to 0, stopping A/D conversion, when one round of conversion ends on all the set channels. Ensure that the ADST bit in ADCR0 to ADCR2 is cleared to 0 before switching the operating mode. Also, make sure that A/D conversion is stopped (ADST is cleared to 0) before changing A/D interrupt enabling (bit ADIE in ADCSR0 to ADCSR2), the A/D conversion time (bit CKS in ADCR0 to ADCR2), the operating mode (bits ADM1 and ADM0 in ADSCR0 to ADCSR2), or the analog input channel selection (bits CH3 to CH0 in ADCSR0 to ADCSR2). The A/D data register contents will not be guaranteed if these changes are made while the A/D converter is operating (ADST is set to 1). Rev.2.0, 07/03, page 598 of 960 * Bit 4--A/D Continuous Scan (ADCS): Selects either single-cycle scan or continuous scan in scan mode. This bit is valid only when scan mode is selected. See section 17.4.2, Scan Mode, for details. Bit 4: ADCS 0 1 Description Single-cycle scan Continuous scan (Initial value) * Bits 3 to 0--Reserved: These bits are always read as 1. The write value should always be 1. 17.2.4 A/D Control/Status Register 2 (ADCSR2) A/D control/status register 2 (ADCSR2) is an 8-bit readable/writable register whose functions include selection of the A/D conversion mode for A/D2. ADCSR2 is initialized to H'08 by a power-on reset, and in hardware standby mode and software standby mode. Bit: 7 ADF Initial value: R/W: 0 R/(W)* 6 ADIE 0 R/W 5 ADM1 0 R/W 4 ADM0 0 R/W 3 -- 1 R 2 CH2 0 R/W 1 CH1 0 R/W 0 CH0 0 R/W Note: * Only 0 can be written to clear the flag. * Bit 7--A/D End Flag (ADF): Indicates the end of A/D conversion. Bit 7: ADF 0 Description Indicates that A/D2 is performing A/D conversion, or is in the idle state (Initial value) [Clearing conditions] * * 1 When ADF is read while set to 1, then 0 is written to ADF When the DMAC is activated by ADI2 Indicates that A/D2 has finished A/D conversion, and the digital value has been transferred to ADDR [Setting conditions] * * Single mode: When A/D conversion ends Scan mode: When all set A/D conversions end The operation of the A/D converter after ADF is set to 1 differs between single mode and scan mode. Rev.2.0, 07/03, page 599 of 960 In single mode, after the A/D converter transfers the digit value to ADDR, ADF is set to 1 and the A/D converter enters the idle state. In scan mode, ADF is set to 1 after all the set conversions end. For example, in the case of 8-channel scanning, ADF is set to 1 immediately after the end of conversion for AN28 to AN31 (group 7). After ADF is set to 1, conversion continues in the case of continuous scanning, and ends in the case of single-cycle scanning. Note that 1 cannot be written to ADF. * Bit 6--A/D Interrupt Enable (ADIE): Enables or disables the A/D interrupt (ADI). To prevent incorrect operation, ensure that the ADST bit in A/D control register 2 (ADCR2) is cleared to 0 before switching the operating mode. Bit 6: ADIE 0 1 Description A/D interrupt (ADI2) is disabled A/D interrupt (ADI2) is enabled (Initial value) When A/D conversion ends and the ADF bit in ADCSR2 is set to 1, an A/D2 A/D interrupt (ADI2) will be generated If the ADIE bit is 1. ADI2 is cleared by clearing ADF or ADIE to 0. * Bits 5 and 4: A/D Mode 1 and 0 (ADM1, ADM0): These bits select the A/D conversion mode from single mode, 4-channel scan mode,and 8-channel scan mode. To prevent incorrect operation, ensure that the ADST bit in A/D control register 2 (ADCR2) is cleared to 0 before switching the operating mode. Bit 5: ADM1 0 Bit 4: ADM0 0 1 1 0 1 Description Single mode 4-channel scan mode (analog groups 6 and 7) 8-channel scan mode (analog groups 6 and 7) Reserved (Initial value) When ADM1 and ADM0 are set to 00, single mode is set. In single mode, operation ends after A/D conversion has been performed once on the analog channels selected with bits CH2 to CH0 in ADCSR. When ADM1 and ADM0 are set to 01, 4-channel scan mode is set. In scan mode, A/D conversion is performed continuously on a number of channels. The channels on which A/D conversion is to be performed in scan mode are set with bits CH2 to CH0 in ADCSR2. In 4channel scan mode, conversion is performed continuously on the channels in one of analog groups 6 (AN24 to AN27) or 7 (AN28 to AN31). When the ADCS bit is cleared to 0, selecting scanning of all channels within the group (AN24 to AN27, AN28 to AN31), conversion is performed continuously, once only for each channel within the group, and operation stops on completion of conversion for the last (highestnumbered) channel. Rev.2.0, 07/03, page 600 of 960 When ADM1 and ADM0 are set to 10, 8-channel scan mode is set. In 8-channel scan mode, conversion is performed continuously on the 8 channels in analog groups 6 (AN24 to AN27) and 7 (AN28 to AN31). When the ADCS bit is cleared to 0, selecting scanning of all channels within the groups (AN24 to AN31), conversion is performed continuously, once only for each channel within the groups, and operation stops on completion of conversion for the last (highest-numbered) channel. For details of the operation in single mode and scan mode, see section 17.4, Operation. * Bit 3--Reserved: This bit is always read as 1. The write value should always be 0. * Bits 2 to 0--Channel Select 2 to 0 (CH2 to CH0): These bits, together with the ADM1 and ADM0 bits, select the analog input channels. To prevent incorrect operation, ensure that the ADST bit in A/D control register 2 (ADCR2) is cleared to 0 before changing the analog input channel selection. Analog Input Channels Bit: CH2 0 Bit: CH1 0 Bit: CH0 0 1 1 0 1 1 0 0 1 1 0 1 Single Mode AN24 (Initial value) AN25 AN26 AN27 AN28 AN29 AN30 AN31 4-Channel Scan Mode AN24 AN24, AN25 AN24-AN26 AN24-AN27 AN28 AN28, AN29 AN28-AN30 AN28-AN31 8-Channel Scan Mode AN24, AN28 AN24, AN25, AN28, AN29 AN24-AN26, AN28-AN30 AN24-AN31 AN24, AN28 AN24, AN25, AN28, AN29 AN24-AN26, AN28-AN30 AN24-AN31 Rev.2.0, 07/03, page 601 of 960 17.2.5 A/D Trigger Registers 0 to 2 (ADTRGR0 to ADTRGR2) The A/D trigger registers (ADTRGR0 to ADTRGR2) are 8-bit readable/writable registers that select the A/D0, A/D1, and A/D2 triggers. Either external pin (ADTRG0, ADTRG1) or ATU-II (ATU-II interval timer A/D conversion request) triggering can be selected. ADTRGR0 to ADTRGR2 are initialized to H'FF by a power-on reset, and in hardware standby mode and software standby mode. Bit: 7 EXTRG Initial value: R/W: 1 R/W 6 -- 1 R 5 -- 1 R 4 -- 1 R 3 -- 1 R 2 -- 1 R 1 -- 1 R 0 -- 1 R * Bit 7--Trigger Enable (EXTRG): Selects external pin input (ADTRG0, ADTRG1) or the ATU-II interval timer A/D conversion request. Bit 7: EXTRG 0 1 Description A/D conversion is triggered by the ATU-II channel 0 interval timer A/D conversion request A/D conversion is triggered by external pin input (ADTRG) (Initial value) In order to select external triggering or ATU-II triggering, the TGRE bit in ADCR0 to ADCR2 must be set to 1. For details, see section 17.2.3, A/D Control Registers 0 to 2 (ADCR0 to ADCR2). * Bits 6 to 0--Reserved: These bits are always read as 1. The write value should always be 1. Rev.2.0, 07/03, page 602 of 960 17.3 CPU Interface A/D data registers 0 to 31 (ADDR0 to ADDR31) are 16-bit registers, but they are connected to the CPU by an 8-bit data bus. Therefore, the upper and lower bytes must be read separately. To prevent the data being changed between the reads of the upper and lower bytes of an A/D data register, the lower byte is read via a temporary register (TEMP). The upper byte can be read directly. Data is read from an A/D data register as follows. When the upper byte is read, the upper-byte value is transferred directly to the CPU and the lower-byte value is transferred into TEMP. Next, when the lower byte is read, the TEMP contents are transferred to the CPU. When performing byte-size reads on an A/D data register, always read the upper byte before the lower byte. It is possible to read only the upper byte, but if only the lower byte is read, incorrect data may be obtained. If a word-size read is performed on an A/D data register, reading is performed in upper byte, lower byte order automatically. Figure 17.2 shows the data flow for access to an A/D data register. Upper-byte read CPU (H'AA) Bus interface Module data bus TEMP (H'40) ADDRnH (H'AA) Lower-byte read CPU (H'40) Bus interface Module data bus ADDRnL (H'40) TEMP (H'40) ADDRnH (H'AA) ADDRnL (H'40) Figure 17.2 A/D Data Register Access Operation (Reading H'AA40) Rev.2.0, 07/03, page 603 of 960 17.4 Operation The A/D converter operates by successive approximations with 10-bit resolution. It has two operating modes: single mode and scan mode. There are two kinds of scan mode: continuous and single-cycle. In single mode, conversion is performed once on one specified channel, then ends. In continuous scan mode, A/D conversion continues on one or more specified channels until the ADST bit is cleared to 0. In single-cycle scan mode, A/D conversion ends after being performed once on one or more channels. 17.4.1 Single Mode Single mode, should be selected when only one A/D conversion on one channel is required. Single mode is selected by setting the ADM1 and ADM0 bits in the A/D control/status register (ADSCR) to 00. When the ADST bit in the A/D control register (ADCR) is set to 1, A/D conversion is started in single mode. The ADST bit remains set to 1 during A/D conversion, and is automatically cleared to 0 when conversion ends. When conversion ends, the ADF flag in ADCSR is set to 1. If the ADIE bit in ADCSR is also 1, an ADI interrupt is requested. To clear the ADF flag, first read ADF when set to 1, then write 0 to ADF. If the DMAC is activated by the ADI interrupt, ADF is cleared automatically. An example of the operation when analog input channel 1 (AN1) is selected and A/D conversion is performed in single mode is described next. Figure 17.3 shows a timing diagram for this example. 1. Single mode is selected (ADM1 = ADM0 = 0), input channel AN1 is selected (CH3 = CH2 = CH1 = 0, CH0 = 1), the A/D interrupt is enabled (ADIE = 1), and A/D conversion is started (ADST = 1). 2. When A/D conversion is completed, the result is transferred to ADDR1. At the same time the ADF flag is set to 1, the ADST bit is cleared to 0, and the A/D converter becomes idle. 3. Since ADF = 1 and ADIE = 1, an ADI interrupt is requested. 4. The A/D interrupt handling routine is started. 5. The routine reads ADF set to 1, then writes 0 to ADF. 6. The routine reads and processes the conversion result (ADDR1). 7. Execution of the A/D interrupt handling routine ends. After this, if the ADST bit is set to 1, A/D conversion starts again and steps 2 to 7 are repeated. Rev.2.0, 07/03, page 604 of 960 Set* ADIE A/D conver- Set* sion starts ADST Clear* ADF Clear* Set* State of channel 0 (AN0) State of channel 1 (AN1) State of channel 2 (AN2) State of channel 3 (AN3) Idle Idle A/D conversion (1) Idle A/D conversion (2) Idle Idle Idle ADDR0 Read conversion result ADDR1 A/D conversion result (1) Read conversion result A/D conversion result (2) ADDR2 ADDR3 Note: * Vertical arrows ( ) indicate instructions executed by software. Figure 17.3 Example of A/D Converter Operation (Single Mode, Channel 1 Selected) Rev.2.0, 07/03, page 605 of 960 17.4.2 Scan Mode Scan mode is useful for monitoring analog inputs in a group of one or more channels. Scan mode is selected for A/D0 or A/D1 by setting the ADM1 and ADM0 bits in A/D control/status register 0 or 1 (ADSCR0 or ADSCR1) to 01 (4-channel scan mode), 10 (8-channel scan mode), or 11 (12channel scan mode). For A/D2, scan mode is selected by setting the ADM1 and ADM0 bits in A/D control/status register 2 (ADCSR2) to 01 (4-channel scan mode) or 10 (8-channel scan mode). When the ADCS bit is cleared to 0 and the ADST bit is set to 1 in the A/D control register (ADCR), single-cycle scanning is performed. When the ADCS bit is set to 1 and the ADST bit is set to 1, continuous scanning is performed. In scan mode, A/D conversion is performed in low-to-high analog input channel number order (AN0, AN1 ... AN11, AN12, AN13 ... AN23, AN24, AN25 ... AN31). In single-cycle scanning, the ADF bit in ADCSR is set to 1 when conversion has been performed once on all the set channels, and the ADST bit is automatically cleared to 0. In continuous scanning, the ADF bit in ADCSR is set to 1 when conversion ends on all the set channels. To stop A/D conversion, write 0 to the ADST bit. If the ADIE bit in ADCSR is set to 1 when ADF is set to 1, an ADI interrupt (ADI0, ADI1, or ADI2) is requested. To clear the ADF flag, first read ADF when set to 1, then write 0 to ADF. If the DMAC is activated by the ADI interrupt, ADF is cleared to 0 automatically. An example of the operation when analog inputs 0 to 11 (AN0 to AN11) are selected and A/D conversion is performed in single-cycle scan mode is described below. Figure 17.4 shows the operation timing for this example. 1. 12-channel scan mode is selected (ADM1 = 1, ADM0 = 1), single-cycle scan mode is selected (ADCS = 0), analog input channels AN0 to AN11 are selected (CH3 = 0, CH2 = 0, CH1 = 1, CH0 = 1), and A/D conversion is started. 2. When conversion of the first channel (AN0) is completed, the result is transferred to ADDR0. Next, conversion of the second channel (AN1) starts automatically. 3. Conversion proceeds in the same way through the 12th channel (AN11). 4. When conversion is completed for all the selected channels (AN0 to AN11), the ADF flag is set to 1, the ADST bit is cleared to 0 automatically, and A/D conversion stops. If the ADIE bit is 1, an ADI interrupt is requested after A/D conversion ends. Rev.2.0, 07/03, page 606 of 960 An example of the operation when analog inputs 0 to 2 and 4 to 6 (AN0 to AN2 and AN4 to AN6) are selected and A/D conversion is performed in 8-channel scan mode is described below. Figure 17.5 shows the operation timing. 1. 8-channel scan mode is selected (ADM1 = 1, ADM0 = 0) continuous scan mode is selected (ADCS = 1), analog input channels AN0 to AN2 and AN4 to AN6 are selected (CH3 = 0, CH2 = 0, CH1 = 1, CH0 = 0), and A/D conversion is started. 2. When conversion of the first channel (AN0) is completed, the result is transferred to ADDR0. Next, conversion of the second channel (AN1) starts automatically. 3. Conversion proceeds in the same way through the third channel (AN2). 4. Conversion of the fourth channel (AN4) starts automatically. 5. Conversion proceeds in the same way through the sixth channel (AN6) 6. When conversion is completed for all the selected channels (AN0 to AN2 and AN4 to AN6), the ADF flag is set to 1. If the ADIE bit is also 1, an ADI interrupt is requested. 7. Steps 2 to 6 are repeated as long as the ADST bit remains set to 1. When the ADST bit is cleared to 0, A/D conversion stops. After this, if the ADST bit is set to 1, A/D conversion starts again from the first channel (AN0). Rev.2.0, 07/03, page 607 of 960 Continuous A/D conversion Set* ADST Clear Clear* ADF State of channel 0 (AN0) State of channel 1 (AN1) State of channel 2 (AN2) Idle A/D conversion (1) Idle A/D conversion (2) Idle A/D conversion (3) Idle Idle Idle State of channel 9 (AN9) State of channel 10 (AN10) State of channel 11 (AN11) Idle A/D conversion (9) A/D conversion (10) A/D conversion (11) Idle Idle Idle Idle Idle ADDR0 A/D conversion result (0) ADDO1 A/D conversion result (1) ADDR2 A/D conversion result (2) ADDR9 A/D conversion result (9) ADDR10 A/D conversion result (10) ADDR11 A/D conversion result (11) Note: * Vertical arrows ( ) indicate instructions executed by software. Figure 17.4 Example of A/D Converter Operation (Scan Mode (Single-Cycle Scan), Channels AN0 to AN11 Selected) Rev.2.0, 07/03, page 608 of 960 Continuous A/D conversion Set*1 ADST Clear*1 Clear*1 ADF State of channel 0 (AN0) State of channel 1 (AN1) State of channel 2 (AN2) State of channel 3 (AN3) State of channel 4 (AN4) State of channel 5 (AN5) State of channel 6 (AN6) State of channel 7 (AN7) ADDR0 Idle A/D conversion (1) A/D conversion (2) Idle A/D conversion (3) Idle A/D conversion (7) Idle A/D conversion (8) Idle Idle Idle Idle A/D conversion (9) Idle Idle Idle A/D conversion (4) A/D conversion (5) A/D conversion (6) Idle A/D conversion (10) Idle Idle *2 Idle Idle A/D conversion (11) Idle Idle Idle A/D conversion result (1) A/D conversion result (7) ADDR1 A/D conversion result (2) A/D conversion result (8) ADDR2 A/D conversion result (3) A/D conversion result (9) ADDR3 ADDR4 A/D conversion result (4) A/D conversion result (10) ADDR5 A/D conversion result (5) ADDR6 A/D conversion result (6) ADDR7 Notes: *1 Vertical arrows ( ) indicate instructions executed by software. *2 Data currently being converted is ignored. Figure 17.5 Example of A/D Converter Operation (Scan Mode (Continuous Scan), Channels AN0 to AN2 and AN4 to AN6 Selected) Rev.2.0, 07/03, page 609 of 960 17.4.3 Analog Input Sampling and A/D Conversion Time The A/D converter has a built-in sample-and-hold circuit in A/D0, A/D1, and A/D2. The A/D converter samples the analog input at time tD (A/D conversion start delay time) after the ADST bit is set to 1, then starts conversion. Figure 17.6 shows the A/D conversion timing. The A/D conversion time (tCONV) includes tD and the analog input sampling time (tSPL). The length of tD is not fixed, since it includes the time required for synchronization of the A/D conversion operation. The total conversion time therefore varies within the ranges shown in table 17.4. In scan mode, the tCONV values given in table 17.4 apply to the first conversion. In the second and subsequent conversions, tCONV is fixed at 512 states when CKS = 0 or 256 states when CKS = 1. Table 17.4 A/D Conversion Time (Single Mode) CKS = 0: = 20 to 40 MHz Item A/D conversion start delay time Input sampling time A/D conversion time Symbol tD tSPL tCONV Min 20 -- 518 Typ -- 128 -- Max 34 -- 532 Min 12 -- 262 CKS = 1: = 20 MHz Typ -- 64 -- Max 18 -- 268 Unit States ( base) Rev.2.0, 07/03, page 610 of 960 A/D conversion time (tCONV) A/D conversion start delay time (tD) Write cycle A/D synchronization time (6 states) (up to 28 states) P Address Internal write signal Analog input sampling signal A/D converter ADF End of A/D conversion Idle Sample-and-hold A/D conversion Analog input sampling time (tSPL) ADST write timing Figure 17.6 A/D Conversion Timing Rev.2.0, 07/03, page 611 of 960 17.4.4 External Triggering of A/D Conversion A/D conversion can be externally triggered. To activate the A/D converter with an external trigger, first set the pin functions with the PFC (pin function controller) and input a high level to the ADTRG pin, then set the TRGE bit to 1 and clear the ADST bit to 0 in the A/D control register (ADCR), and set the EXTRG bit to 1 in the A/D trigger register (ADTRGR). When a low level is input to the ADTRG pin after these settings have been made, the A/D converter detects the low level and sets the ADST bit to 1. If a low level is being input to the ADTRG pin when A/D conversion ends, the ADST bit is set to 1 again, and A/D conversion is started. Figure 17.7 shows the timing for external trigger input. The ADST bit is set to 1 two states after the A/D converter samples the low level on the ADTRG pin. The timing from setting of the ADST bit until the start of A/D conversion is the same as when 1 is written into the ADST bit by software. pin sampled P input ADST bit ADST = 1 Figure 17.7 External Trigger Input Timing Rev.2.0, 07/03, page 612 of 960 17.4.5 A/D Converter Activation by ATU-II The A/D0, A/D1, and A/D2 converter modules can be activated by an A/D conversion request from the ATU-II's channel 0 interval timer. To activate the A/D converter by means of the ATU-II, set the TRGE bit to 1 in the A/D control register (ADCR) and clear the EXTRG bit to 0 in the A/D trigger register (ADTRGR). When an ATU-II channel 0 interval timer A/D conversion request is generated after these settings have been made, the ADST bit set to 1. The timing from setting of the ADST bit until the start of A/D conversion is the same as when 1 is written into the ADST bit by software. 17.4.6 ADEND Output Pin When channel 31 is used in scan mode, the conversion timing can be monitored with the ADEND output pin. After the channel 31 analog voltage has been latched in scan mode, and conversion has started, the ADEND pin goes high. The ADEND pin subsequently goes low when channel 31 conversion ends. ADEND State of channel 28 (AN28) Idle A/D conversion Idle A/D conversion Idle State of channel 29 (AN29) Idle A/D conversion Idle A/D conversion State of channel 30 (AN30) Idle A/D conversion Idle State of channel 31 A/D (AN31) conversion Idle A/D conversion Idle Figure 17.8 ADEND Output Timing Rev.2.0, 07/03, page 613 of 960 17.5 Interrupt Sources and DMA Transfer Requests The A/D converter can generate an A/D conversion end interrupt request (ADI0, ADI1, or ADI2) upon completion of A/D conversions. The ADI interrupt can be enabled by setting the ADIE bit in the A/D control/status register (ADCSR) to 1, or disabled by clearing the ADIE bit to 0. The DMAC can be activated by an ADI interrupt. In this case an interrupt request is not sent to the CPU. When the DMAC is activated by an ADI interrupt, the ADF bit in ADCSR is automatically cleared when data is transferred by the DMAC. See section 10.4.2, Example of DMA Transfer between A/D Converter and On-Chip Memory (Address Reload On), for an example of this operation. 17.6 Usage Notes The following points should be noted when using the A/D converter. 1. Analog input voltage range The voltage applied to analog input pins during A/D conversion should be in the range AVSS ANn AVref. 2. Relation between, AVSS, AVCC, and VSS, VCC When using the A/D converter, set AVCC = 5.0 V 0.5 V, and AVSS = VSS. When the A/D converter is not used, set AVSS = VSS , and do not leave the AVCC pin open. 3. AVref input range Set AVref = 4.5 V to AVCC when the A/D converter is used, and AVref AVCC when not used. If conditions above are not met, the reliability of the device may be adversely affected. 4. Notes on board design In board design, digital circuitry and analog circuitry should be as mutually isolated as possible, and layout in which digital circuit signal lines and analog circuit signal lines cross or are in close proximity should be avoided as far as possible. Failure to do so may result in incorrect operation of the analog circuitry due to inductance, adversely affecting A/D conversion values. Also, digital circuitry must be isolated from the analog input signals (ANn), analog reference voltage (AVref), and analog power supply (AVCC) by the analog ground (AVSS). AVSS should be connected at one point to a stable digital ground (VSS) on the board. 5. Notes on noise countermeasures A protection circuit connected to prevent damage due to an abnormal voltage such as an excessive surge at the analog input pins (ANn) and analog reference voltage (AVref) should be connected between AVCC and AVSS as shown in figure 17.9. Rev.2.0, 07/03, page 614 of 960 Also, the bypass capacitors connected to AVCC and AVref and the filter capacitor connected to ANn must be connected to AVSS. If a filter capacitor is connected as shown in figure 17.9, the input currents at the analog input pins (ANn) are averaged, and so an error may arise. Careful consideration is therefore required when deciding the circuit constants. AVCC AVref Rin*2 *1 *1 100 AN0-NAN31 SH7055SF 0.1 F AVSS Notes: *1 10 F 0.01 F *2 Rin: Input impedance Figure 17.9 Example of Analog Input Pin Protection Circuit Table 17.5 Analog Pin Specifications Item Analog input capacitance Permissible signal source impedance Min -- -- Max 20 3 Unit pF k Rev.2.0, 07/03, page 615 of 960 17.6.1 A/D conversion accuracy definitions A/D conversion accuracy definitions are given below. 1. Resolution The number of A/D converter digital conversion output codes 2. Offset error The deviation of the analog input voltage value from the ideal A/D conversion characteristic when the digital output changes from the minimum voltage value 0000000000 to 0000000001 (does not include quantization error) (see figure 17.10). 3. Full-scale error The deviation of the analog input voltage value from the ideal A/D conversion characteristic when the digital output changes from 1111111110 to 111111111 (does not include quantization error) (see figure 17.10). 4. Quantization error The deviation inherent in the A/D converter, given by 1/2 LSB (see figure 17.10). 5. Nonlinearity error The error with respect to the ideal A/D conversion characteristic between the zero voltage and the full-scale voltage. Does not include the offset error, full-scale error, or quantization error. 6. Absolute accuracy The deviation between the digital value and the analog input value. Includes the offset error, full-scale error, quantization error, and nonlinearity error. Digital output Ideal A/D conversion characteristic Digital output Ideal A/D conversion characteristic Full-scale error 111 110 101 100 011 010 001 000 ; ;;;; ; Nonlinearity error Actual A/D conversion characteristic Quantization error 0 1/8 2/8 3/8 4/8 5/8 6/8 7/8 FS Analog input voltage Offset error FS Analog input voltage Figure 17.10 A/D Conversion Accuracy Definitions Rev.2.0, 07/03, page 616 of 960 Section 18 High-Performance User Debug Interface (H-UDI) 18.1 Overview The high-performance user debug interface (H-UDI) provides data transfer and interrupt request functions. The H-UDI performs serial transfer by means of external signal control. 18.1.1 Features The H-UDI has the following features conforming to the IEEE 1149.1 standard: * Five test signals (TCK, TDI, TDO, TMS, and TRST) * TAP controller * Instruction register * Data register * Bypass register The H-UDI has two instructions: * Bypass mode Test mode conforming to IEEE 1149.1 * H-UDI interrupt H-UDI interrupt request to INTC The SH7055SF does not support test modes other than the bypass mode. Rev.2.0, 07/03, page 617 of 960 18.1.2 Block Diagram Figure 18.1 shows a block diagram of the H-UDI. TCK TMS TAP controller Internal bus controller H-UDI interrupt signal TDI Decoder SDIR SDSR SDBPR SDDRH SDDRL TDO Mux SDIR: SDSR: SDDRH: SDDRL: SDBPR: Instruction register Status register Data register H Data register L Bypass register TCK: TMS: : TDI: TDO: Test clock Test mode select Test reset Test data input Test data output Figure 18.1 H-UDI Block Diagram Rev.2.0, 07/03, page 618 of 960 Peripheral bus Shift register 16 18.1.3 Pin Configuration Table 18.1 shows the H-UDI pin configuration. Table 18.1 H-UDI Pins Name Test clock Test mode select Test data input Test data output Test reset Abbreviation TCK TMS TDI TDO TRST I/O Input Input Input Output Input Function Test clock input Test mode select input signal Serial data input Serial data output Test reset input signal 18.1.4 Register Configuration Table 18.2 shows the H-UDI registers. Table 18.2 H-UDI Registers Register Instruction register Status register Data register H Data register L Bypass register Abbreviation SDIR SDSR SDDRH SDDRL SDBPR R/W* R R/W R/W R/W -- 1 Initial 2 Value* H'F000 H'0201 Undefined Undefined -- Address H'FFFFF7C0 H'FFFFF7C2 H'FFFFF7C4 H'FFFFF7C6 -- Access Size (Bits) 8/16/32 8/16/32 8/16/32 8/16/32 -- Notes: *1 Indicates whether the register can be read and written to by the CPU. *2 Initial value when the TRST signal is input. Not initialized by a reset (power-on or manual) or in software standby mode. Instructions and data can be input to the instruction register (SDIR) and data register (SDDR) by serial transfer from the test data input pin (TDI). Data from SDIR, the status register (SDSR), and SDDR can be output via the test data output pin (TDO). The bypass register (SDBPR) is a one-bit register that is connected to TDI and TDO in bypass mode. Except for SDBPR, all the registers can be accessed by the CPU. Table 18.3 shows the kinds of serial transfer that can be used with each of the H-UDI's registers. Rev.2.0, 07/03, page 619 of 960 Table 18.3 Serial Transfer Characteristics of H-UDI Registers Register SDIR SDSR SDDRH SDDRL SDBPR Serial Input Possible Not possible Possible Possible Possible Serial Output Possible Possible Possible Possible Possible 18.2 18.2.1 External Signals Test Clock (TCK) The test clock pin (TCK) supplies an independent clock to the H-UDI. As the clock input to TCK is supplied directly to the H-UDI, a clock waveform with a duty ratio close to 50% should be input (see section 25, Electrical Characteristics, for details). If no signal is input, TCK is fixed at 1 by internal pull-up. 18.2.2 Test Mode Select (TMS) The test mode select pin (TMS) is sampled at the rise of TCK. TMS controls the internal status of the TAP controller. If no signal is input, TMS is fixed at 1 by internal pull-up. 18.2.3 Test Data Input (TDI) The test data input pin (TDI) performs serial input of instructions and data to H-UDI registers. TDI is sampled at the rise of TCK. If no signal is input, TDI is fixed at 1 by internal pull-up. 18.2.4 Test Data Output (TDO) The test data input pin (TDO) performs serial output of instructions and data from H-UDI registers. Transfer is synchronized with TCK. When no signal is being output, TDO goes to the high-impedance state. 18.2.5 Test Reset (TRST TRST) TRST The test reset pin (TRST) is used to initialize the H-UDI asynchronously. If no signal is input, TRST is fixed at 1 by internal pull-up. Rev.2.0, 07/03, page 620 of 960 18.3 18.3.1 Register Descriptions Instruction Register (SDIR) Bit: 15 TS3 Initial value: R/W: Bit: 1 R 7 -- Initial value: R/W: 0 R 14 TS2 1 R 6 -- 0 R 13 TS1 1 R 5 -- 0 R 12 TS0 1 R 4 -- 0 R 11 -- 0 R 3 -- 0 R 10 -- 0 R 2 -- 0 R 9 -- 0 R 1 -- 0 R 8 -- 0 R 0 -- 0 R The instruction register (SDIR) is a 16-bit register that can be read, but not written to, by the CPU. H-UDI instructions can be transferred to SDIR from TDI by serial input. SDIR can be initialized by the TRST signal, but is not initialized by a reset or in software standby mode. Instructions transferred to SDIR must be 4 bits in length. If an instruction exceeding 4 bits is input, the last 4 bits of the serial data will be stored in SDIR. Rev.2.0, 07/03, page 621 of 960 * Bits 15 to 12--Test Instruction Bits (TS3 to TS0): The instruction configuration is shown in table 18.4. Table 18.4 Instruction Configuration TS3 0 TS2 0 TS1 0 TS0 0 1 1 0 1 1 0 0 1 1 0 1 1 0 0 0 1 1 0 1 1 0 0 1 1 0 1 Instruction Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved H-UDI interrupt Reserved Reserved Reserved Reserved Bypass mode (Initial value) * Bits 11 to 0--Reserved: These bits always read 0. The write value should always be 0. Rev.2.0, 07/03, page 622 of 960 18.3.2 Status Register (SDSR) Bit: 15 -- Initial value: R/W: Bit: 0 R 7 -- Initial value: R/W: 0 R 14 -- 0 R 6 -- 0 R 13 -- 0 R 5 -- 0 R 12 -- 0 R 4 -- 0 R 11 -- 0 R 3 -- 0 R 10 -- 0 R 2 -- 0 R 9 -- 1 R 1 -- 0 R 8 -- 0 R 0 SDTRF 1 R/W The status register (SDSR) is a 16-bit register that can be read and written to by the CPU. The SDSR value can be output from TDO, but serial data cannot be written to SDSR via TDI. The SDTRF bit is output by means of a one-bit shift. In a two-bit shift, the SDTRF bit is output first, followed by a reserved bit. SDSR is initialized by TRST signal input, but is not initialized by a reset or in software standby mode. * Bits 15 to 1--Reserved: Bits 15 to 10 and 8 to 1 always read 0, and the write value should always be 0. Bit 9 always reads 1, and the write value should always be 1. * Bit 0--Serial Data Transfer Control Flag (SDTRF): Indicates whether H-UDI registers can be accessed by the CPU. The SDTRF bit is initialized by the TRST signal, but is not initialized by a reset or in software standby mode. Bit 0: SDTRF 0 1 Description Serial transfer to SDDR has ended, and SDDR can be accessed (Initial value) Serial transfer to SDDR is in progress Rev.2.0, 07/03, page 623 of 960 18.3.3 Data Register (SDDR) The data register (SDDR) comprises data register H (SDDRH) and data register L (SDDRL), each of which has the following configuration. Bit: 15 14 13 12 11 10 9 8 Initial value: R/W: Bit: -- R/W 7 -- R/W 6 -- R/W 5 -- R/W 4 -- R/W 3 -- R/W 2 -- R/W 1 -- R/W 0 Initial value: R/W: -- R/W -- R/W -- R/W -- R/W -- R/W -- R/W -- R/W -- R/W SDDRH and SDDRL are 16-bit registers that can be read and written to by the CPU. SDDR is connected to TDO and TDI for serial data transfer to and from an external device. 32-bit data is input and output in serial data transfer. If data exceeding 32 bits is input, only the last 32 bits will be stored in SDDR. Serial data is input starting with the MSB of SDDR (bit 15 of SDDRH), and output starting with the LSB (bit 0 of SDDRL). SDDR is not initialized by a reset, in hardware or software standby mode, or by the TRST signal. 18.3.4 Bypass Register (SDBPR) The bypass register (SDBPR) is a one-bit shift register. In bypass mode, SDBPR is connected to TDI and TDO, and the SH7055SF chip is bypassed in a board test. SDBPR cannot be read or written to by the CPU. Rev.2.0, 07/03, page 624 of 960 18.4 18.4.1 Operation H-UDI Interrupt When an H-UDI interrupt instruction is transferred to SDIR via TDI, an interrupt is generated. Data transfer can be controlled by means of the H-UDI interrupt service routine. Transfer can be performed by means of SDDR. Control of data input/output between an external device and the H-UDI is performed by monitoring the SDTRF bit in SDSR externally and internally. Internal SDTRF bit monitoring is carried out by having SDSR read by the CPU. The H-UDI interrupt and serial transfer procedure is as follows. 1. An instruction is input to SDIR by serial transfer, and an H-UDI interrupt request is generated. 2. After the H-UDI interrupt request is issued, the SDTRF bit in SDSR is monitored externally. After output of SDTRF = 1 from TDO is observed, serial data is transferred to SDDR. 3. On completion of the serial transfer to SDDR, the SDTRF bit is cleared to 0, and SDDR can be accessed by the CPU. After SDDR has been accessed, SDDR serial transfer is enabled by setting the SDTRF bit to 1 in SDSR. 4. Serial data transfer between an external device and the H-UDI can be carried out by constantly monitoring the SDTRF bit in SDSR externally and internally. Figures 18.2, 18.3, and 18.4 show the timing of data transfer between an external device and the H-UDI. Rev.2.0, 07/03, page 625 of 960 Serial data Instruction SDTRF 1 Input 0 1 Input/ output H-UDI interrupt request Shift disabled SDTRF (in SDSR)*1 SDSR and SDDR MUX*2 SDDR access state Shift enabled SDSR SDDR Shift enabled SDDR SDSR Shift CPU Shift CPU SDSR serial transfer (monitoring) Notes: *1 SDTRF flag (in SDSR): Indicates whether SDDR access by the CPU or serial transfer data input/output to SDDR is possible. 1 0 SDDR is shift-enabled. Do not access SDDR until SDTRF = 0. SDDR is shift-disabled. SDDR access by the CPU is enabled. Conditions: *o SDTRF = 1 -- When =0 -- When the CPU writes 1 -- In bypass mode * SDTRF = 0 -- End of SDDR shift access in serial transfer *2 SDSR/SDDR (Update-DR state) internal MUX switchover timing * Switchover from SDSR to SDDR: On completion of serial transfer in which SDTRF = 1 is output from TDO * Switchover from SDDR to SDSR: On completion of serial transfer to SDDR Figure 18.2 Data Input/Output Timing Chart (1) Rev.2.0, 07/03, page 626 of 960 TDO TDI TMS TCK TDO TCK Select-DR Capture-DR Shift-DR Exit1-DR Update-DR Select-DR Capture-DR Shift-DR Exit1-DR Update-DR Select-DR Capture-DR Shift-DR Exit1-DR Update-DR Select-DR Capture-DR Shift-DR Exit1-DR Update-DR TMS TDI SDTRF Test-Logic-Reset Run-Test/Idle Select-DR Select-IR Capture-IR TS0 Bit 0 Bit 0 Bit 31 Bit 31 Shift-IR TS3 Exit1-IR Update-IR Select-DR SDTRF SDTRF Capture-DR Shift-DR Exit1-DR Update-DR Run-Test/Idle Figure 18.4 Data Input/Output Timing Chart (3) Figure 18.3 Data Input/Output Timing Chart (2) Bit 0 Bit 0 Bit 31 Bit 31 Rev.2.0, 07/03, page 627 of 960 Test-Logic-Reset 18.4.2 Bypass Mode Bypass mode can be used to bypass the SH7055SF chip in a boundary-scan test. Bypass mode is entered by transferring B'1111 to SDIR. In bypass mode, SDBPR is connected to TDI and TDO. 18.4.3 H-UDI Reset The H-UDI can be reset as follows. * By holding the TRST signal at 0 * When TRST = 1, by inputting at least five TCK clock cycles while TMS = 1 * By setting the MSTOP2 bit to 1 in the MSTCR register (see section 24.2.3) * By entering hardware standby mode 18.5 Usage Notes * A reset must always be executed by driving the TRST signal to 0, regardless of whether or not the H-UDI is to be activated. TRST must be held low for 20 TCK clock cycles. For details, see section 26, Electrical Characteristics. * The registers are not initialized in software standby mode. If TRST is set to 0 in software standby mode, the correct operation is not guaranteed. Note that the operation is different from that of SH7055F. * The frequency of TCK must be lower than that of the peripheral module clock (Po). For details, see section 26, Electrical Characteristics. * In data transfer, data input/output starts with the LSB. Figure 18.5 shows serial data input/output. * If the H-UDI serial transfer sequence is disrupted, a TRST reset must be executed. Transfer should then be retried, regardless of the transfer operation. * The TDO output timing is from the rise of TCK. * In the Shift-IR state, the lower 2 bits of the output data from TDO (the IR status word) may not always be 01. * If more than 32 bits are serially transferred, serial data exceeding 32 bits output from TDO should be ignored. Rev.2.0, 07/03, page 628 of 960 TDI SDIR, SDSR, SDDRH/SDDRL 31 30 Shift register Serial data input/output is in LSB-first order. 1 0 TDO Figure 18.5 Serial Data Input/Output Rev.2.0, 07/03, page 629 of 960 Rev.2.0, 07/03, page 630 of 960 Section 19 Advanced User Debugger (AUD) 19.1 Overview The SH7055SF has an on-chip advanced user debugger (AUD). Use of the AUD simplifies the construction of a simple emulator, with functions such as acquisition of branch trace data and monitoring/tuning of on-chip RAM data. 19.1.1 Features The AUD has the following features: * Eight input/output pins Data bus (AUDATA3-AUDATA0) AUD reset (AUDRST) AUD sync signal (AUDSYNC) AUD clock (AUDCK) AUD mode (AUDMD) * Two modes Branch trace mode or RAM monitor mode can be selected by switching AUDMD. Branch trace mode When the PC branches on execution of a branch instruction or generation of an interrupt in the user program , the branch is detected by the AUD and the branch destination address is output from AUDATA. The address is compared with the previously output address, and 4-, 8-, 16-, or 32-bit output is selected automatically according to the upper address matching status. RAM monitor mode When an address is written to AUDATA from off-chip, the data corresponding to that address is output. If an address and data are written to AUDATA, the data is transferred to that address. Rev.2.0, 07/03, page 631 of 960 19.1.2 Block Diagram Figure 19.1 shows a block diagram of the AUD. Internal bus AUDATA0 AUDATA1 AUDATA2 AUDATA3 Data buffer AUDMD AUDCK Mode control On-chip peripheral module Address buffer Bus controller PC output circuit Peripheral module bus On-chip memory CPU Figure 19.1 AUD Block Diagram 19.2 Pin Configuration Table 19.1 shows the AUD's input/output pins. Table 19.1 AUD Pins Function Name AUD data AUD reset AUD mode AUD clock AUD sync signal Abbreviation AUDATA3- AUDATA0 AUDRST AUDMD AUDCK AUDSYNC Branch Trace Mode Branch destination address output AUD reset input Mode select input (L) Serial clock (/2) output Data start position identification signal output RAM Monitor Mode Monitor address/data input/output AUD reset input Mode select input (H) Serial clock input Data start position identification signal input Rev.2.0, 07/03, page 632 of 960 19.2.1 Pin Descriptions Pins Used in Both Modes Pin AUDMD Description The mode is selected by changing the input level at this pin. Low: Branch trace mode High: RAM monitor mode The input at this pin should be changed when AUDRST is low. When no connection is made, this pin is pulled up internally. AUDRST The AUDis internal buffers and logic are initialized by inputting a low level to this pin. When this signal goes low, the AUD enters the reset state and the AUDis internal buffers and logic are reset. When AUDRST goes high again after the AUDMD level settles, the AUD starts operating in the selected mode. When no connection is made, this pin is pulled down internally. Rev.2.0, 07/03, page 633 of 960 Pin Functions in Branch Trace Mode Pin AUDCK AUDSYNC Description This pin outputs 1/2 the operating frequency (/2). This is the clock for AUDATA synchronization. This pin indicates whether output from AUDATA is valid. High: Valid data is not being output Low: An address is being output AUDATA3 to AUDATA0 1. When AUDSYNC is low When a program branch or interrupt branch occurs, the AUD asserts AUDSYNC and outputs the branch destination address. The output order is A3-A0, A7-A4, A11-A8, A15-A12, A19-A16, A23-A20, A27-A24, A31-A28. 2. When AUDSYNC is high When waiting for branch destination address output, these pins constantly output 0011. When an branch occurs, AUDATA3-AUDATA2 output 10, and AUDATA1- AUDATA0 indicate whether a 4-, 8-, 16-, or 32-bit address is to be output by comparing the previous fully output address with the address output this time (see table below). AUDATA1, AUDATA0 00 01 10 Address bits A31-A4 match; 4 address bits A3-A0 are to be output (i.e. output is performed once). Address bits A31-A8 match; 8 address bits A3-A0 and A7-A4 are to be output (i.e. output is performed twice). Address bits A31-A16 match; 16 address bits A3-A0, A7-A4, A11-A8, and A15-A12 are to be output (i.e. output is performed four times). None of the above cases applies; 31 address bits A3-A0, A7- A4, A11-A8, and A15-A12, A19-A16, A23-A20, A27-A24, and A31-A28 are to be output (i.e. output is performed eight times). 11 Rev.2.0, 07/03, page 634 of 960 Pin Functions in RAM Monitor Mode Pin AUDCK Description The external clock input pin. Input the clock to be used for debugging to this pin. The input frequency must not exceed 1/4 the operating frequency. When no connection is made, this pin is pulled up internally. Do not assert this pin until a command is input to AUDATA from off-chip and the necessary data can be prepared. See the protocol description for details. When no connection is made, this pin is pulled up internally. When a command is input from off-chip, data is output after Ready reception. Output starts when AUDSYNC is negated. See the protocol description for details. When no connections are made, these pins are pulled up internally. AUDSYNC AUDATA3 to AUDATA0 19.3 19.3.1 Branch Trace Mode Overview In this mode, the branch destination address is output when a branch occurs in the user program. Branches may be caused by branch instruction execution or interrupt/exception processing, but no distinction is made between the two in this mode. 19.3.2 Operation Operation starts in branch trace mode when AUDRST is asserted, AUDMD is driven low, then AUDRST is negated. Figure 19.2 shows an example of data output. While the user program is being executed without branches, the AUDATA pins constantly output 0011 in synchronization with AUDCK. When a branch occurs, after execution starts at the branch destination address in the PC, the previous fully output address (i.e. for which output was not interrupted by the occurrence of another branch) is compared with the current branch address, and depending on the result, AUDSYNC is asserted and the branch destination address output after 1-clock output of 1000 (in the case of 4-bit output), 1001 (8-bit output), 1010 (16-bit output), or 1011 (32-bit output). The initial value of the compared address is H'00000000. On completion of the cycle in which the address is output, AUDSYNC is negated and 0011 is output from the AUDATA pins. Rev.2.0, 07/03, page 635 of 960 If another branch occurs during branch destination address output, the later branch has priority for output. In this case, AUDSYNC is negated and the AUDATA pins output the address after outputting 10xx again (figure 19.3 shows an example of the output when consecutive branches occur). Note that the compared address is the previous fully output address, and not an interrupted address (since the upper address of an interrupted address will be unknown). The interval from the start of execution at the branch destination address in the PC until the AUDATA pins output 10xx is 1.5 or 2 AUDCK cycles. Start of execution at branch destination address in PC AUDCK AUDATA [3:0] 0011 0011 1011 A3-A0 A7-A4 A11-A8 A15-A12 A19-A16 A23-A20 A27-A24 A31-A28 0011 Figure 19.2 Example of Data Output (32-Bit Output) Start of execution at branch destination address in PC (1) Start of execution at branch destination address in PC (2) AUDCK AUDATA [3:0] 0011 0011 1011 A3-A0 A7-A4 1010 A3-A0 A7-A4 A11-A8 A15-A12 0011 0011 Figure 19.3 Example of Output in Case of Successive Branches Rev.2.0, 07/03, page 636 of 960 19.4 19.4.1 RAM Monitor Mode Overview In this mode, all the modules connected to the SH7055SF's internal or external bus can be read and written to, allowing RAM monitoring and tuning to be carried out. 19.4.2 Communication Protocol The AUD latches the AUDATA input when AUDSYNC is asserted. The following AUDATA input format should be used. Input format 0000 DIR Command A3-A0 . . . . . . A31-A28 D3-D0 Address . . . . . . Dn-Dn-3 Data (in case of write only) B write: n = 7 W write: n = 15 L write: n = 31 Bit 3 Fixed at 1 Bit 2 0: Read 1: Write Bit 1 Bit 0 00: Byte 01: Word 10: Longword Spare bits (4 bits): b'0000 Figure 19.4 AUDATA Input Format Rev.2.0, 07/03, page 637 of 960 19.4.3 Operation Operation starts in RAM monitor mode AUDMD is driven high after AUDRST has been asserted, then AUDRST is negated. Figure 19.5 shows an example of a read operation, and figure 19.6 an example of a write operation. When AUDSYNC is asserted, input from the AUDATA pins begins. When a command, address, or data (writing only) is input in the format shown in figure 19.2, execution of read/write access to the specified address is started. During internal execution, the AUD returns Not Ready (0000). When execution is completed, the Ready flag (0001) is returned (figures 19.5 and 19.6). Table 19.2 shows the Ready flag format. In a read, data of the specified size is output when AUDSYNC is negated following detection of this flag (figure 19.7). If a command other than the above is input in DIR, the AUD treats this as a command error, disables processing, and sets bit 1 in the Ready flag to 1. If a read/write operation initiated by the command specified in DIR causes a bus error, the AUD disables processing and sets bit 2 in the Ready flag to 1 (figure 19.7). Table 19.2 Ready Flag Format Bit 3 Fixed at 0 Bit 2 0: Normal status 1: Bus error Bit 1 0: Normal status 1: Bus error Bit 0 0: Not ready 1: Ready Bus error conditions are shown below. 1. Word access to address 4n+1 or 4n+3 2. Longword access to address 4n+1, 4n+2, or 4n+3 3. Longword access to on-chip I/O 8-bit space 4. Access to external space in single-chip mode AUDCK Input/output switchover AUDATAn 0000 1000 DIR Input A3-A0 A31-A28 0000 Not ready 0001 Ready 0001 0001 D3-D0 D7-D4 Ready Ready Output Figure 19.5 Example of Read Operation (Byte Read) Rev.2.0, 07/03, page 638 of 960 AUDCK Input/output switchover AUDATAn 0000 1110 A3-A0 DIR Input A31-A28 D3-D0 D31-D28 0000 Not ready 0001 Ready Output 0001 0001 Ready Ready Figure 19.6 Example of Write Operation (Longword Write) AUDCK Input/output switchover AUDATAn 0000 1010 A3-A0 DIR Input A31-A28 0000 Not ready 0101 Ready (Bus error) 0101 Ready Output 0101 Ready (Bus error) (Bus error) Figure 19.7 Example of Error Occurrence (Longword Read) 19.5 19.5.1 Usage Notes Initialization The debugger's internal buffers and processing states are initialized in the following cases: 1. In a power-on reset 2. In hardware standby mode 3. When AUDRST is driven low 4. When the AUDSRST bit is set to 1 in the SYSCR register (see section 24.2.2) 5. When the MSTOP3 bit is set to 1 in the MSTCR register (see section 24.2.3) 19.5.2 Operation in Software Standby Mode The debugger is not initialized in software standby mode. However, since the SH7055SF's internal operation halts in software standby mode: 1. When AUDMD is high (RAM monitor mode): Ready is not returned. Since the operation after the software standby mode cancellation is not guaranteed, input AUDRST, and re-execute. However, when operating on an external clock, the protocol continues. 2. When AUDMD is low (PC trace): Operation stops. However, operation continues when software standby is released. Rev.2.0, 07/03, page 639 of 960 19.5.3 Boot Mode Operation and User Boot Mode Initial State The AUD operation cannot be provided in the boot mode operation and user boot mode initial states. For details on the boot mode and user boot mode, see section 22, ROM. 19.5.4 AUD Input Signal in Software Standby/Hardware Standby Mode If the AUD interface input is changed during software standby/hardware standby mode operation, the reliability may be lowered significantly. Be careful not to change the AUD input signal during software standby/hardware standby mode operation. Rev.2.0, 07/03, page 640 of 960 Section 20 Pin Function Controller (PFC) 20.1 Overview The pin function controller (PFC) consists of registers for selecting multiplex pin functions and their input/output direction. Table 20.1 shows the SH7055SF's multiplex pins. Table 20.1 SH7055SF Multiplex Pins Port A A A A A A A A A A A A A A A A B B B B B B B B B B Function 1 (Related Module) PA0 input/output (port) PA1 input/output (port) PA2 input/output (port) PA3 input/output (port) PA4 input/output (port) PA5 input/output (port) PA6 input/output (port) PA7 input/output (port) PA8 input/output (port) PA9 input/output (port) PA10 input/output (port) PA11 input/output (port) PA12 input/output (port) PA13 input/output (port) PA14 input/output (port) PA15 input/output (port) PB0 input/output (port) PB1 input/output (port) PB2 input/output (port) PB3 input/output (port) PB4 input/output (port) PB5 input/output (port) PB6 input/output (port) PB7 input/output (port) PB8 input/output (port) PB9 input/output (port) Function 2 (Related Module) TI0A input (ATU-II) TI0B input (ATU-II) TI0C input (ATU-II) TI0D input (ATU-II) TIO3A input/output (ATU-II) TIO3B input/output (ATU-II) TIO3C input/output (ATU-II) TIO3D input/output (ATU-II) TIO4A input/output (ATU-II) TIO4B input/output (ATU-II) TIO4C input/output (ATU-II) TIO4D input/output (ATU-II) TIO5A input/output (ATU-II) TIO5B input/output (ATU-II) TxD0 output (SCI) RxD0 input (SCI) TO6A output (ATU-II) TO6B output (ATU-II) TO6C output (ATU-II) TO6D output (ATU-II) TO7A output (ATU-II) TO7B output (ATU-II) TO7C output (ATU-II) TO7D output (ATU-II) TxD3 output (SCI) RxD3 input (SCI) TO8A output (ATU-II) TO8B output (ATU-II) TO8C output (ATU-II) TO8D output (ATU-II) TO8E output (ATU-II) TO8F output (ATU-II) Function 3 (Related Module) Function 4 (Related Module) Rev.2.0, 07/03, page 641 of 960 Table 20.1 SH7055SF Multiplex Pins (cont) Port B B B B B B C C C C C D D D D D D D D D D D D D D E E E E E E E E Function 1 (Related Module) PB10 input/output (port) PB11 input/output (port) PB12 input/output (port) PB13 input/output (port) PB14 input/output (port) PB15 input/output (port) PC0 input/output (port) PC1 input/output (port) PC2 input/output (port) PC3 input/output (port) PC4 input/output (port) PD0 input/output (port) PD1 input/output (port) PD2 input/output (port) PD3 input/output (port) PD4 input/output (port) PD5 input/output (port) PD6 input/output (port) PD7 input/output (port) PD8 input/output (port) PD9 input/output (port) PD10 input/output (port) PD11 input/output (port) PD12 input/output (port) PD13 input/output (port) PE0 input/output (port) PE1 input/output (port) PE2 input/output (port) PE3 input/output (port) PE4 input/output (port) PE5 input/output (port) PE6 input/output (port) PE7 input/output (port) Function 2 (Related Module) TxD4 output (SCI) RxD4 input (SCI) TCLKA input (ATU-II) SCK0 input/output (SCI) SCK1 input/output (SCI) PULS5 output (APC) TxD1 output (SCI) RxD1 input (SCI) TxD2 output (SCI) RxD2 input (SCI) IRQ0 input (INTC) TIO1A input/output (ATU-II) TIO1B input/output (ATU-II) TIO1C input/output (ATU-II) TIO1D input/output (ATU-II) TIO1E input/output (ATU-II) TIO1F input/output (ATU-II) TIO1G input/output (ATU-II) TIO1H input/output (ATU-II) PULS0 output (APC) PULS1 output (APC) PULS2 output (APC) PULS3 output (APC) PULS4 output (APC) PULS6 output (APC) A0 output (BSC) A1 output (BSC) A2 output (BSC) A3 output (BSC) A4 output (BSC) A5 output (BSC) A6 output (BSC) A7 output (BSC) HTxD0 output (HCAN) HTxD1 output (HCAN) TCLKB input (ATU-II) SCK2 input/output (SCI) TI10 input (ATU-II) Function 3 (Related Module) HTxD0 output (HCAN) HRxD0 input (HCAN) UBCTRG output (UBC) Function 4 (Related Module) TO8G output (ATU-II) TO8H output (ATU-II) Rev.2.0, 07/03, page 642 of 960 Table 20.1 SH7055SF Multiplex Pins (cont) Port E E E E E E E E F F F F F F F F F F F F F F F F G G G G H H H H H Function 1 (Related Module) PE8 input/output (port) PE9 input/output (port) PE10 input/output (port) PE11 input/output (port) PE12 input/output (port) PE13 input/output (port) PE14 input/output (port) PE15 input/output (port) PF0 input/output (port) PF1 input/output (port) PF2 input/output (port) PF3 input/output (port) PF4 input/output (port) PF5 input/output (port) PF6 input/output (port) PF7 input/output (port) PF8 input/output (port) PF9 input/output (port) PF10 input/output (port) PF11 input/output (port) PF12 input/output (port) PF13 input/output (port) PF14 input/output (port) PF15 input/output (port) PG0 input/output (port) PG1 input/output (port) PG2 input/output (port) PG3 input/output (port) PH0 input/output (port) PH1 input/output (port) PH2 input/output (port) PH3 input/output (port) PH4 input/output (port) Function 2 (Related Module) A8 output (BSC) A9 output (BSC) A10 output (BSC) A11 output (BSC) A12 output (BSC) A13 output (BSC) A14 output (BSC) A15 output (BSC) A16 output (BSC) A17 output (BSC) A18 output (BSC) A19 output (BSC) A20 output (BSC) A21 output (BSC) WRL output (BSC) WRH output (BSC) WAIT input (BSC) RD output (BSC) CS0 output (BSC) CS1 output (BSC) CS2 output (BSC) CS3 output (BSC) BACK output (BSC) BREQ input (BSC) PULS7 output (APC) IRQ1 input (INTC) IRQ2 input (INTC) IRQ3 input (INTC) D0 input/output (BSC) D1 input/output (BSC) D2 input/output (BSC) D3 input/output (BSC) D4 input/output (BSC) ADEND output (A/D) ADTRG0 input (A/D) HRxD0 input (HCAN) HRxD1 input (HCAN) POD input (port) Function 3 (Related Module) Function 4 (Related Module) Rev.2.0, 07/03, page 643 of 960 Table 20.1 SH7055SF Multiplex Pins (cont) Port H H H H H H H H H H H J J J J J J J J J J J J J J J J K K K K K K Function 1 (Related Module) PH5 input/output (port) PH6 input/output (port) PH7 input/output (port) PH8 input/output (port) PH9 input/output (port) PH10 input/output (port) PH11 input/output (port) PH12 input/output (port) PH13 input/output (port) PH14 input/output (port) PH15 input/output (port) PJ0 input/output (port) PJ1 input/output (port) PJ2 input/output (port) PJ3 input/output (port) PJ4 input/output (port) PJ5 input/output (port) PJ6 input/output (port) PJ7 input/output (port) PJ8 input/output (port) PJ9 input/output (port) PJ10 input/output (port) PJ11 input/output (port) PJ12 input/output (port) PJ13 input/output (port) PJ14 input/output (port) PJ15 input/output (port) PK0 input/output (port) PK1 input/output (port) PK2 input/output (port) PK3 input/output (port) PK4 input/output (port) PK5 input/output (port) Function 2 (Related Module) D5 input/output (BSC) D6 input/output (BSC) D7 input/output (BSC) D8 input/output (BSC) D9 input/output (BSC) D10 input/output (BSC) D11 input/output (BSC) D12 input/output (BSC) D13 input/output (BSC) D14 input/output (BSC) D15 input/output (BSC) TIO2A input/output (ATU-II) TIO2B input/output (ATU-II) TIO2C input/output (ATU-II) TIO2D input/output (ATU-II) TIO2E input/output (ATU-II) TIO2F input/output (ATU-II) TIO2G input/output (ATU-II) TIO2H input/output (ATU-II) TIO5C input/output (ATU-II) TIO5D input/output (ATU-II) TI9A input (ATU-II) TI9B input (ATU-II) TI9C input (ATU-II) TI9D input (ATU-II) TI9E input (ATU-II) TI9F input (ATU-II) TO8A output (ATU-II) TO8B output (ATU-II) TO8C output (ATU-II) TO8D output (ATU-II) TO8E output (ATU-II) TO8F output (ATU-II) Function 3 (Related Module) Function 4 (Related Module) Rev.2.0, 07/03, page 644 of 960 Table 20.1 SH7055SF Multiplex Pins (cont) Port K K K K K K K K K K L L L L L L L L L L L L L L Function 1 (Related Module) PK6 input/output (port) PK7 input/output (port) PK8 input/output (port) PK9 input/output (port) PK10 input/output (port) PK11 input/output (port) PK12 input/output (port) PK13 input/output (port) PK14 input/output (port) PK15 input/output (port) PL0 input/output (port) PL1 input/output (port) PL2 input/output (port) PL3 input/output (port) PL4 input/output (port) PL5 input/output (port) PL6 input/output (port) PL7 input/output (port) PL8 input/output (port) PL9 input/output (port) PL10 input/output (port) PL11 input/output (port) PL12 input/output (port) PL13 input/output (port) Function 2 (Related Module) TO8G output (ATU-II) TO8H output (ATU-II) TO8I output (ATU-II) TO8J output (ATU-II) TO8K output (ATU-II) TO8L output (ATU-II) TO8M output (ATU-II) TO8N output (ATU-II) TO8O output (ATU-II) TO8P output (ATU-II) TI10 input (ATU-II) TIO11A input/output (ATU-II) TIO11B input/output (ATU-II) TCLKB input (ATU-II) ADTRG0 input (A/D) ADTRG1 input (A/D) ADEND output (A/D) SCK2 input/output (SCI) SCK3 input/output (SCI) SCK4 input/output (SCI) HTxD0 output (HCAN) HRxD0 input (HCAN) IRQ4 input (INTC) IRQOUT output (INTC) IRQOUT output (INTC) IRQ5 input (INTC) HTxD1 output (HCAN) HRxD1 input (HCAN) HTxD0 & HTxD1 (HCAN) HRxD0 & HRxD1 (HCAN) IRQ6 input (INTC) IRQ7 input (INTC) Function 3 (Related Module) Function 4 (Related Module) Rev.2.0, 07/03, page 645 of 960 20.2 Register Configuration PFC registers are listed in table 20.2. Table 20.2 PFC Registers Name Port A IO register Port A control register H Port A control register L Port B IO register Port B control register H Port B control register L Port B invert register Port C IO register Port C control register Port D IO register Port D control register H Port D control register L Port E IO register Port E control register Port F IO register Port F control register H Port F control register L Port G IO register Port G control register Port H IO register Port H control register Port J IO register Port J control register H Port J control register L Port K IO register Port K control register H Port K control register L Port K invert register Abbreviation PAIOR PACRH PACRL PBIOR PBCRH PBCRL PBIR PCIOR PCCR PDIOR PDCRH PDCRL PEIOR PECR PFIOR PFCRH PFCRL PGIOR PGCR PHIOR PHCR PJIOR PJCRH PJCRL PKIOR PKCRH PKCRL PKIR R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Initial Value H'0000 H'0000 H'0000 H'0000 H'0000 H'0000 H'0000 H'0000 H'0000 H'0000 H'0000 H'0000 H'0000 H'0000 H'0000 H'0015 H'5000 H'0000 H'0000 H'0000 H'0000 H'0000 H'0000 H'0000 H'0000 H'0000 H'0000 H'0000 Address H'FFFFF720 H'FFFFF722 H'FFFFF724 H'FFFFF730 H'FFFFF732 H'FFFFF734 H'FFFFF736 H'FFFFF73A H'FFFFF73C H'FFFFF740 H'FFFFF742 H'FFFFF744 H'FFFFF750 H'FFFFF752 H'FFFFF748 H'FFFFF74A H'FFFFF74C H'FFFFF760 H'FFFFF762 H'FFFFF728 H'FFFFF72A H'FFFFF766 H'FFFFF768 H'FFFFF76A H'FFFFF770 H'FFFFF772 H'FFFFF774 H'FFFFF776 Access Size 8, 16 8, 16 8, 16 8, 16 8, 16 8, 16 8, 16 8, 16 8, 16 8, 16 8, 16 8, 16 8, 16 8, 16 8, 16 8, 16 8, 16 8, 16 8, 16 8, 16 8, 16 8, 16 8, 16 8, 16 8, 16 8, 16 8, 16 8, 16 Rev.2.0, 07/03, page 646 of 960 Table 20.2 PFC Registers (cont) Name Port L IO register Port L control register H Port L control register L Port L invert register Abbreviation PLIOR PLCRH PLCRL PLIR R/W R/W R/W R/W R/W Initial Value H'0000 H'0000 H'0000 H'0000 Address H'FFFFF756 H'FFFFF758 H'FFFFF75A H'FFFFF75C Access Size 8, 16 8, 16 8, 16 8, 16 20.3 20.3.1 Register Descriptions Port A IO Register (PAIOR) Bit: 15 PA15 IOR Initial value: R/W: Bit: 0 R/W 14 PA14 IOR 0 R/W 13 PA13 IOR 0 R/W 12 PA12 IOR 0 R/W 11 PA11 IOR 0 R/W 10 PA10 IOR 0 R/W 9 PA9 IOR 0 R/W 8 PA8 IOR 0 R/W 7 PA7 IOR 6 PA6 IOR 0 R/W 5 PA5 IOR 0 R/W 4 PA4 IOR 0 R/W 3 PA3 IOR 0 R/W 2 PA2 IOR 0 R/W 1 PA1 IOR 0 R/W 0 PA0 IOR 0 R/W Initial value: R/W: 0 R/W The port A IO register (PAIOR) is a 16-bit readable/writable register that selects the input/output direction of the 16 pins in port A. Bits PA15IOR to PA0IOR correspond to pins PA15/RxD0 to PA0/TI0A. PAIOR is enabled when port A pins function as general input/output pins (PA15 to PA0) or ATU-II input/output pins, and disabled otherwise. For bits 3 to 0, when ATU-II input capture input is selected, the PAIOR bits should be cleared to 0. When port A pins function as PA15 to PA0 or ATU-II input/output pins, a pin becomes an output when the corresponding bit in PAIOR is set to 1, and an input when the bit is cleared to 0. PAIOR is initialized to H'0000 by a power-on reset (excluding a WDT power-on reset), and in hardware standby mode. It is not initialized in software standby mode or sleep mode. Rev.2.0, 07/03, page 647 of 960 20.3.2 Port A Control Registers H and L (PACRH, PACRL) Port A control registers H and L (PACRH, PACRL) are 16-bit readable/writable registers that select the functions of the 16 multiplex pins in port A. PACRH selects the functions of the pins for the upper 8 bits of port A, and PACRL selects the functions of the pins for the lower 8 bits. PACRH and PACRL are initialized to H'0000 by a power-on reset (excluding a WDT power-on reset), and in hardware standby mode. They are not initialized in software standby mode or sleep mode. Port A Control Register H (PACRH) Bit: 15 -- Initial value: R/W: Bit: 0 R 7 -- Initial value: R/W: 0 R 14 PA15MD 0 R/W 6 PA11MD 0 R/W 13 -- 0 R 5 -- 0 R 12 PA14MD 0 R/W 4 PA10MD 0 R/W 11 -- 0 R 3 -- 0 R 10 PA13MD 0 R/W 2 PA9MD 0 R/W 9 -- 0 R 1 -- 0 R 8 PA12MD 0 R/W 0 PA8MD 0 R/W * Bit 15--Reserved: This bit is always read as 0. The write value should always be 0. * Bit 14--PA15 Mode Bit (PA15MD): Selects the function of pin PA15/RxD0. Bit 14: PA15MD 0 1 Description General input/output (PA15) Receive data input (RxD0) (Initial value) * Bit 13--Reserved: This bit is always read as 0. The write value should always be 0. * Bit 12--PA14 Mode Bit (PA14MD): Selects the function of pin PA14/TxD0. Bit 12: PA14MD 0 1 Description General input/output (PA14) Transmit data output (TxD0) (Initial value) Rev.2.0, 07/03, page 648 of 960 * Bit 11--Reserved: This bit is always read as 0. The write value should always be 0. * Bit 10--PA13 Mode Bit (PA13MD): Selects the function of pin PA13/TIO5B. Bit 10: PA13MD 0 1 Description General input/output (PA13) ATU-II input capture input/output compare output (TIO5B) (Initial value) * Bit 9--Reserved: This bit is always read as 0. The write value should always be 0. * Bit 8--PA12 Mode Bit (PA12MD): Selects the function of pin PA12/TIO5A. Bit 8: PA12MD 0 1 Description General input/output (PA12) ATU-II input capture input/output compare output (TIO5A) (Initial value) * Bit 7--Reserved: This bit is always read as 0. The write value should always be 0. * Bit 6--PA11 Mode Bit (PA11MD): Selects the function of pin PA11/TIO4D. Bit 6: PA11MD 0 1 Description General input/output (PA11) ATU-II input capture input/output compare output (TIO4D) (Initial value) * Bit 5--Reserved: This bit is always read as 0. The write value should always be 0. * Bit 4--PA10 Mode Bit (PA10MD): Selects the function of pin PA10/TIO4C. Bit 4: PA10MD 0 1 Description General input/output (PA10) ATU-II input capture input/output compare output (TIO4C) (Initial value) * Bit 3--Reserved: This bit is always read as 0. The write value should always be 0. * Bit 2--PA9 Mode Bit (PA9MD): Selects the function of pin PA9/TIO4B. Bit 2: PA9MD 0 1 Description General input/output (PA9) ATU-II input capture input/output compare output (TIO4B) (Initial value) Rev.2.0, 07/03, page 649 of 960 * Bit 1--Reserved: This bit is always read as 0. The write value should always be 0. * Bit 0--PA8 Mode Bit (PA8MD): Selects the function of pin PA8/TIO4A. Bit 0: PA8MD 0 1 Description General input/output (PA8) ATU-II input capture input/output compare output (TIO4A) (Initial value) Port A Control Register L (PACRL) Bit: 15 -- Initial value: R/W: Bit: 0 R 7 -- Initial value: R/W: 0 R 14 PA7MD 0 R/W 6 PA3MD 0 R/W 13 -- 0 R 5 -- 0 R 12 PA6MD 0 R/W 4 PA2MD 0 R/W 11 -- 0 R 3 -- 0 R 10 PA5MD 0 R/W 2 PA1MD 0 R/W 9 -- 0 R 1 -- 0 R 8 PA4MD 0 R/W 0 PA0MD 0 R/W * Bit 15--Reserved: This bit is always read as 0. The write value should always be 0. * Bit 14--PA7 Mode Bit (PA7MD): Selects the function of pin PA7/TIO3D. Bit 14: PA7MD 0 1 Description General input/output (PA7) ATU-II input capture input/output compare output (TIO3D) (Initial value) * Bit 13--Reserved: This bit is always read as 0. The write value should always be 0. * Bit 12--PA6 Mode Bit (PA6MD): Selects the function of pin PA6/TIO3C. Bit 12: PA6MD 0 1 Description General input/output (PA6) ATU-II input capture input/output compare output (TIO3C) (Initial value) Rev.2.0, 07/03, page 650 of 960 * Bit 11--Reserved: This bit is always read as 0. The write value should always be 0. * Bit 10--PA5 Mode Bit (PA5MD): Selects the function of pin PA5/TIO3B. Bit 10: PA5MD 0 1 Description General input/output (PA5) ATU-II input capture input/output compare output (TIO3B) (Initial value) * Bit 9--Reserved: This bit is always read as 0. The write value should always be 0. * Bit 8--PA4 Mode Bit (PA4MD): Selects the function of pin PA4/TIO3A. Bit 8: PA4MD 0 1 Description General input/output (PA4) ATU-II input capture input/output compare output (TIO3A) (Initial value) * Bit 7--Reserved: This bit is always read as 0. The write value should always be 0. If 1 is written to this bit, correct operation cannot be guaranteed. * Bit 6--PA3 Mode Bit (PA3MD): Selects the function of pin PA3/TI0D. Bit 6: PA3MD 0 1 Description General input/output (PA3) ATU-II input capture input (TI0D) (Initial value) * Bit 5--Reserved: This bit is always read as 0. The write value should always be 0. If 1 is written to this bit, correct operation cannot be guaranteed. * Bit 4--PA2 Mode Bit (PA2MD): Selects the function of pin PA2/TI0C. Bit 4: PA2MD 0 1 Description General input/output (PA2) ATU-II input capture input (TI0C) (Initial value) * Bit 3--Reserved: This bit is always read as 0. The write value should always be 0. If 1 is written to this bit, correct operation cannot be guaranteed. * Bit 2--PA1 Mode Bit (PA1MD): Selects the function of pin PA1/TI0B. Bit 2: PA1MD 0 1 Description General input/output (PA1) ATU-II input capture input (TI0B) (Initial value) Rev.2.0, 07/03, page 651 of 960 * Bit 1--Reserved: This bit is always read as 0. The write value should always be 0. If 1 is written to this bit, correct operation cannot be guaranteed. * Bit 0--PA0 Mode Bit (PA0MD): Selects the function of pin PA0/TI0A. Bit 0: PA0MD 0 1 Description General input/output (PA0) ATU-II input capture input (TI0A) (Initial value) 20.3.3 Port B IO Register (PBIOR) Bit: 15 PB15 IOR Initial value: R/W: Bit: 0 R/W 7 PB7 IOR Initial value: R/W: 0 R/W 14 PB14 IOR 0 R/W 6 PB6 IOR 0 R/W 13 PB13 IOR 0 R/W 5 PB5 IOR 0 R/W 12 PB12 IOR 0 R/W 4 PB4 IOR 0 R/W 11 PB11 IOR 0 R/W 3 PB3 IOR 0 R/W 10 PB10 IOR 0 R/W 2 PB2 IOR 0 R/W 9 PB9 IOR 0 R/W 1 PB1 IOR 0 R/W 8 PB8 IOR 0 R/W 0 PB0 IOR 0 R/W The port B IO register (PBIOR) is a 16-bit readable/writable register that selects the input/output direction of the 16 pins in port B. Bits PB15IOR to PB0IOR correspond to pins PB15/PULS5/SCK2 to PB0/TO6A. PBIOR is enabled when port B pins function as general input/output pins (PB15 to PB0) or serial clock pins (SCK0, SCK1, SCK2), and disabled otherwise. When port B pins function as PB15 to PB0 or SCK0, SCK1, and SCK2, a pin becomes an output when the corresponding bit in PBIOR is set to 1, and an input when the bit is cleared to 0. PBIOR is initialized to H'0000 by a power-on reset (excluding a WDT power-on reset), and in hardware standby mode. It is not initialized in software standby mode or sleep mode. Rev.2.0, 07/03, page 652 of 960 20.3.4 Port B Control Registers H and L (PBCRH, PBCRL) Port B control registers H and L (PBCRH, PBCRL) are 16-bit readable/writable registers that select the functions of the 16 multiplex pins in port B. PBCRH selects the functions of the pins for the upper 8 bits of port B, and PBCRL selects the functions of the pins for the lower 8 bits. PBCRH and PBCRL are initialized to H'0000 by a power-on reset (excluding a WDT power-on reset), and in hardware standby mode. They are not initialized in software standby mode or sleep mode. Port B Control Register H (PBCRH) Bit: 15 PB15 MD1 Initial value: R/W: Bit: 0 R/W 7 PB11 MD1 Initial value: R/W: 0 R/W 14 PB15 MD0 0 R/W 6 PB11 MD0 0 R/W 13 PB14 MD1 0 R/W 5 PB10 MD1 0 R/W 12 PB14 MD0 0 R/W 4 PB10 MD0 0 R/W 11 -- 0 R 3 PB9 MD1 0 R/W 10 PB13 MD 0 R/W 2 PB9 MD0 0 R/W 9 PB12 MD1 0 R/W 1 PB8 MD1 0 R/W 8 PB12 MD0 0 R/W 0 PB8 MD0 0 R/W * Bits 15 and 14--PB15 Mode Bits 1 and 0 (PB15MD1, PB15MD0): These bits select the function of pin PB15/PULS5/SCK2. Bit 15: PB15MD1 0 Bit 14: PB15MD0 0 1 1 0 1 Description General input/output (PB15) APC pulse output (PULS5) Serial clock input/output (SCK2) Reserved (Do not set) (Initial value) Rev.2.0, 07/03, page 653 of 960 * Bits 13 and 12--PB14 Mode Bits 1 and 0 (PB14MD1, PB14MD0): These bits select the function of pin PB14/SCK1/TCLKB/T110. Bit 13: PB14MD1 0 Bit 12: PB14MD0 0 1 1 0 1 Description General input/output (PB14) Serial clock input/output (SCK1) ATU-II clock input (TCLKB) ATU-II edge input (TI10) (Initial value) * Bit 11--Reserved: This bit is always read as 0. The write value should always be 0. * Bit 10--PB13 Mode Bit (PB13MD): Selects the function of pin PB13/SCK0. Bit 10: PB13MD 0 1 Description General input/output (PB13) Serial clock input/output (SCK0) (Initial value) * Bits 9 and 8--PB12 Mode Bits 1 and 0 (PB12MD1, PB12MD0): These bits select the function of pin PB12/TCLKA/UBCTRG. Bit 9: PB12MD1 0 Bit 8: PB12MD0 0 1 1 0 1 Description General input/output (PB12) ATU-II clock input (TCLKA) Trigger pulse output (UBCTRG) Reserved (Do not set) (Initial value) * Bits 7 and 6--PB11 Mode Bits 1 and 0 (PB11MD1, PB11MD0): These bits select the function of pin PB11/RxD4/HRxD0/TO8H. Bit 7: PB11MD1 0 Bit 6: PB11MD0 0 1 1 0 1 Description General input/output (PB11) Receive data input (RxD4) HCAN receive data input (HRxD0) ATU-II one-shot pulse output (TO8H) (Initial value) Rev.2.0, 07/03, page 654 of 960 * Bits 5 and 4--PB10 Mode Bits 1 and 0 (PB10MD1, PB10MD0): These bits select the function of pin PB10/TxD4/HTxD0/TO8G. Bit 5: PB10MD1 0 Bit 4: PB10MD0 0 1 1 0 1 Description General input/output (PB10) Transmit data output (TxD4) HCAN transmit data output (HTxD0) ATU-II one-shot pulse output (TO8G) (Initial value) * Bits 3 and 2--PB9 Mode Bits 1 and 0 (PB9MD1, PB9MD0): These bits select the function of pin PB9/RxD3/TO8F. Bit 3: PB9MD1 0 Bit 2: PB9MD0 0 1 1 0 1 Description General input/output (PB9) Receive data input (RxD3) ATU-II one-shot pulse output (TO8F) Reserved (Do not set) (Initial value) * Bits 1 and 0--PB8 Mode Bits 1 and 0 (PB8MD1, PB8MD0): These bits select the function of pin PB8/TxD3/TO8E. Bit 1: PB8MD1 0 Bit 0: PB8MD0 0 1 1 0 1 Description General input/output (PB8) Transmit data output (TxD3) ATU-II one-shot pulse output (TO8E) Reserved (Do not set) (Initial value) Port B Control Register L (PBCRL) Bit: 15 14 13 12 11 10 9 8 PB7MD1 PB7MD0 PB6MD1 PB6MD0 PB5MD1 PB5MD0 PB4MD1 PB4MD0 Initial value: R/W: Bit: 0 R/W 7 -- Initial value: R/W: 0 R 0 R/W 6 PB3MD 0 R/W 0 R/W 5 -- 0 R 0 R/W 4 PB2MD 0 R/W 0 R/W 3 -- 0 R 0 R/W 2 PB1MD 0 R/W 0 R/W 1 -- 0 R 0 R/W 0 PB0MD 0 R/W Rev.2.0, 07/03, page 655 of 960 * Bits 15 and 14--PB7 Mode Bits 1 and 0 (PB7MD1, PB7MD0): These bits select the function of pin PB7/TO7D/TO8D. Bit 15: PB7MD1 0 Bit 14: PB7MD0 0 1 1 0 1 Description General input/output (PB7) ATU-II PWM output (TO7D) ATU-II one-shot pulse output (TO8D) Reserved (Do not set) (Initial value) * Bits 13 and 12--PB6 Mode Bits 1 and 0 (PB6MD1, PB6MD0): These bits select the function of pin PB6/TO7C/TO8C. Bit 13: PB6MD1 0 Bit 12: PB6MD0 0 1 1 0 1 Description General input/output (PB6) ATU-II PWM output (TO7C) ATU-II one-shot pulse output (TO8C) Reserved (Do not set) (Initial value) * Bits 11 and 10--PB5 Mode Bits 1 and 0 (PB5MD1, PB5MD0): These bits select the function of pin PB5/TO7B/TO8B. Bit 11: PB5MD1 0 Bit 10: PB5MD0 0 1 1 0 1 Description General input/output (PB5) ATU-II PWM output (TO7B) ATU-II one-shot pulse output (TO8B) Reserved (Do not set) (Initial value) * Bits 9 and 8--PB4 Mode Bits 1 and 0 (PB4MD1, PB4MD0): These bits select the function of pin PB4/TO7A/TO8A. Bit 9: PB4MD1 0 Bit 8: PB4MD0 0 1 1 0 1 Description General input/output (PB4) ATU-II PWM output (TO7A) ATU-II one-shot pulse output (TO8A) Reserved (Do not set) (Initial value) Rev.2.0, 07/03, page 656 of 960 * Bit 7--Reserved: This bit is always read as 0. The write value should always be 0. * Bit 6--PB3 Mode Bit (PB3MD): Selects the function of pin PB3/TO6D. Bit 6: PB3MD 0 1 Description General input/output (PB3) ATU-II PWM output (TO6D) (Initial value) * Bit 5--Reserved: This bit is always read as 0. The write value should always be 0. * Bit 4--PB2 Mode Bit (PB2MD): Selects the function of pin PB2/TO6C. Bit 4: PB2MD 0 1 Description General input/output (PB2) ATU-II PWM output (TO6C) (Initial value) * Bit 3--Reserved: This bit is always read as 0. The write value should always be 0. * Bit 2--PB1 Mode Bit (PB1MD): Selects the function of pin PB1/TO6B. Bit 2: PB1MD 0 1 Description General input/output (PB1) ATU-II PWM output (TO6B) (Initial value) * Bit 1--Reserved: This bit is always read as 0. The write value should always be 0. * Bit 0--PB0 Mode Bit (PB0MD): Selects the function of pin PB0/TO6A. Bit 0: PB0MD 0 1 Description General input/output (PB0) ATU-II PWM output (TO6A) (Initial value) Rev.2.0, 07/03, page 657 of 960 20.3.5 Port B Invert Register (PBIR) Bit: 15 14 13 12 -- 0 R 4 PB4IR 0 R/W 11 10 9 PB9IR 0 R/W 1 PB1IR 0 R/W 8 PB8IR 0 R/W 0 PB0IR 0 R/W PB15IR PB14IR PB13IR Initial value: R/W: Bit: 0 R/W 7 PB7IR Initial value: R/W: 0 R/W 0 R/W 6 PB6IR 0 R/W 0 R/W 5 PB5IR 0 R/W PB11IR PB10IR 0 R/W 3 PB3IR 0 R/W 0 R/W 2 PB2IR 0 R/W The port B invert register (PBIR) is a 16-bit readable/writable register that sets the port B inversion function. Bits PB15IR to PB13IR and PB11IR to PB0IR correspond to pins PB15/PULS5/SCK2 to PB13/SCK0 and PB11/RxD4/HRxD0/TO8H to PB0/TO6A. PBIR is enabled when port B pins function as ATU-II outputs or serial clock pins, and disabled otherwise. When port B pins function as ATU-II outputs or serial clock pins, the value of a pin is inverted when the corresponding bit in PBIR is set to 1. PBIR is initialized to H'0000 by a power-on reset (excluding a WDT power-on reset), and in hardware standby mode. It is not initialized in software standby mode or sleep mode. PBnIR 0 1 n = 15 to 13, 11 to 0 Description Value is not inverted Value is inverted (Initial value) Rev.2.0, 07/03, page 658 of 960 20.3.6 Port C IO Register (PCIOR) Bit: 15 -- Initial value: R/W: Bit: 0 R 7 -- Initial value: R/W: 0 R 14 -- 0 R 6 -- 0 R 13 -- 0 R 5 -- 0 R 12 -- 0 R 4 11 -- 0 R 3 10 -- 0 R 2 9 -- 0 R 1 8 -- 0 R 0 PC4IOR PC3IOR PC2IOR PC1IOR PC0IOR 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W The port C IO register (PCIOR) is a 16-bit readable/writable register that selects the input/output direction of the 5 pins in port C. Bits PC4IOR to PC0IOR correspond to pins PC4/IRQ0 to PC0/TxD1. PCIOR is enabled when port C pins function as general input/output pins (PC4 to PC0), and disabled otherwise. When port C pins function as PC4 to PC0, a pin becomes an output when the corresponding bit in PCIOR is set to 1, and an input when the bit is cleared to 0. PCIOR is initialized to H'0000 by a power-on reset (excluding a WDT power-on reset), and in hardware standby mode. It is not initialized in software standby mode or sleep mode. 20.3.7 Port C Control Register (PCCR) The port C control register (PCCR) is a 16-bit readable/writable register that selects the functions of the 5 multiplex pins in port C. PCCR is initialized to H'0000 by a power-on reset (excluding a WDT power-on reset), and in hardware standby mode. It is not initialized in software standby mode or sleep mode. Bit: 15 -- Initial value: R/W: Bit: 0 R 7 -- Initial value: R/W: 0 R 14 -- 0 R 6 PC3MD 0 R/W 13 -- 0 R 5 -- 0 R 12 -- 0 R 4 PC2MD 0 R/W 11 -- 0 R 3 -- 0 R 10 -- 0 R 2 PC1MD 0 R/W 9 -- 0 R 1 -- 0 R 8 PC4MD 0 R/W 0 PC0MD 0 R/W Rev.2.0, 07/03, page 659 of 960 * Bits 15 to 9--Reserved: These bits are always read as 0. The write value should always be 0. * Bit 8--PC4 Mode Bit (PC4MD): Selects the function of pin PC4/IRQ0. Bit 8: PC4MD 0 1 Description General input/output (PC4) Interrupt request input (IRQ0) (Initial value) * Bit 7--Reserved: This bit is always read as 0. The write value should always be 0. * Bit 6--PC3 Mode Bit (PC3MD): Selects the function of pin PC3/RxD2. Bit 6: PC3MD 0 1 Description General input/output (PC3) Receive data input (RxD2) (Initial value) * Bit 5--Reserved: This bit is always read as 0. The write value should always be 0. * Bit 4--PC2 Mode Bit (PC2MD): Selects the function of pin PC2/TxD2. Bit 4: PC2MD 0 1 Description General input/output (PC2) Transmit data output (TxD2) (Initial value) * Bit 3--Reserved: This bit is always read as 0. The write value should always be 0. * Bit 2--PC1 Mode Bit (PC1MD): Selects the function of pin PC1/RxD1. Bit 2: PC1MD 0 1 Description General input/output (PC1) Receive data input (RxD1) (Initial value) * Bit 1--Reserved: This bit is always read as 0. The write value should always be 0. * Bit 0--PC0 Mode Bit (PC0MD): Selects the function of pin PC0/TxD1. Bit 0: PC0MD 0 1 Description General input/output (PC0) Transmit data output (TxD1) (Initial value) Rev.2.0, 07/03, page 660 of 960 20.3.8 Port D IO Register (PDIOR) Bit: 15 -- Initial value: R/W: Bit: 0 R 7 PD7 IOR Initial value: R/W: 0 R/W 14 -- 0 R 6 PD6 IOR 0 R/W 13 PD13 IOR 0 R/W 5 PD5 IOR 0 R/W 12 PD12 IOR 0 R/W 4 PD4 IOR 0 R/W 11 PD11 IOR 0 R/W 3 PD3 IOR 0 R/W 10 PD10 IOR 0 R/W 2 PD2 IOR 0 R/W 9 PD9 IOR 0 R/W 1 PD1 IOR 0 R/W 8 PC8 IOR 0 R/W 0 PD0 IOR 0 R/W The port D IO register (PDIOR) is a 16-bit readable/writable register that selects the input/output direction of the 14 pins in port D. Bits PD13IOR to PD0IOR correspond to pins PD13/PULS6/HTxD0/HTxD1 to PD0/TIO1A. PDIOR is enabled when port D pins function as general input/output pins (PD13 to PD0) or timer input/output pins, and disabled otherwise. When port D pins function as PD13 to PD0 or timer input/output pins, a pin becomes an output when the corresponding bit in PDIOR is set to 1, and an input when the bit is cleared to 0. PDIOR is initialized to H'0000 by a power-on reset (excluding a WDT power-on reset), and in hardware standby mode. It is not initialized in software standby mode or sleep mode. 20.3.9 Port D Control Registers H and L (PDCRH, PDCRL) Port D control registers H and L (PDCRH, PDCRL) are 16-bit readable/writable registers that select the functions of the 14 multiplex pins in port D. PDCRH selects the functions of the pins for the upper 6 bits of port D, and PDCRL selects the functions of the pins for the lower 8 bits. PDCRH and PDCRL are initialized to H'0000 by a power-on reset (excluding a WDT power-on reset), and in hardware standby mode. They are not initialized in software standby mode or sleep mode. Rev.2.0, 07/03, page 661 of 960 Port D Control Register H (PDCRH) Bit: 15 -- Initial value: R/W: Bit: 0 R 7 -- Initial value: R/W: 0 R 14 -- 0 R 6 PD11 MD 0 R/W 13 -- 0 R 5 -- 0 R 12 -- 0 R 4 PD10 MD 0 R/W 11 PD13 MD1 0 R/W 3 -- 0 R 10 PD13 MD0 0 R/W 2 PD9 MD 0 R/W 9 -- 0 R 1 -- 0 R 8 PD12 MD 0 R/W 0 PD8 MD 0 R/W * Bits 15 to 12--Reserved: These bits are always read as 0. The write value should always be 0. * Bits 11 and 10--PD13 Mode Bits 1 and 0 (PD13MD1, PD13MD0): These bits select the function of pin PD13/PULS6/HTxD0/HTxD1. Bit 11: PD13MD1 0 Bit 10: PD13MD0 0 1 1 0 1 Description General input/output (PD13) APC pulse output (PULS6) HCAN transmit data output (HTxD0) HCAN transmit data output (HTxD1) (Initial value) * Bit 9--Reserved: This bit is always read as 0. The write value should always be 0. * Bit 8--PD12 Mode Bit (PD12MD): Selects the function of pin PD12/PULS4. Bit 8: PD12MD 0 1 Description General input/output (PD12) APC pulse output (PULS4) (Initial value) * Bit 7--Reserved: This bit is always read as 0. The write value should always be 0. * Bit 6--PD11 Mode Bit (PD11MD): Selects the function of pin PD11/PULS3. Bit 6: PD12MD 0 1 Description General input/output (PD11) APC pulse output (PULS3) (Initial value) Rev.2.0, 07/03, page 662 of 960 * Bit 5--Reserved: This bit is always read as 0. The write value should always be 0. * Bit 4--PD10 Mode Bit (PD10MD): Selects the function of pin PD10/PULS2. Bit 4: PD10MD 0 1 Description General input/output (PD10) APC pulse output (PULS2) (Initial value) * Bit 3--Reserved: This bit is always read as 0. The write value should always be 0. * Bit 2--PD9 Mode Bit (PD9MD): Selects the function of pin PD9/PULS1. Bit 2: PD9MD 0 1 Description General input/output (PD9) APC pulse output (PULS1) (Initial value) * Bit 1--Reserved: This bit is always read as 0. The write value should always be 0. * Bit 0--PD8 Mode Bit (PD8MD): Selects the function of pin PD8/PULS0. Bit 0: PD8MD 0 1 Description General input/output (PD8) APC pulse output (PULS0) (Initial value) Port D Control Register L (PDCRL) Bit: 15 -- Initial value: R/W: Bit: 0 R 7 -- Initial value: R/W: 0 R 14 PD7MD 0 R/W 6 PD3MD 0 R/W 13 -- 0 R 5 -- 0 R 12 PD6MD 0 R/W 4 PD2MD 0 R/W 11 -- 0 R 3 -- 0 R 10 PD5MD 0 R/W 2 PD1MD 0 R/W 9 -- 0 R 1 -- 0 R 8 PD4MD 0 R/W 0 PD0MD 0 R/W Rev.2.0, 07/03, page 663 of 960 * Bit 15--Reserved: This bit is always read as 0. The write value should always be 0. * Bit 14--PD7 Mode Bit (PD7MD): Selects the function of pin PD7/TIO1H. Bit 14: PD7MD 0 1 Description General input/output (PD7) ATU-II input capture input/output compare output (TIO1H) (Initial value) * Bit 13--Reserved: This bit is always read as 0. The write value should always be 0. * Bit 12--PD6 Mode Bit (PD6MD): Selects the function of pin PD6/TIO1G. Bit 12: PD6MD 0 1 Description General input/output (PD6) ATU-II input capture input/output compare output (TIO1G) (Initial value) * Bit 11--Reserved: This bit is always read as 0. The write value should always be 0. * Bit 10--PD5 Mode Bit (PD5MD): Selects the function of pin PD5/TIO1F. Bit 10: PD5MD 0 1 Description General input/output (PD5) ATU-II input capture input/output compare output (TIO1F) (Initial value) * Bit 9--Reserved: This bit is always read as 0. The write value should always be 0. * Bit 8--PD4 Mode Bit (PD4MD): Selects the function of pin PD4/TIO1E. Bit 8: PD4MD 0 1 Description General input/output (PD4) ATU-II input capture input/output compare output (TIO1E) (Initial value) * Bit 7--Reserved: This bit is always read as 0. The write value should always be 0. * Bit 6--PD3 Mode Bit (PD3MD): Selects the function of pin PD3/TIO1D. Bit 6: PD3MD 0 1 Description General input/output (PD3) ATU-II input capture input/output compare output (TIO1D) (Initial value) * Bit 5--Reserved: This bit is always read as 0. The write value should always be 0. * Bit 4--PD2 Mode Bit (PD2MD): Selects the function of pin PD2/TIO1C. Rev.2.0, 07/03, page 664 of 960 Bit 4: PD2MD 0 1 Description General input/output (PD2) ATU-II input capture input/output compare output (TIO1C) (Initial value) * Bit 3--Reserved: This bit is always read as 0. The write value should always be 0. * Bit 2--PD1 Mode Bit (PD1MD): Selects the function of pin PD1/TIO1B. Bit 2: PD1MD 0 1 Description General input/output (PD1) ATU-II input capture input/output compare output (TIO1B) (Initial value) * Bit 1--Reserved: This bit is always read as 0. The write value should always be 0. * Bit 0--PD0 Mode Bit (PD0MD): Selects the function of pin PD0/TIO1A. Bit 0: PD0MD 0 1 Description General input/output (PD0) ATU-II input capture input/output compare output (TIO1A) (Initial value) 20.3.10 Port E IO Register (PEIOR) Bit: 15 PE15 IOR Initial value: R/W: Bit: 0 R/W 7 PE7 IOR Initial value: R/W: 0 R/W 14 PE14 IOR 0 R/W 6 PE6 IOR 0 R/W 13 PE13 IOR 0 R/W 5 PE5 IOR 0 R/W 12 PE12 IOR 0 R/W 4 PE4 IOR 0 R/W 11 PE11 IOR 0 R/W 3 PE3 IOR 0 R/W 10 PE10 IOR 0 R/W 2 PE2 IOR 0 R/W 9 PE9 IOR 0 R/W 1 PE1 IOR 0 R/W 8 PE8 IOR 0 R/W 0 PE0 IOR 0 R/W The port E IO register (PEIOR) is a 16-bit readable/writable register that selects the input/output direction of the 16 pins in port E. Bits PE15IOR to PE0IOR correspond to pins PE15/A15 to PE0/A0. PEIOR is enabled when port E pins function as general input/output pins (PE15 to PE0), and disabled otherwise. When port E pins function as PE15 to PE0, a pin becomes an output when the corresponding bit in PEIOR is set to 1, and an input when the bit is cleared to 0. Rev.2.0, 07/03, page 665 of 960 PEIOR is initialized to H'0000 by a power-on reset (excluding a WDT power-on reset), and in hardware standby mode. It is not initialized in software standby mode or sleep mode. 20.3.11 Port E Control Register (PECR) Bit: 15 PE15 MD Initial value: R/W: Bit: 0 R/W 7 PE7 MD Initial value: R/W: 0 R/W 14 PE14 MD 0 R/W 6 PE6 MD 0 R/W 13 PE13 MD 0 R/W 5 PE5 MD 0 R/W 12 PE12 MD 0 R/W 4 PE4 MD 0 R/W 11 PE11 MD 0 R/W 3 PE3 MD 0 R/W 10 PE10 MD 0 R/W 2 PE2 MD 0 R/W 9 PE9 MD 0 R/W 1 PE1 MD 0 R/W 8 PE8 MD 0 R/W 0 PE0 MD 0 R/W The port E control register (PECR) is a 16-bit readable/writable register that selects the functions of the 16 multiplex pins in port E. PECR settings are not valid in all operating modes. 1. Expanded mode with on-chip ROM disabled Port E pins function as address output pins, and PECR settings are invalid. 2. Expanded mode with on-chip ROM enabled Port E pins are multiplexed as address output pins and general input/output pins. PECR settings are valid. 3. Single-chip mode Port E pins function as general input/output pins, and PECR settings are invalid. PECR is initialized to H'0000 by a power-on reset (excluding a WDT power-on reset), and in hardware standby mode. It is not initialized in software standby mode or sleep mode. * Bit 15--PE15 Mode Bit (PE15MD): Selects the function of pin PE15/A15. Description Bit 15: PE15MD 0 1 Expanded Mode with ROM Disabled Address output (A15) (Initial value) Address output (A15) Expanded Mode with ROM Enabled General input/output (PE15) (Initial value) Address output (A15) Single-Chip Mode General input/output (PE15) (Initial value) General input/output (PE15) Rev.2.0, 07/03, page 666 of 960 * Bit 14--PE14 Mode Bit (PE14MD): Selects the function of pin PE14/A14. Description Bit 14: PE14MD 0 1 Expanded Mode with ROM Disabled Address output (A14) (Initial value) Address output (A14) Expanded Mode with ROM Enabled General input/output (PE14) (Initial value) Address output (A14) Single-Chip Mode General input/output (PE14) (Initial value) General input/output (PE14) * Bit 13--PE13 Mode Bit (PE13MD): Selects the function of pin PE13/A13. Description Bit 13: PE13MD 0 1 Expanded Mode with ROM Disabled Address output (A13) (Initial value) Address output (A13) Expanded Mode with ROM Enabled General input/output (PE13) (Initial value) Address output (A13) Single-Chip Mode General input/output (PE13) (Initial value) General input/output (PE13) * Bit 12--PE12 Mode Bit (PE12MD): Selects the function of pin PE12/A12. Description Bit 12: PE12MD 0 1 Expanded Mode with ROM Disabled Address output (A12) (Initial value) Address output (A12) Expanded Mode with ROM Enabled General input/output (PE12) (Initial value) Address output (A12) Single-Chip Mode General input/output (PE12) (Initial value) General input/output (PE12) * Bit 11--PE11 Mode Bit (PE11MD): Selects the function of pin PE11/A11. Description Bit 11: PE11MD 0 1 Expanded Mode with ROM Disabled Address output (A11) (Initial value) Address output (A11) Expanded Mode with ROM Enabled General input/output (PE11) (Initial value) Address output (A11) Single-Chip Mode General input/output (PE11) (Initial value) General input/output (PE11) Rev.2.0, 07/03, page 667 of 960 * Bit 10--PE10 Mode Bit (PE10MD): Selects the function of pin PE10/A10. Description Bit 10: PE10MD 0 1 Expanded Mode with ROM Disabled Address output (A10) (Initial value) Address output (A10) Expanded Mode with ROM Enabled General input/output (PE10) (Initial value) Address output (A10) Single-Chip Mode General input/output (PE10) (Initial value) General input/output (PE10) * Bit 9--PE9 Mode Bit (PE9MD): Selects the function of pin PE9/A9. Description Bit 9: PE9MD 0 1 Expanded Mode with ROM Disabled Address output (A9) (Initial value) Address output (A9) Expanded Mode with ROM Enabled General input/output (PE9) (Initial value) Address output (A9) Single-Chip Mode General input/output (PE9) (Initial value) General input/output (PE9) * Bit 8--PE8 Mode Bit (PE8MD): Selects the function of pin PE8/A8. Description Bit 8: PE8MD 0 1 Expanded Mode with ROM Disabled Address output (A8) (Initial value) Address output (A8) Expanded Mode with ROM Enabled General input/output (PE8) (Initial value) Address output (A8) Single-Chip Mode General input/output (PE8) (Initial value) General input/output (PE8) * Bit 7--PE7 Mode Bit (PE7MD): Selects the function of pin PE7/A7. Description Bit 7: PE7MD 0 1 Expanded Mode with ROM Disabled Address output (A7) (Initial value) Address output (A7) Expanded Mode with ROM Enabled General input/output (PE7) (Initial value) Address output (A7) Single-Chip Mode General input/output (PE7) (Initial value) General input/output (PE7) Rev.2.0, 07/03, page 668 of 960 * Bit 6--PE6 Mode Bit (PE6MD): Selects the function of pin PE6/A6. Description Bit 6: PE6MD 0 1 Expanded Mode with ROM Disabled Address output (A6) (Initial value) Address output (A6) Expanded Mode with ROM Enabled General input/output (PE6) (Initial value) Address output (A6) Single-Chip Mode General input/output (PE6) (Initial value) General input/output (PE6) * Bit 5--PE5 Mode Bit (PE5MD): Selects the function of pin PE5/A5. Description Bit 5: PE5MD 0 1 Expanded Mode with ROM Disabled Address output (A5) (Initial value) Address output (A5) Expanded Mode with ROM Enabled General input/output (PE5) (Initial value) Address output (A5) Single-Chip Mode General input/output (PE5) (Initial value) General input/output (PE5) * Bit 4--PE4 Mode Bit (PE4MD): Selects the function of pin PE4/A4. Description Bit 4: PE4MD 0 1 Expanded Mode with ROM Disabled Address output (A4) (Initial value) Address output (A4) Expanded Mode with ROM Enabled General input/output (PE4) (Initial value) Address output (A4) Single-Chip Mode General input/output (PE4) (Initial value) General input/output (PE4) * Bit 3--PE3 Mode Bit (PE3MD): Selects the function of pin PE3/A3. Description Bit 3: PE3MD 0 1 Expanded Mode with ROM Disabled Address output (A3) (Initial value) Address output (A3) Expanded Mode with ROM Enabled General input/output (PE3) (Initial value) Address output (A3) Single-Chip Mode General input/output (PE3) (Initial value) General input/output (PE3) Rev.2.0, 07/03, page 669 of 960 * Bit 2--PE2 Mode Bit (PE2MD): Selects the function of pin PE2/A2. Description Bit 2: PE2MD 0 1 Expanded Mode with ROM Disabled Address output (A2) (Initial value) Address output (A2) Expanded Mode with ROM Enabled General input/output (PE2) (Initial value) Address output (A2) Single-Chip Mode General input/output (PE2) (Initial value) General input/output (PE2) * Bit 1--PE1 Mode Bit (PE1MD): Selects the function of pin PE1/A1. Description Bit 1: PE1MD 0 1 Expanded Mode with ROM Disabled Address output (A1) (Initial value) Address output (A1) Expanded Mode with ROM Enabled General input/output (PE1) (Initial value) Address output (A1) Single-Chip Mode General input/output (PE1) (Initial value) General input/output (PE1) * Bit 0--PE0 Mode Bit (PE0MD): Selects the function of pin PE0/A0. Description Bit 0: PE0MD 0 1 Expanded Mode with ROM Disabled Address output (A0) (Initial value) Address output (A0) Expanded Mode with ROM Enabled General input/output (PE0) (Initial value) Address output (A0) Single-Chip Mode General input/output (PE0) (Initial value) General input/output (PE0) Rev.2.0, 07/03, page 670 of 960 20.3.12 Port F IO Register (PFIOR) Bit: 15 PF15 IOR Initial value: R/W: Bit: 0 R/W 7 PF7 IOR Initial value: R/W: 0 R/W 14 PF14 IOR 0 R/W 6 PF6 IOR 0 R/W 13 PF13 IOR 0 R/W 5 PF5 IOR 0 R/W 12 PF12 IOR 0 R/W 4 PF4 IOR 0 R/W 11 PF11 IOR 0 R/W 3 PF3 IOR 0 R/W 10 PF10 IOR 0 R/W 2 PF2 IOR 0 R/W 9 PF9 IOR 0 R/W 1 PF1 IOR 0 R/W 8 PF8 IOR 0 R/W 0 PF0 IOR 0 R/W The port F IO register (PFIOR) is a 16-bit readable/writable register that selects the input/output direction of the 16 pins in port F. Bits PF15IOR to PF0IOR correspond to pins PF15/BREQ to PF0/A16. PFIOR is enabled when port F pins function as general input/output pins (PF15 to PF0), and disabled otherwise. When port F pins function as PF15 to PF0, a pin becomes an output when the corresponding bit in PFIOR is set to 1, and an input when the bit is cleared to 0. PFIOR is initialized to H'0000 by a power-on reset (excluding a WDT power-on reset), and in hardware standby mode. It is not initialized in software standby mode or sleep mode. Rev.2.0, 07/03, page 671 of 960 20.3.13 Port F Control Registers H and L (PFCRH, PFCRL) Port F control registers H and L (PFCRH, PFCRL) are 16-bit readable/writable registers that select the functions of the 16 multiplex pins in port F and the function of the CK pin. PFCRH selects the functions of the pins for the upper 8 bits of port F, and PFCRL selects the functions of the pins for the lower 8 bits. PFCRH and PFCRL are initialized to H'0015 and H'5000, respectively, by a power-on reset (excluding a WDT power-on reset), and in hardware standby mode. They are not initialized in software standby mode or sleep mode. Port F Control Register H (PFCRH) Bit: 15 14 13 -- 0 R 5 -- 0 R 12 PF14MD 0 R/W 4 PF10MD 1 R/W 11 -- 0 R 3 -- 0 R 10 PF13MD 0 R/W 2 PF9MD 1 R/W 9 -- 0 R 1 -- 0 R 8 PF12MD 0 R/W 0 PF8MD 1 R/W CKHIZ PF15MD Initial value: R/W: Bit: 0 R/W 7 -- Initial value: R/W: 0 R 0 R/W 6 PF11MD 0 R/W * Bit 15--CKHIZ Bit: Selects the function of pin CK. Bit: CKHIZ 0 1 Description CK pin output CK pin Hi-Z (Initial value) * Bit 14--PF15 Mode Bit (PF15MD): Selects the function of pin PF15/BREQ. Description Bit 14: PF15MD 0 1 Expanded Mode General input/output (PF15) (Initial value) Bus request input (BREQ) Single-Chip Mode General input/output (PF15) (Initial value) General input/output (PF15) Rev.2.0, 07/03, page 672 of 960 * Bit 13--Reserved: This bit is always read as 0. The write value should always be 0. * Bit 12--PF14 Mode Bit (PF14MD): Selects the function of pin PF14/BACK. Description Bit 12: PF14MD 0 1 Expanded Mode General input/output (PF14) (Initial value) Bus acknowledge output (BACK) Single-Chip Mode General input/output (PF14) (Initial value) General input/output (PF14) * Bit 11--Reserved: This bit is always read as 0. The write value should always be 0. * Bit 10--PF13 Mode Bit (PF13MD): Selects the function of pin PF13/CS3. Description Bit 10: PF13MD 0 1 Expanded Mode General input/output (PF13) (Initial value) Chip select output (CS3) Single-Chip Mode General input/output (PF13) (Initial value) General input/output (PF13) * Bit 9--Reserved: This bit is always read as 0. The write value should always be 0. * Bit 8--PF12 Mode Bit (PF12MD): Selects the function of pin PF12/CS2. Description Bit 8: PF12MD 0 1 Expanded Mode General input/output (PF12) (Initial value) Chip select output (CS2) Single-Chip Mode General input/output (PF12) (Initial value) General input/output (PF12) * Bit 7--Reserved: This bit is always read as 0. The write value should always be 0. * Bit 6--PF11 Mode Bit (PF11MD): Selects the function of pin PF11/CS1. Description Bit 6: PF11MD 0 1 Expanded Mode General input/output (PF11) (Initial value) Chip select output (CS1) Single-Chip Mode General input/output (PF11) (Initial value) General input/output (PF11) Rev.2.0, 07/03, page 673 of 960 * Bit 5--Reserved: This bit is always read as 0. The write value should always be 0. * Bit 4--PF10 Mode Bit (PF10MD): Selects the function of pin PF10/CS0. Description Bit 4: PF10MD 0 1 Expanded Mode General input/output (PF10) Chip select output (CS0) (Initial value) Single-Chip Mode General input/output (PF10) General input/output (PF10) (Initial value) * Bit 3--Reserved: This bit is always read as 0. The write value should always be 0. * Bit 2--PF9 Mode Bit (PF9MD): Selects the function of pin PF9/RD. Description Bit 2: PF9MD 0 1 Expanded Mode General input/output (PF9) Read output (RD) (Initial value) Single-Chip Mode General input/output (PF9) General input/output (PF9) (Initial value) * Bit 1--Reserved: This bit is always read as 0. The write value should always be 0. * Bit 0--PF8 Mode Bit (PF8MD): Selects the function of pin PF8/WAIT. Description Bit 0: PF8MD 0 1 Expanded Mode General input/output (PF8) Wait state input (WAIT) (Initial value) Single-Chip Mode General input/output (PF8) General input/output (PF8) (Initial value) Port F Control Register L (PFCRL) Bit: 15 -- Initial value: R/W: Bit: 0 R 7 -- Initial value: R/W: 0 R 14 PF7MD 1 R/W 6 PF3MD 0 R/W 13 -- 0 R 5 -- 0 R 12 11 10 9 -- 0 R 1 -- 0 R 8 PF4MD 0 R/W 0 PF0MD 0 R/W PF6MD PF5MD1 PF5MD0 1 R/W 4 PF2MD 0 R/W 0 R/W 3 -- 0 R 0 R/W 2 PF1MD 0 R/W Rev.2.0, 07/03, page 674 of 960 * Bit 15--Reserved: This bit is always read as 0. The write value should always be 0. * Bit 14--PF7 Mode Bit (PF7MD): Selects the function of pin PF7/WRH. Description Bit 14: PF7MD 0 1 Expanded Mode General input/output (PF7) Upper write (WRH) (Initial value) Single-Chip Mode General input/output (PF7) General input/output (PF7) (Initial value) * Bit 13--Reserved: This bit is always read as 0. The write value should always be 0. * Bit 12--PF6 Mode Bit (PF6MD): Selects the function of pin PF6/WRL. Description Bit 12: PF6MD 0 1 Expanded Mode General input/output (PF6) Lower write (WRL) (Initial value) Single-Chip Mode General input/output (PF6) General input/output (PF6) (Initial value) * Bits 11 and 10--PF5 Mode Bits 1 and 0 (PF5MD1, PF5MD0): These bits select the function of pin PF5/A21/POD. Description Bit 11: PF5MD1 0 Bit 10: PF5MD0 0 1 1 0 1 Expanded Mode with ROM Disabled Address output (A21) (Initial value) Address output (A21) Address output (A21) Reserved (Do not set) Expanded Mode with ROM Enabled General input/output (PF5) (Initial value) Address output (A21) Port output disable input (POD) Reserved (Do not set) Single-Chip Mode General input/output (PF5) (Initial value) General input/output (PF5) Port output disable input (POD) Reserved (Do not set) Rev.2.0, 07/03, page 675 of 960 * Bit 9--Reserved: This bit is always read as 0. The write value should always be 0. * Bit 8--PF4 Mode Bit (PF4MD): Selects the function of pin PF4/A20. Description Bit 8: PF4MD 0 1 Expanded Mode with ROM Disabled Address output (A20) (Initial value) Address output (A20) Expanded Mode with ROM Enabled General input/output (PF4) (Initial value) Address output (A20) Single-Chip Mode General input/output (PF4) (Initial value) General input/output (PF4) * Bit 7--Reserved: This bit is always read as 0. The write value should always be 0. * Bit 6--PF3 Mode Bit (PF3MD): Selects the function of pin PF3/A19. Description Bit 6: PF3MD 0 1 Expanded Mode with ROM Disabled Address output (A19) (Initial value) Address output (A19) Expanded Mode with ROM Enabled General input/output (PF3) (Initial value) Address output (A19) Single-Chip Mode General input/output (PF3) (Initial value) General input/output (PF3) * Bit 5--Reserved: This bit is always read as 0. The write value should always be 0. * Bit 4--PF2 Mode Bit (PF2MD): Selects the function of pin PF2/A18. Description Bit 4: PF2MD 0 1 Expanded Mode with ROM Disabled Address output (A18) (Initial value) Address output (A18) Expanded Mode with ROM Enabled General input/output (PF2) (Initial value) Address output (A18) Single-Chip Mode General input/output (PF2) (Initial value) General input/output (PF2) * Bit 3--Reserved: This bit is always read as 0. The write value should always be 0. * Bit 2--PF1 Mode Bit (PF1MD): Selects the function of pin PF1/A17. Description Bit 2: PF1MD 0 1 Expanded Mode with ROM Disabled Address output (A17) (Initial value) Address output (A17) Expanded Mode with ROM Enabled General input/output (PF1) (Initial value) Address output (A17) Single-Chip Mode General input/output (PF1) (Initial value) General input/output (PF1) Rev.2.0, 07/03, page 676 of 960 * Bit 1--Reserved: This bit is always read as 0. The write value should always be 0. * Bit 0--PF0 Mode Bit (PF0MD): Selects the function of pin PF0/A16. Description Bit 0: PF0MD 0 1 Expanded Mode with ROM Disabled Address output (A16) (Initial value) Address output (A16) Expanded Mode with ROM Enabled General input/output (PF0) (Initial value) Address output (A16) Single-Chip Mode General input/output (PF0) (Initial value) General input/output (PF0) 20.3.14 Port G IO Register (PGIOR) Bit: 15 -- Initial value: R/W: Bit: 0 R 7 -- Initial value: R/W: 0 R 14 -- 0 R 6 -- 0 R 13 -- 0 R 5 -- 0 R 12 -- 0 R 4 -- 0 R 11 -- 0 R 3 10 -- 0 R 2 9 -- 0 R 1 8 -- 0 R 0 PG3IOR PG2IOR PG1IOR PG0IOR 0 R/W 0 R/W 0 R/W 0 R/W The port G IO register (PGIOR) is a 16-bit readable/writable register that selects the input/output direction of the 4 pins in port G. Bits PG3IOR to PG0IOR correspond to pins PG3/IRQ3/ADTRG0 to PG0/PULS7/HRxD0/HRxD1. When port G pins function as PG3 to PG0, a pin becomes an output when the corresponding bit in PGIOR is set to 1, and an input when the bit is cleared to 0. PGIOR is initialized to H'0000 by a power-on reset (excluding a WDT power-on reset), and in hardware standby mode. It is not initialized in software standby mode or sleep mode. Rev.2.0, 07/03, page 677 of 960 20.3.15 Port G Control Register (PGCR) The port G control register (PGCR) is a 16-bit readable/writable register that selects the functions of the 4 multiplex pins in port G. PGCR is initialized to H'0000 by a power-on reset (excluding a WDT power-on reset), and in hardware standby mode. It is not initialized in software standby mode or sleep mode. Bit: 15 -- Initial value: R/W: Bit: 0 R 7 14 -- 0 R 6 13 -- 0 R 5 12 -- 0 R 4 11 -- 0 R 3 -- 0 R 10 -- 0 R 2 9 -- 0 R 1 8 -- 0 R 0 PG3MD1 PG3MD0 PG2MD1 PG2MD0 Initial value: R/W: 0 R/W 0 R/W 0 R/W 0 R/W PG1MD PG0MD1 PG0MD0 0 R/W 0 R/W 0 R/W * Bits 15 to 8--Reserved: These bits are always read as 0. The write value should always be 0. * Bits 7 and 6--PG3 Mode Bits 1 and 0 (PG3MD1, PG3MD0): These bits select the function of pin PG3/IRQ3/ADTRG0. Bit 7: PG3MD1 0 Bit 6: PG3MD0 0 1 1 0 1 Description General input/output (PG3) Interrupt request input (IRQ3) A/D conversion trigger input (ADTRG0) Reserved (Do not set) (Initial value) * Bits 5 and 4--PG2 Mode Bits 1 and 0 (PG2MD1, PG2MD0): These bits select the function of pin PG2/IRQ2/ADEND. Bit 5: PG2MD1 0 Bit 4: PG2MD0 0 1 1 0 1 Description General input/output (PG2) Interrupt request input (IRQ2) A/D conversion end output (ADEND) Reserved (Do not set) (Initial value) Rev.2.0, 07/03, page 678 of 960 * Bit 3--Reserved: This bit is always read as 0. The write value should always be 0. * Bit 2--PG1 Mode Bit (PG1MD): Selects the function of pin PG1/IRQ1. Bit 2: PG1MD 0 1 Description General input/output (PG1) Interrupt request input (IRQ1) (Initial value) * Bits 1 and 0--PG0 Mode Bits 1 and 0 (PG0MD1, PG2MD0): These bits select the function of pin PG0/PULS7/HRxD0/HRxD1. Bit 1: PG0MD1 0 Bit 0: PG0MD0 0 1 1 0 1 Description General input/output (PG0) APC pulse output (PULS7) HCAN receive data input (HRxD0) HCAN receive data input (HRxD1) (Initial value) 20.3.16 Port H IO Register (PHIOR) Bit: 15 PH15 IOR Initial value: R/W: Bit: 0 R/W 7 PH7 IOR Initial value: R/W: 0 R/W 14 PH14 IOR 0 R/W 6 PH6 IOR 0 R/W 13 PH13 IOR 0 R/W 5 PH5 IOR 0 R/W 12 PH12 IOR 0 R/W 4 PH4 IOR 0 R/W 11 PH11 IOR 0 R/W 3 PH3 IOR 0 R/W 10 PH10 IOR 0 R/W 2 PH2 IOR 0 R/W 9 PH9 IOR 0 R/W 1 PH1 IOR 0 R/W 8 PH8 IOR 0 R/W 0 PH0 IOR 0 R/W The port H IO register (PHIOR) is a 16-bit readable/writable register that selects the input/output direction of the 16 pins in port H. Bits PH15IOR to PH0IOR correspond to pins PH15/D15 to PH0/D0. PHIOR is enabled when port H pins function as general input/output pins (PH15 to PH0), and disabled otherwise. When port H pins function as PH15 to PH0, a pin becomes an output when the corresponding bit in PHIOR is set to 1, and an input when the bit is cleared to 0. PHIOR is initialized to H'0000 by a power-on reset (excluding a WDT power-on reset), and in hardware standby mode. It is not initialized in software standby mode or sleep mode. Rev.2.0, 07/03, page 679 of 960 20.3.17 Port H Control Register (PHCR) Bit: 15 PH15 MD Initial value: R/W: Bit: 0 R/W 7 PH7 MD Initial value: R/W: 0 R/W 14 PH14 MD 0 R/W 6 PH6 MD 0 R/W 13 PH13 MD 0 R/W 5 PH5 MD 0 R/W 12 PH12 MD 0 R/W 4 PH4 MD 0 R/W 11 PH11 MD 0 R/W 3 PH3 MD 0 R/W 10 PH10 MD 0 R/W 2 PH2 MD 0 R/W 9 PH9 MD 0 R/W 1 PH1 MD 0 R/W 8 PH8 MD 0 R/W 0 PH0 MD 0 R/W The port H control register (PHCR) is a 16-bit readable/writable register that selects the functions of the 16 multiplex pins in port H. PHCR settings are not valid in all operating modes. 1. Expanded mode with on-chip ROM disabled (area 0: 8-bit bus) Port H pins D0 to D7 function as data input/output pins, and PHCR settings are invalid. 2. Expanded mode with on-chip ROM disabled (area 0: 16-bit bus) Port H pins function as data input/output pins, and PHCR settings are invalid. 3. Expanded mode with on-chip ROM enabled Port H pins are multiplexed as data input/output pins and general input/output pins. PHCR settings are valid. 4. Single-chip mode Port H pins function as general input/output pins, and PHCR settings are invalid. PHCR is initialized to H'0000 by a power-on reset (excluding a WDT power-on reset), and in hardware standby mode. It is not initialized in software standby mode or sleep mode. Rev.2.0, 07/03, page 680 of 960 * Bit 15--PH15 Mode Bit (PH15MD): Selects the function of pin PH15/D15. Description Bit 15: PH15MD 0 Expanded Mode Expanded Mode with ROM Disabled with ROM Disabled Expanded Mode Area 0: 8 Bits Area 0: 16 Bits with ROM Enabled Single-Chip Mode General input/output Data input/output (PH15) (D15) (Initial value) (Initial value) Data input/output (D15) Data input/output (D15) General input/output General input/output (PH15) (PH15) (Initial value) (Initial value) Data input/output (D15) General input/output (PH15) 1 * Bit 14--PH14 Mode Bit (PH14MD): Selects the function of pin PH14/D14. Description Bit 14: PH14MD 0 Expanded Mode Expanded Mode with ROM Disabled with ROM Disabled Expanded Mode Area 0: 8 Bits Area 0: 16 Bits with ROM Enabled Single-Chip Mode General input/output Data input/output (PH14) (D14) (Initial value) (Initial value) Data input/output (D14) Data input/output (D14) General input/output General input/output (PH14) (PH14) (Initial value) (Initial value) Data input/output (D14) General input/output (PH14) 1 * Bit 13--PH13 Mode Bit (PH13MD): Selects the function of pin PH13/D13. Description Bit 13: PH13MD 0 Expanded Mode Expanded Mode with ROM Disabled with ROM Disabled Expanded Mode Area 0: 8 Bits Area 0: 16 Bits with ROM Enabled Single-Chip Mode General input/output Data input/output (PH13) (D13) (Initial value) (Initial value) Data input/output (D13) Data input/output (D13) General input/output General input/output (PH13) (PH13) (Initial value) (Initial value) Data input/output (D13) General input/output (PH13) 1 Rev.2.0, 07/03, page 681 of 960 * Bit 12--PH12 Mode Bit (PH12MD): Selects the function of pin PH12/D12. Description Bit 12: PH12MD 0 Expanded Mode Expanded Mode with ROM Disabled with ROM Disabled Expanded Mode Area 0: 8 Bits Area 0: 16 Bits with ROM Enabled Single-Chip Mode General input/output Data input/output (PH12) (D12) (Initial value) (Initial value) Data input/output (D12) Data input/output (D12) General input/output General input/output (PH12) (PH12) (Initial value) (Initial value) Data input/output (D12) General input/output (PH12) 1 * Bit 11--PH11 Mode Bit (PH11MD): Selects the function of pin PH11/D11. Description Bit 11: PH11MD 0 Expanded Mode Expanded Mode with ROM Disabled with ROM Disabled Expanded Mode Area 0: 8 Bits Area 0: 16 Bits with ROM Enabled Single-Chip Mode General input/output Data input/output (PH11) (D11) (Initial value) (Initial value) Data input/output (D11) Data input/output (D11) General input/output General input/output (PH11) (PH11) (Initial value) (Initial value) Data input/output (D11) General input/output (PH11) 1 * Bit 10--PH10 Mode Bit (PH10MD): Selects the function of pin PH10/D10. Description Bit 10: PH10MD 0 Expanded Mode Expanded Mode with ROM Disabled with ROM Disabled Expanded Mode Area 0: 8 Bits Area 0: 16 Bits with ROM Enabled Single-Chip Mode General input/output Data input/output (PH10) (D10) (Initial value) (Initial value) Data input/output (D10) Data input/output (D10) General input/output General input/output (PH10) (PH10) (Initial value) (Initial value) Data input/output (D10) General input/output (PH10) 1 Rev.2.0, 07/03, page 682 of 960 * Bit 9--PH9 Mode Bit (PH9MD): Selects the function of pin PH9/D9. Description Bit 9: PH9MD 0 Expanded Mode Expanded Mode with ROM Disabled with ROM Disabled Expanded Mode Area 0: 8 Bits Area 0: 16 Bits with ROM Enabled Single-Chip Mode General input/output Data input/output (PH9) (D9) (Initial value) (Initial value) Data input/output (D9) Data input/output (D9) General input/output General input/output (PH9) (PH9) (Initial value) (Initial value) Data input/output (D9) General input/output (PH9) 1 * Bit 8--PH8 Mode Bit (PH8MD): Selects the function of pin PH8/D8. Description Bit 8: PH8MD 0 Expanded Mode Expanded Mode with ROM Disabled with ROM Disabled Expanded Mode Area 0: 8 Bits Area 0: 16 Bits with ROM Enabled Single-Chip Mode General input/output Data input/output (PH8) (D8) (Initial value) (Initial value) Data input/output (D8) Data input/output (D8) General input/output General input/output (PH8) (PH8) (Initial value) (Initial value) Data input/output (D8) General input/output (PH8) 1 * Bit 7--PH7 Mode Bit (PH7MD): Selects the function of pin PH7/D7. Description Bit 7: PH7MD 0 1 Expanded Mode with ROM Disabled Data input/output (D7) (Initial value) Data input/output (D7) Expanded Mode with ROM Enabled General input/output (PH7) (Initial value) Data input/output (D7) Single-Chip Mode General input/output (PH7) (Initial value) General input/output (PH7) Rev.2.0, 07/03, page 683 of 960 * Bit 6--PH6 Mode Bit (PH6MD): Selects the function of pin PH6/D6. Description Bit 6: PH6MD 0 1 Expanded Mode with ROM Disabled Data input/output (D6) (Initial value) Data input/output (D6) Expanded Mode with ROM Enabled General input/output (PH6) (Initial value) Data input/output (D6) Single-Chip Mode General input/output (PH6) (Initial value) General input/output (PH6) * Bit 5--PH5 Mode Bit (PH5MD): Selects the function of pin PH5/D5. Description Bit 5: PH5MD 0 1 Expanded Mode with ROM Disabled Data input/output (D5) (Initial value) Data input/output (D5) Expanded Mode with ROM Enabled General input/output (PH5) (Initial value) Data input/output (D5) Single-Chip Mode General input/output (PH5) (Initial value) General input/output (PH5) * Bit 4--PH4 Mode Bit (PH4MD): Selects the function of pin PH4/D4. Description Bit 4: PH4MD 0 1 Expanded Mode with ROM Disabled Data input/output (D4) (Initial value) Data input/output (D4) Expanded Mode with ROM Enabled General input/output (PH4) (Initial value) Data input/output (D4) Single-Chip Mode General input/output (PH4) (Initial value) General input/output (PH4) * Bit 3--PH3 Mode Bit (PH3MD): Selects the function of pin PH3/D3. Description Bit 3: PH3MD 0 1 Expanded Mode with ROM Disabled Data input/output (D3) (Initial value) Data input/output (D3) Expanded Mode with ROM Enabled General input/output (PH3) (Initial value) Data input/output (D3) Single-Chip Mode General input/output (PH3) (Initial value) General input/output (PH3) Rev.2.0, 07/03, page 684 of 960 * Bit 2--PH2 Mode Bit (PH2MD): Selects the function of pin PH2/D2. Description Bit 2: PH2MD 0 1 Expanded Mode with ROM Disabled Data input/output (D2) (Initial value) Data input/output (D2) Expanded Mode with ROM Enabled General input/output (PH2) (Initial value) Data input/output (D2) Single-Chip Mode General input/output (PH2) (Initial value) General input/output (PH2) * Bit 1--PH1 Mode Bit (PH1MD): Selects the function of pin PH1/D1. Description Bit 1: PH1MD 0 1 Expanded Mode with ROM Disabled Data input/output (D1) (Initial value) Data input/output (D1) Expanded Mode with ROM Enabled General input/output (PH1) (Initial value) Data input/output (D1) Single-Chip Mode General input/output (PH1) (Initial value) General input/output (PH1) * Bit 0--PH0 Mode Bit (PH0MD): Selects the function of pin PH0/D0. Description Bit 0: PH0MD 0 1 Expanded Mode with ROM Disabled Data input/output (D0) (Initial value) Data input/output (D0) Expanded Mode with ROM Enabled General input/output (PH0) (Initial value) Data input/output (D0) Single-Chip Mode General input/output (PH0) (Initial value) General input/output (PH0) Rev.2.0, 07/03, page 685 of 960 20.3.18 Port J IO Register (PJIOR) Bit: 15 PJ15 IOR Initial value: R/W: Bit: 0 R/W 7 PJ7 IOR Initial value: R/W: 0 R/W 14 PJ14 IOR 0 R/W 6 PJ6 IOR 0 R/W 13 PJ13 IOR 0 R/W 5 PJ5 IOR 0 R/W 12 PJ12 IOR 0 R/W 4 PJ4 IOR 0 R/W 11 PJ11 IOR 0 R/W 3 PJ3 IOR 0 R/W 10 PJ10 IOR 0 R/W 2 PJ2 IOR 0 R/W 9 PJ9 IOR 0 R/W 1 PJ1 IOR 0 R/W 8 PJ8 IOR 0 R/W 0 PJ0 IOR 0 R/W The port J IO register (PJIOR) is a 16-bit readable/writable register that selects the input/output direction of the 16 pins in port J. Bits PJ15IOR to PJ0IOR correspond to pins PJ15/TI9F to PJ0/TIO2A. PJIOR is enabled when port J pins function as general input/output pins (PJ15 to PJ0) or ATU-II input/output pins, and disabled otherwise. When ATU-II event counter input is selected, however, the bits 10 to 15 of the PJIOR should be cleared to 0. When port J pins function as PJ15 to PJ0 or ATU-II input/output pins, a pin becomes an output when the corresponding bit in PJIOR is set to 1, and an input when the bit is cleared to 0. PJIOR is initialized to H'0000 by a power-on reset (excluding a WDT power-on reset), and in hardware standby mode. It is not initialized in software standby mode or sleep mode. Rev.2.0, 07/03, page 686 of 960 20.3.19 Port J Control Registers H and L (PJCRH, PJCRL) Port J control registers H and L (PJCRH, PJCRL) are 16-bit readable/writable registers that select the functions of the 16 multiplex pins in port J. PJCRH selects the functions of the pins for the upper 8 bits of port J, and PJCRL selects the functions of the pins for the lower 8 bits. PJCRH and PJCRL are initialized to H'0000 by a power-on reset (excluding a WDT power-on reset), and in hardware standby mode. They are not initialized in software standby mode or sleep mode. Port J Control Register H (PJCRH) Bit: 15 -- Initial value: R/W: Bit: 0 R 7 -- Initial value: R/W: 0 R 14 PJ15MD 0 R/W 6 PJ11MD 0 R/W 13 -- 0 R 5 -- 0 R 12 PJ14MD 0 R/W 4 PJ10MD 0 R/W 11 -- 0 R 3 -- 0 R 10 PJ13MD 0 R/W 2 PJ9MD 0 R/W 9 -- 0 R 1 -- 0 R 8 PJ12MD 0 R/W 0 PJ8MD 0 R/W * Bit 15--Reserved: This bit is always read as 0. The write value should always be 0. * Bit 14--PJ15 Mode Bit (PJ15MD): Selects the function of pin PJ15/TI9F. Bit 14: PJ15MD 0 1 Description General input/output (PJ15) ATU-II event counter input (TI9F) (Initial value) * Bit 13--Reserved: This bit is always read as 0. The write value should always be 0. * Bit 12--PJ14 Mode Bit (PJ14MD): Selects the function of pin PJ14/TI9E. Bit 12: PJ14MD 0 1 Description General input/output (PJ14) ATU-II event counter input (TI9E) (Initial value) Rev.2.0, 07/03, page 687 of 960 * Bit 11--Reserved: This bit is always read as 0. The write value should always be 0. * Bit 10--PJ13 Mode Bit (PJ13MD): Selects the function of pin PJ13/TI9D. Bit 10: PJ13MD 0 1 Description General input/output (PJ13) ATU-II event counter input (TI9D) (Initial value) * Bit 9--Reserved: This bit is always read as 0. The write value should always be 0. * Bit 8--PJ12 Mode Bit (PJ12MD): Selects the function of pin PJ12/TI9C. Bit 8: PJ12MD 0 1 Description General input/output (PJ12) ATU-II event counter input (TI9C) (Initial value) * Bit 7--Reserved: This bit is always read as 0. The write value should always be 0. * Bit 6--PJ11 Mode Bit (PJ11MD): Selects the function of pin PJ11/TI9B. Bit 6: PJ11MD 0 1 Description General input/output (PJ11) ATU-II event counter input (TI9B) (Initial value) * Bit 5--Reserved: This bit is always read as 0. The write value should always be 0. * Bit 4--PJ10 Mode Bit (PJ10MD): Selects the function of pin PJ10/TI9A. Bit 4: PJ10MD 0 1 Description General input/output (PJ10) ATU-II event counter input (TI9A) (Initial value) * Bit 3--Reserved: This bit is always read as 0. The write value should always be 0. * Bit 2--PJ9 Mode Bit (PJ9MD): Selects the function of pin PJ9/TIO5D. Bit 2: PJ9MD 0 1 Description General input/output (PJ9) ATU-II input capture input/output compare output (TIO5D) (Initial value) Rev.2.0, 07/03, page 688 of 960 * Bit 1--Reserved: This bit is always read as 0. The write value should always be 0. * Bit 0--PJ8 Mode Bit (PJ8MD): Selects the function of pin PJ8/TIO5C. Bit 0: PJ8MD 0 1 Description General input/output (PJ8) ATU-II input capture input/output compare output (TIO5C) (Initial value) Port J Control Register L (PJCRL) Bit: 15 -- Initial value: R/W: Bit: 0 R 7 -- Initial value: R/W: 0 R 14 PJ7MD 0 R/W 6 PJ3MD 0 R/W 13 -- 0 R 5 -- 0 R 12 PJ6MD 0 R/W 4 PJ2MD 0 R/W 11 -- 0 R 3 -- 0 R 10 PJ5MD 0 R/W 2 PJ1MD 0 R/W 9 -- 0 R 1 -- 0 R 8 PJ4MD 0 R/W 0 PJ0MD 0 R/W * Bit 15--Reserved: This bit is always read as 0. The write value should always be 0. * Bit 14--PJ7 Mode Bit (PJ7MD): Selects the function of pin PJ7/TIO2H. Bit 14: PJ7MD 0 1 Description General input/output (PJ7) ATU-II input capture input/output compare output (TIO2H) (Initial value) * Bit 13--Reserved: This bit is always read as 0. The write value should always be 0. * Bit 12--PJ6 Mode Bit (PJ6MD): Selects the function of pin PJ6/TIO2G. Bit 12: PJ6MD 0 1 Description General input/output (PJ6) ATU-II input capture input/output compare output (TIO2G) (Initial value) Rev.2.0, 07/03, page 689 of 960 * Bit 11--Reserved: This bit is always read as 0. The write value should always be 0. * Bit 10--PJ5 Mode Bit (PJ5MD): Selects the function of pin PJ5/TIO2F. Bit 10: PJ5MD 0 1 Description General input/output (PJ5) ATU-II input capture input/output compare output (TIO2F) (Initial value) * Bit 9--Reserved: This bit is always read as 0. The write value should always be 0. * Bit 8--PJ4 Mode Bit (PJ4MD): Selects the function of pin PJ4/TIO2E. Bit 8: PJ4MD 0 1 Description General input/output (PJ4) ATU-II input capture input/output compare output (TIO2E) (Initial value) * Bit 7--Reserved: This bit is always read as 0. The write value should always be 0. * Bit 6--PJ3 Mode Bit (PJ3MD): Selects the function of pin PJ3/TIO2D. Bit 6: PJ3MD 0 1 Description General input/output (PJ3) ATU-II input capture input/output compare output (TIO2D) (Initial value) * Bit 5--Reserved: This bit is always read as 0. The write value should always be 0. * Bit 4--PJ2 Mode Bit (PJ2MD): Selects the function of pin PJ2/TIO2C. Bit 4: PJ2MD 0 1 Description General input/output (PJ2) ATU-II input capture input/output compare output (TIO2C) (Initial value) * Bit 3--Reserved: This bit is always read as 0. The write value should always be 0. * Bit 2--PJ1 Mode Bit (PJ1MD): Selects the function of pin PJ1/TIO2B. Bit 2: PJ1MD 0 1 Description General input/output (PJ1) ATU-II input capture input/output compare output (TIO2B) (Initial value) Rev.2.0, 07/03, page 690 of 960 * Bit 1--Reserved: This bit is always read as 0. The write value should always be 0. * Bit 0--PJ0 Mode Bit (PJ0MD): Selects the function of pin PJ0/TIO2A. Bit 0: PJ0MD 0 1 Description General input/output (PJ0) ATU-II input capture input/output compare output (TIO2A) (Initial value) 20.3.20 Port K IO Register (PKIOR) Bit: 15 PK15 IOR Initial value: R/W: Bit: 0 R/W 7 PK7 IOR Initial value: R/W: 0 R/W 14 PK14 IOR 0 R/W 6 PK6 IOR 0 R/W 13 PK13 IOR 0 R/W 5 PK5 IOR 0 R/W 12 PK12 IOR 0 R/W 4 PK4 IOR 0 R/W 11 PK11 IOR 0 R/W 3 PK3 IOR 0 R/W 10 PK10 IOR 0 R/W 2 PK2 IOR 0 R/W 9 PK9 IOR 0 R/W 1 PK1 IOR 0 R/W 8 PK8 IOR 0 R/W 0 PK0 IOR 0 R/W The port K IO register (PKIOR) is a 16-bit readable/writable register that selects the input/output direction of the 16 pins in port K. Bits PK15IOR to PK0IOR correspond to pins PK15/TO8P to PK0/TO8A. PKIOR is enabled when port K pins function as general input/output pins (PK15 to PK0), and disabled otherwise. When port K pins function as PK15 to PK0, a pin becomes an output when the corresponding bit in PKIOR is set to 1, and an input when the bit is cleared to 0. PKIOR is initialized to H'0000 by a power-on reset (excluding a WDT power-on reset), and in hardware standby mode. It is not initialized in software standby mode or sleep mode. 20.3.21 Port K Control Registers H and L (PKCRH, PKCRL) Port K control registers H and L (PKCRH, PKCRL) are 16-bit readable/writable registers that select the functions of the 16 multiplex pins in port K. PKCRH selects the functions of the pins for the upper 8 bits of port K, and PKCRL selects the functions of the pins for the lower 8 bits. PKCRH and PKCRL are initialized to H'0000 by a power-on reset (excluding a WDT power-on reset), and in hardware standby mode. They are not initialized in software standby mode or sleep mode. Rev.2.0, 07/03, page 691 of 960 Port K Control Register H (PKCRH) Bit: 15 -- Initial value: R/W: Bit: 0 R 7 -- Initial value: R/W: 0 R 14 PK15 MD 0 R/W 6 PK11 MD 0 R/W 13 -- 0 R 5 -- 0 R 12 PK14 MD 0 R/W 4 PK10 MD 0 R/W 11 -- 0 R 3 -- 0 R 10 PK13 MD 0 R/W 2 PK9 MD 0 R/W 9 -- 0 R 1 -- 0 R 8 PK12 MD 0 R/W 0 PK8 MD 0 R/W * Bit 15--Reserved: This bit is always read as 0. The write value should always be 0. * Bit 14--PK15 Mode Bit (PK15MD): Selects the function of pin PK15/TO8P. Bit 14: PK15MD 0 1 Description General input/output (PK15) ATU-II one-shot pulse output (TO8P) (Initial value) * Bit 13--Reserved: This bit is always read as 0. The write value should always be 0. * Bit 12--PK14 Mode Bit (PK14MD): Selects the function of pin PK14/TO8O. Bit 12: PK14MD 0 1 Description General input/output (PK14) ATU-II one-shot pulse output (TO8O) (Initial value) * Bit 11--Reserved: This bit is always read as 0. The write value should always be 0. * Bit 10--PK13 Mode Bit (PK13MD): Selects the function of pin PK13/TO8N. Bit 10: PK13MD 0 1 Description General input/output (PK13) ATU-II one-shot pulse output (TO8N) (Initial value) Rev.2.0, 07/03, page 692 of 960 * Bit 9--Reserved: This bit is always read as 0. The write value should always be 0. * Bit 8--PK12 Mode Bit (PK12MD): Selects the function of pin PK12/TO8M. Bit 8: PK12MD 0 1 Description General input/output (PK12) ATU-II one-shot pulse output (TO8M) (Initial value) * Bit 7--Reserved: This bit is always read as 0. The write value should always be 0. * Bit 6--PK11 Mode Bit (PK11MD): Selects the function of pin PK11/TO8L. Bit 6: PK11MD 0 1 Description General input/output (PK11) ATU-II one-shot pulse output (TO8L) (Initial value) * Bit 5--Reserved: This bit is always read as 0. The write value should always be 0. * Bit 4--PK10 Mode Bit (PK10MD): Selects the function of pin PK10/TO8K. Bit 4: PK10MD 0 1 Description General input/output (PK10) ATU-II one-shot pulse output (TO8K) (Initial value) * Bit 3--Reserved: This bit is always read as 0. The write value should always be 0. * Bit 2--PK9 Mode Bit (PK9MD): Selects the function of pin PK9/TO8J. Bit 2: PK9MD 0 1 Description General input/output (PK9) ATU-II one-shot pulse output (TO8J) (Initial value) * Bit 1--Reserved: This bit is always read as 0. The write value should always be 0. * Bit 0--PK8 Mode Bit (PK8MD): Selects the function of pin PK8/TO8I. Bit 0: PK8MD 0 1 Description General input/output (PK8) ATU-II one-shot pulse output (TO8I) (Initial value) Rev.2.0, 07/03, page 693 of 960 Port K Control Register L (PKCRL) Bit: 15 -- Initial value: R/W: Bit: 0 R 7 -- Initial value: R/W: 0 R 14 PK7MD 0 R/W 6 PK3MD 0 R/W 13 -- 0 R 5 -- 0 R 12 PK6MD 0 R/W 4 PK2MD 0 R/W 11 -- 0 R 3 -- 0 R 10 PK5MD 0 R/W 2 PK1MD 0 R/W 9 -- 0 R 1 -- 0 R 8 PK4MD 0 R/W 0 PK0MD 0 R/W * Bit 15--Reserved: This bit is always read as 0. The write value should always be 0. * Bit 14--PK7 Mode Bit (PK7MD): Selects the function of pin PK7/TO8H. Bit 14: PK7MD 0 1 Description General input/output (PK7) ATU-II one-shot pulse output (TO8H) (Initial value) * Bit 13--Reserved: This bit is always read as 0. The write value should always be 0. * Bit 12--PK6 Mode Bit (PK6MD): Selects the function of pin PK6/TO8G. Bit 12: PK6MD 0 1 Description General input/output (PK6) ATU-II one-shot pulse output (TO8G) (Initial value) * Bit 11--Reserved: This bit is always read as 0. The write value should always be 0. * Bit 10--PK5 Mode Bit (PK5MD): Selects the function of pin PK5/TO8F. Bit 10: PK5MD 0 1 Description General input/output (PK5) ATU-II one-shot pulse output (TO8F) (Initial value) Rev.2.0, 07/03, page 694 of 960 * Bit 9--Reserved: This bit is always read as 0. The write value should always be 0. * Bit 8--PK4 Mode Bit (PK4MD): Selects the function of pin PK4/TO8E. Bit 8: PK4MD 0 1 Description General input/output (PK4) ATU-II one-shot pulse output (TO8E) (Initial value) * Bit 7--Reserved: This bit is always read as 0. The write value should always be 0. * Bit 6--PK3 Mode Bit (PK3MD): Selects the function of pin PK3/TO8D. Bit 6: PK3MD 0 1 Description General input/output (PK3) ATU-II one-shot pulse output (TO8D) (Initial value) * Bit 5--Reserved: This bit is always read as 0. The write value should always be 0. * Bit 4--PK2 Mode Bit (PK2MD): Selects the function of pin PK2/TO8C. Bit 4: PK2MD 0 1 Description General input/output (PK2) ATU-II one-shot pulse output (TO8C) (Initial value) * Bit 3--Reserved: This bit is always read as 0. The write value should always be 0. * Bit 2--PK1 Mode Bit (PK1MD): Selects the function of pin PK1/TO8B. Bit 2: PK1MD 0 1 Description General input/output (PK1) ATU-II one-shot pulse output (TO8B) (Initial value) * Bit 1--Reserved: This bit is always read as 0. The write value should always be 0. * Bit 0--PK0 Mode Bit (PK0MD): Selects the function of pin PK0/TO8A. Bit 0: PK0MD 0 1 Description General input/output (PK0) ATU-II one-shot pulse output (TO8A) (Initial value) Rev.2.0, 07/03, page 695 of 960 20.3.22 Port K Invert Register (PKIR) Bit: 15 14 13 12 11 10 9 PK9IR 0 R/W 1 PK1IR 0 R/W 8 PK8IR 0 R/W 0 PK0IR 0 R/W PK15IR PK14IR PK13IR PK12IR PK11IR PK10IR Initial value: R/W: Bit: 0 R/W 7 PK7IR Initial value: R/W: 0 R/W 0 R/W 6 PK6IR 0 R/W 0 R/W 5 PK5IR 0 R/W 0 R/W 4 PK4IR 0 R/W 0 R/W 3 PK3IR 0 R/W 0 R/W 2 PK2IR 0 R/W The port K invert register (PKIR) is a 16-bit readable/writable register that sets the port K inversion function. Bits PK15IR to PK0IR correspond to pins PK15/TO8P to PK0/TO8A. PKIR is enabled when port K pins function as ATU-II outputs, and disabled otherwise. When port K pins function as ATU-II outputs, the value of a pin is inverted when the corresponding bit in PKIR is set to 1. PKIR is initialized to H'0000 by a power-on reset (excluding a WDT power-on reset), and in hardware standby mode. It is not initialized in software standby mode or sleep mode. PKnIR 0 1 n = 15 to 0 Description Value is not inverted Value is inverted (Initial value) Rev.2.0, 07/03, page 696 of 960 20.3.23 Port L IO Register (PLIOR) Bit: 15 -- Initial value: R/W: Bit: 0 R 7 PL7 IOR Initial value: R/W: 0 R/W 14 -- 0 R 6 PL6 IOR 0 R/W 13 PL13 IOR 0 R/W 5 PL5 IOR 0 R/W 12 PL12 IOR 0 R/W 4 PL4 IOR 0 R/W 11 PL11 IOR 0 R/W 3 PL3 IOR 0 R/W 10 PL10 IOR 0 R/W 2 PL2 IOR 0 R/W 9 PL9 IOR 0 R/W 1 PL1 IOR 0 R/W 8 PL8 IOR 0 R/W 0 PL0 IOR 0 R/W The port L IO register (PLIOR) is a 16-bit readable/writable register that selects the input/output direction of the 14 pins in port L. Bits PL13IOR to PL0IOR correspond to pins PL13/IRQOUT to PL0/TI10. PLIOR is enabled when port L pins function as general input/output pins (PL13 to PL0), timer input/output pins (TIO11A, TIO11B), or serial clock pins (SCK2, SCK3, SCK4), and disabled otherwise. When port L pins function as PL13 to PL0, TIO11A and TIO11B, or SCK2, SCK3, and SCK4, a pin becomes an output when the corresponding bit in PLIOR is set to 1, and an input when the bit is cleared to 0. PLIOR is initialized to H'0000 by a power-on reset (excluding a WDT power-on reset), and in hardware standby mode. It is not initialized in software standby mode or sleep mode. Rev.2.0, 07/03, page 697 of 960 20.3.24 Port L Control Registers H and L (PLCRH, PLCRL) Port L control registers H and L (PLCRH, PLCRL) are 16-bit readable/writable registers that select the functions of the 14 multiplex pins in port L. PLCRH selects the functions of the pins for the upper 6 bits of port L, and PLCRL selects the functions of the pins for the lower 8 bits. PLCRH and PLCRL are initialized to H'0000 by a power-on reset (excluding a WDT power-on reset), and in hardware standby mode. They are not initialized in software standby mode or sleep mode. Port L Control Register H (PLCRH) Bit: 15 -- Initial value: R/W: Bit: 0 R 7 PL11 MD1 Initial value: R/W: 0 R/W 14 -- 0 R 6 PL11 MD0 0 R/W 13 -- 0 R 5 PL10 MD1 0 R/W 12 -- 0 R 4 PL10 MD0 0 R/W 11 PL13 MD1 0 R/W 3 PL9 MD1 0 R/W 10 PL13 MD0 0 R/W 2 PL9 MD0 0 R/W 9 -- 0 R 1 -- 0 R 8 PL12 MD 0 R/W 0 PL8 MD 0 R/W * Bits 15 to 12--Reserved: These bits are always read as 0. The write value should always be 0. * Bits 11 and 10--PL13 Mode Bits 1 and 0 (PL13MD1, PL13MD0): These bits select the function of pin PL13/IRQOUT. Bit 11: PL13MD1 0 Bit 10: PL13MD0 0 1 1 0 1 Description General input/output (PL13) IRQOUT is fixed high (IRQOUT) IRQOUT is output by INTC interrupt request (IRQOUT) Reserved (Do not set) (Initial value) Rev.2.0, 07/03, page 698 of 960 * Bit 9--Reserved: This bit is always read as 0. The write value should always be 0. * Bit 8--PL12 Mode Bit (PL12MD): Selects the function of pin PL12/IRQ4. Bit 8: PL12MD 0 1 Description General input/output (PL12) Interrupt request input (IRQ4) (Initial value) * Bits 7 and 6--PL11 Mode Bits 1 and 0 (PL11MD1, PL11MD0): These bits select the function of pin PL11/HRxD0/HRxD1. Bit 7: PL11MD1 0 Bit 6: PL11MD0 0 1 1 0 1 Description General input/output (PL11) HCAN receive data input (HRxD0) HCAN receive data input (HRxD1) HCAN receive data input (both HRxD0 and HRxD1 input) (Initial value) * Bits 5 and 4--PL10 Mode Bits 1 and 0 (PL10MD1, PL10MD0): These bits select the function of pin PL10/HTxD0/HTxD1. Bit 5: PL10MD1 0 Bit 4: PL10MD0 0 1 1 0 1 Description General input/output (PL10) HCAN transmit data output (HTxD0) HCAN transmit data output (HTxD1) HCAN transmit data output (AND of HTxD0 and HTxD1) (Initial value) * Bits 3 and 2--PL9 Mode Bits 1 and 0 (PL9MD1, PL9MD0): These bits select the function of pin PL9/SCK4/IRQ5. Bit 3: PL9MD1 0 Bit 2: PL9MD0 0 1 1 0 1 Description General input/output (PL9) Serial clock input/output (SCK4) Interrupt request input (IRQ5) Reserved (Do not set) (Initial value) Rev.2.0, 07/03, page 699 of 960 * Bit 1--Reserved: This bit is always read as 0. The write value should always be 0. * Bit 0--PL8 Mode Bit (PL8MD): Selects the function of pin PL8/SCK3. Bit 0: PL8MD 0 1 Description General input/output (PL8) Serial clock input/output (SCK3) (Initial value) Port L Control Register L (PLCRL) Bit: 15 -- Initial value: R/W: Bit: 0 R 7 -- Initial value: R/W: 0 R 14 PL7MD 0 R/W 6 13 -- 0 R 5 12 PL6MD 0 R/W 4 11 -- 0 R 3 10 PL5MD 0 R/W 2 9 -- 0 R 1 -- 0 R 8 PL4MD 0 R/W 0 PL0MD 0 R/W PL3MD PL2MD1 PL2MD0 PL1MD1 PL1MD0 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W * Bit 15--Reserved: This bit is always read as 0. The write value should always be 0. * Bit 14--PL7 Mode Bit (PL7MD): Selects the function of pin PL7/SCK2. Bit 14: PL7MD 0 1 Description General input/output (PL7) Serial clock input/output (SCK2) (Initial value) * Bit 13--Reserved: This bit is always read as 0. The write value should always be 0. * Bit 12--PL6 Mode Bit (PL6MD): Selects the function of pin PL6/ADEND. Bit 12: PL6MD 0 1 Description General input/output (PL6) A/D conversion end output (ADEND) (Initial value) Rev.2.0, 07/03, page 700 of 960 * Bit 11--Reserved: This bit is always read as 0. The write value should always be 0. * Bit 10--PL5 Mode Bit (PL5MD): Selects the function of pin PL5/ADTRG1. Bit 10: PL5MD 0 1 Description General input/output (PL5) A/D conversion trigger input (ADTRG1) (Initial value) * Bit 9--Reserved: This bit is always read as 0. The write value should always be 0. * Bit 8--PL4 Mode Bit (PL4MD): Selects the function of pin PL4/ADTRG0. Bit 8: PL4MD 0 1 Description General input/output (PL4) A/D conversion trigger input (ADTRG0) (Initial value) * Bit 7--Reserved: This bit is always read as 0. The write value should always be 0. * Bit 6--PL3 Mode Bit (PL3MD): Selects the function of pin PL3/TCLKB. Bit 6: PL3MD 0 1 Description General input/output (PL3) ATU-II clock input (TCLKB) (Initial value) * Bits 5 and 4--PL2 Mode Bits 1 and 0 (PL2MD1, PL2MD0): These bits select the function of pin PL2/TIO11B/IRQ7. Bit 5: PL2MD1 0 Bit 4: PL2MD0 0 1 1 0 1 Description General input/output (PL2) (Initial value) ATU-II input capture input/output compare output (TIO11B) Interrupt request input (IRQ7) Reserved (Do not set) Rev.2.0, 07/03, page 701 of 960 * Bits 3 and 2--PL1 Mode Bits 1 and 0 (PL1MD1, PL1MD0): These bits select the function of pin PL1/TIO11A/IRQ6. Bit 3: PL1MD1 0 Bit 2: PL1MD0 0 1 1 0 1 Description General input/output (PL1) (Initial value) ATU-II input capture input/output compare output (TIO11A) Interrupt request input (IRQ6) Reserved (Do not set) * Bit 1--Reserved: This bit is always read as 0. The write value should always be 0. * Bit 0--PL0 Mode Bit (PL0MD): Selects the function of pin PL0/TI10. Bit 0: PL0MD 0 1 Description General input/output (PL0) ATU-II edge input (TI10) (Initial value) Rev.2.0, 07/03, page 702 of 960 20.3.25 Port L Invert Register (PLIR) Bit: 15 -- Initial value: R/W: Bit: 0 R 7 PL7IR Initial value: R/W: 0 R/W 14 -- 0 R 6 -- 0 R 13 -- 0 R 5 -- 0 R 12 -- 0 R 4 -- 0 R 11 -- 0 R 3 -- 0 R 10 -- 0 R 2 -- 0 R 9 PL9IR 0 R/W 1 -- 0 R 8 PL8IR 0 R/W 0 -- 0 R The port L invert register (PLIR) is a 16-bit readable/writable register that sets the port L inversion function. Bits PL9IR to PL7IR correspond to pins PL9/SCK4/IRQ5 to PL7/SCK2. PLIR is enabled when port L pins function as serial clock pins, and disabled otherwise. When port L pins function as serial clock pins, the value of a pin is inverted when the corresponding bit in PLIR is set to 1. PLIR is initialized to H'0000 by a power-on reset (excluding a WDT power-on reset), and in hardware standby mode. It is not initialized in software standby mode or sleep mode. PLnIR 0 1 n = 9 to 7 Description Value is not inverted Value is inverted (Initial value) Rev.2.0, 07/03, page 703 of 960 Rev.2.0, 07/03, page 704 of 960 Section 21 I/O Ports (I/O) 21.1 Overview The SH7055SF has 11 ports: A, B, C, D, E, F, G, H, I, J, K and L, all supporting both input and output. Ports A B, E, F, H, J and K are 16-bit ports, port C is a 5-bit port, ports D and L are 14-bit ports, and port G is a 4-bit port. All the port pins are multiplexed as general input/output pins and special function pins. The functions of the multiplex pins are selected by means of the pin function controller (PFC). Each port is provided with a data register for storing the pin data. Each of the ports A, B, D, J and L is provided with a port register to read the pin values. 21.2 Port A Port A is an input/output port with the 16 pins shown in figure 21.1. PA15 (I/O) /RxD0 (input) PA14 (I/O) /TxD0 (output) PA13 (I/O) /TIO5B (I/O) PA12 (I/O) /TIO5A (I/O) PA11 (I/O) /TIO4D (I/O) PA10 (I/O) /TIO4C (I/O) PA9 (I/O) /TIO4B (I/O) Port A PA8 (I/O) /TIO4A (I/O) PA7 (I/O) /TIO3D (I/O) PA6 (I/O) /TIO3C (I/O) PA5 (I/O) /TIO3B (I/O) PA4 (I/O) /TIO3A (I/O) PA3 (I/O) /TIOD (input) PA2 (I/O) /TIOC (input) PA1 (I/O) /TIOB (input) PA0 (I/O) /TIOA (input) Figure 21.1 Port A Rev.2.0, 07/03, page 705 of 960 21.2.1 Register Configuration The port A register configuration is shown in table 21.1. Table 21.1 Register Configuration Name Port A data register Port A port register Abbreviation PADR PAPR R/W R/W R Initial Value H'0000 port A pin values Address H'FFFFF726 H'FFFFF780 Access Size 8, 16 8, 16 Note: A register access is performed in four or five cycles regardless of the access size. 21.2.2 Port A Data Register (PADR) Bit: 15 PA15 DR Initial value: R/W: Bit: 0 R/W 7 PA7 DR Initial value: R/W: 0 R/W 14 PA14 DR 0 R/W 6 PA6 DR 0 R/W 13 PA13 DR 0 R/W 5 PA5 DR 0 R/W 12 PA12 DR 0 R/W 4 PA4 DR 0 R/W 11 PA11 DR 0 R/W 3 PA3 DR 0 R/W 10 PA10 DR 0 R/W 2 PA2 DR 0 R/W 9 PA9 DR 0 R/W 1 PA1 DR 0 R/W 8 PA8 DR 0 R/W 0 PA0 DR 0 R/W The port A data register (PADR) is a 16-bit readable/writable register that stores port A data. Bits PA15DR to PA0DR correspond to pins PA15/RxD0 to PA0/TI0A. When a pin functions as a general output, if a value is written to PADR, that value is output directly from the pin, and if PADR is read, the register value is returned directly regardless of the pin state. When a pin functions as a general input, if PADR is read the pin state, not the register value, is returned directly. If a value is written to PADR, although that value is written into PADR it does not affect the pin state. Table 21.2 summarizes port A data register read/write operations. PADR is initialized to H'0000 by a power-on reset (excluding a WDT power-on reset), and in hardware standby mode. It is not initialized in software standby mode or sleep mode. Rev.2.0, 07/03, page 706 of 960 Table 21.2 Port A Data Register (PADR) Read/Write Operations Bits 15 to 0: PAIOR 0 Pin Function General input Other than general input 1 General output Other than general output Read Pin state Pin state PADR value PADR value Write Value is written to PADR, but does not affect pin state Value is written to PADR, but does not affect pin state Write value is output from pin Value is written to PADR, but does not affect pin state 21.2.3 Port A Port Register (PAPR) Bit: 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 PA15 PA14 PA13 PA12 PA11 PA10 PA9 PA8 PA7 PA6 PA5 PA4 PA3 PA2 PA1 PA0 PR PR PR PR PR PR PR PR PR PR PR PR PR PR PR PR Initial value: R/W: * R * R * R * R * R * R * R * R * R * R * R * R * R * R * R * R Note: * The initial value is 1 when the PA15 to PA0 pins are high, and it is 0 when the pins are low. The port A port register (PAPR) is a 16-bit read-only register that always stores the value of the port A pins. The CPU cannot write data to this register. Bits PA15PR to PA0PR correspond to pins PA15/RxD0 to PA0/TI0A. If PAPR is read, the corresponding pin values are returned. * Bits 15 to 0: Port A15 to A0 Port Register (PA15PR to PA0PR) PA15PR to PA0PR 0 1 Description Low-level signals are output from or input to the PA15 to PA0 pins. High-level signals are output from or input to the PA15 to PA0 pins. Rev.2.0, 07/03, page 707 of 960 21.3 Port B Port B is an input/output port with the 16 pins shown in figure 21.2. PB15 (I/O) /PULS5 (output) /SCK2 (I/O) PB14 (I/O) /SCK1 (I/O) /TCLKB (input) /TI10 (input) PB13 (I/O) /SCK0 (I/O) PB12 (I/O) /TCLKA (input) / (output) PB11 (I/O) /RxD4 (input) /HRxD0 (input) /TO8H (output) PB10 (I/O) /TxD4 (output) /HTxD0 (output) /TO8G (output) PB9 (I/O) /RxD3 (input) /TO8F (output) Port B PB8 (I/O) /TxD3 (output) /TO8E (output) PB7 (I/O) /TO7D (output) /TO8D (output) PB6 (I/O) /TO7C (output) /TO8C (output) PB5 (I/O) /TO7B (output) /TO8B (output) PB4 (I/O) /TO7A (output) /TO8A (output) PB3 (I/O) /TO6D (output) PB2 (I/O) /TO6C (output) PB1 (I/O) /TO6B (output) PB0 (I/O) /TO6A (output) Figure 21.2 Port B 21.3.1 Register Configuration The port B register configuration is shown in table 21.3. Table 21.3 Register Configuration Name Port B data register Port B port register Abbreviation PBDR PBPR R/W R/W R Initial Value H'0000 Address H'FFFFF738 Access Size 8, 16 8, 16 port B pin valuesH'FFFFF782 Note: A register access is performed in four or five cycles regardless of the access size. Rev.2.0, 07/03, page 708 of 960 21.3.2 Port B Data Register (PBDR) Bit: 15 PB15 DR Initial value: R/W: Bit: 0 R/W 7 PB7 DR Initial value: R/W: 0 R/W 14 PB14 DR 0 R/W 6 PB6 DR 0 R/W 13 PB13 DR 0 R/W 5 PB5 DR 0 R/W 12 PB12 DR 0 R/W 4 PB4 DR 0 R/W 11 PB11 DR 0 R/W 3 PB3 DR 0 R/W 10 PB10 DR 0 R/W 2 PB2 DR 0 R/W 9 PB9 DR 0 R/W 1 PB1 DR 0 R/W 8 PB8 DR 0 R/W 0 PB0 DR 0 R/W The port B data register (PBDR) is a 16-bit readable/writable register that stores port B data. Bits PB15DR to PB0DR correspond to pins PB15/PULS5/SCK2 to PB0/TO6A. When a pin functions as a general output, if a value is written to PBDR, that value is output directly from the pin, and if PBDR is read, the register value is returned directly regardless of the pin state. When a pin functions as a general input, if PBDR is read the pin state, not the register value, is returned directly. If a value is written to PBDR, although that value is written into PBDR it does not affect the pin state. Table 21.4 summarizes port B data register read/write operations. PBDR is initialized to H'0000 by a power-on reset (excluding a WDT power-on reset), and in hardware standby mode. It is not initialized in software standby mode or sleep mode. Table 21.4 Port B Data Register (PBDR) Read/Write Operations Bits 15 to 0: PBIOR 0 Pin Function General input Other than general input 1 General output Other than general output Read Pin state Pin state PBDR value PBDR value Write Value is written to PBDR, but does not affect pin state Value is written to PBDR, but does not affect pin state Write value is output from pin Value is written to PBDR, but does not affect pin state Rev.2.0, 07/03, page 709 of 960 21.3.3 Port B Port Register (PBPR) Bit: 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 PB15 PB14 PB13 PB12 PB11 PB10 PB9 PB8 PB7 PB6 PB5 PB4 PB3 PB2 PB1 PB0 PR PR PR PR PR PR PR PR PR PR PR PR PR PR PR PR Initial value: R/W: * R * R * R * R * R * R * R * R * R * R * R * R * R * R * R * R Note: * The initial value is 1 when the PB15 to PB0 pins are high, and it is 0 when the pins are low. The port B port register (PBPR) is a 16-bit read-only register that always stores the value of the port B pins. The CPU cannot write data to this register. Bits PB15PR to PB0PR correspond to pins PB15/PULS5/SCK2 to PB0/TO6A. If PBPR is read, the corresponding pin values are returned. * Bits 15 to 0: Port B15 to B0 Port Register (PB15PR to PB0PR) PB15PR to PB0PR 0 1 Description Low-level signals are output from or input to the PB15 to PB0 pins. High-level signals are output from or input to the PB15 to PB0 pins. 21.4 Port C Port C is an input/output port with the 5 pins shown in figure 21.3. PC4 (I/O) / (input) PC3 (I/O) /RxD2 (input) Port C PC2 (I/O) /TxD2 (output) PC1 (I/O) /RxD1 (input) PC0 (I/O) /TxD1 (output) Figure 21.3 Port C 21.4.1 Register Configuration The port C register configuration is shown in table 21.5. Table 21.5 Register Configuration Name Port C data register Abbreviation PCDR R/W R/W Initial Value H'0000 Address H'FFFFF73E Access Size 8, 16 Note: A register access is performed in four or five cycles regardless of the access size. Rev.2.0, 07/03, page 710 of 960 21.4.2 Port C Data Register (PCDR) Bit: 15 -- Initial value: R/W: Bit: 0 R 7 -- Initial value: R/W: 0 R 14 -- 0 R 6 -- 0 R 13 -- 0 R 5 -- 0 R 12 -- 0 R 4 PC4 DR 0 R/W 11 -- 0 R 3 PC3 DR 0 R/W 10 -- 0 R 2 PC2 DR 0 R/W 9 -- 0 R 1 PC1 DR 0 R/W 8 -- 0 R 0 PC0 DR 0 R/W The port C data register (PCDR) is a 16-bit readable/writable register that stores port C data. Bits PC4DR to PC0DR correspond to pins PC4/IRQ0 to PC0/TxD1. When a pin functions as a general output, if a value is written to PCDR, that value is output directly from the pin, and if PCDR is read, the register value is returned directly regardless of the pin state. When a pin functions as a general input, if PCDR is read the pin state, not the register value, is returned directly. If a value is written to PCDR, although that value is written into PCDR it does not affect the pin state. Table 21.6 summarizes port C data register read/write operations. PCDR is initialized to H'0000 by a power-on reset (excluding a WDT power-on reset), and in hardware standby mode. It is not initialized in software standby mode or sleep mode. * Bits 15 to 5--Reserved: These bits always read 0. The write value should always be 0. Table 21.6 Port C Data Register (PCDR) Read/Write Operations Bits 4 to 0: PCIOR 0 Pin Function General input Other than general input 1 General output Other than general output Read Pin state Pin state PCDR value PCDR value Write Value is written to PCDR, but does not affect pin state Value is written to PCDR, but does not affect pin state Write value is output from pin Value is written to PCDR, but does not affect pin state Rev.2.0, 07/03, page 711 of 960 21.5 Port D Port D is an input/output port with the 14 pins shown in figure 21.4. PD13 (I/O) /PULS6 (output) / HTxD0 (output) /HTxD1 (output) PD12 (I/O) /PULS4 (output) PD11 (I/O) /PULS3 (output) PD10 (I/O) /PULS2 (output) PD9 (I/O) /PULS1 (output) PD8 (I/O) /PULS0 (output) Port D PD7 (I/O) /TIO1H (I/O) PD6 (I/O) /TIO1G (I/O) PD5 (I/O) /TIO1F (I/O) PD4 (I/O) /TIO1E (I/O) PD3 (I/O) /TIO1D (I/O) PD2 (I/O) /TIO1C (I/O) PD1 (I/O) /TIO1B (I/O) PD0 (I/O) /TIO1A (I/O) Figure 21.4 Port D 21.5.1 Register Configuration The port D register configuration is shown in table 21.7. Table 21.7 Register Configuration Name Port D data register Port D port register Abbreviation PDDR PDPR R/W R/W R Initial Value H'0000 port D pin values Address H'FFFFF746 H'FFFFF784 Access Size 8, 16 8, 16 Note: A register access is performed in four or five cycles regardless of the access size. Rev.2.0, 07/03, page 712 of 960 21.5.2 Port D Data Register (PDDR) Bit: 15 -- Initial value: R/W: Bit: 0 R 7 PD7 DR Initial value: R/W: 0 R/W 14 -- 0 R 6 PD6 DR 0 R/W 13 PD13 DR 0 R/W 5 PD5 DR 0 R/W 12 PD12 DR 0 R/W 4 PD4 DR 0 R/W 11 PD11 DR 0 R/W 3 PD3 DR 0 R/W 10 PD10 DR 0 R/W 2 PD2 DR 0 R/W 9 PD9 DR 0 R/W 1 PD1 DR 0 R/W 8 PD8 DR 0 R/W 0 PD0 DR 0 R/W The port D data register (PDDR) is a 16-bit readable/writable register that stores port D data. Bits PD13DR to PD0DR correspond to pins PD13/PULS6/HTxD0/HTxD1 to PD0/TIO1A. When a pin functions as a general output, if a value is written to PDDR, that value is output directly from the pin, and if PDDR is read, the register value is returned directly regardless of the pin state. When a pin functions as a general input, if PDDR is read the pin state, not the register value, is returned directly. If a value is written to PDDR, although that value is written into PDDR it does not affect the pin state. Table 21.8 summarizes port D data register read/write operations. PDDR is initialized to H'0000 by a power-on reset (excluding a WDT power-on reset), and in hardware standby mode. It is not initialized in software standby mode or sleep mode. * Bits 15 and 14-- Reserved: These bits always read 0. The write value should always be 0. Table 21.8 Port D Data Register (PDDR) Read/Write Operations Bits 13 to 0: PDIOR 0 Pin Function General input Other than general input 1 General output Other than general output Read Pin state Pin state PDDR value PDDR value Write Value is written to PDDR, but does not affect pin state Value is written to PDDR, but does not affect pin state Write value is output from pin Value is written to PDDR, but does not affect pin state Rev.2.0, 07/03, page 713 of 960 21.5.3 Port D Port Register (PDPR) Bit: 15 - 14 - 13 12 11 10 9 8 7 6 5 4 3 2 1 0 PD13 PD12 PD11 PD10 PD9 PD8 PD7 PD6 PD5 PD4 PD3 PD2 PD1 PD0 PR PR PR PR PR PR PR PR PR PR PR PR PR PR Initial value: R/W: 0 R 0 R * R * R * R * R * R * R * R * R * R * R * R * R * R * R Note: * The initial value is 1 when the PD13 to PD0 pins are high, and it is 0 when the pins are low. The port D port register (PDPR) is a 16-bit read-only register that always stores the value of the port D pins. The CPU cannot write data to this register. Bits PD13PR to PD0PR correspond to pins PD13/PULS6/HTxD0/HTxD1 to PD0/TIO1A. If PDPR is read, the corresponding pin values are returned. * Bits 15 and 14: Reserved: These bits are always read as 0. * Bits 13 to 0: Port D13 to D0 Port Register (PD13PR to PD0PR) PD13PR to PD0PR 0 1 Description Low-level signals are output from or input to the PD13 to PD0 pins. High-level signals are output from or input to the PD13 to PD0 pins. Rev.2.0, 07/03, page 714 of 960 21.6 Port E Port E is an input/output port with the 16 pins shown in figure 21.5. ROM disabled ROM enabled expansion mode expansion mode A15 (output) A14 (output) A13 (output) A12 (output) A11 (output) A10 (output) A9 (output) Port E A8 (output) A7 (output) A6 (output) A5 (output) A4 (output) A3 (output) A2 (output) A1 (output) A0 (output) PE15 (I/O) /A15 (output) PE14 (I/O) /A14 (output) PE13 (I/O) /A13 (output) PE12 (I/O) /A12 (output) PE11 (I/O) /A11 (output) PE10 (I/O) /A10 (output) PE9 (I/O) /A9 (output) PE8 (I/O) /A8 (output) PE7 (I/O) /A7 (output) PE6 (I/O) /A6 (output) PE5 (I/O) /A5 (output) PE4 (I/O) /A4 (output) PE3 (I/O) /A3 (output) PE2 (I/O) /A2 (output) PE1 (I/O) /A1 (output) PE0 (I/O) /A0 (output) Singlechip mode PE15 (I/O) PE14 (I/O) PE13 (I/O) PE12 (I/O) PE11 (I/O) PE10 (I/O) PE9 (I/O) PE8 (I/O) PE7 (I/O) PE6 (I/O) PE5 (I/O) PE4 (I/O) PE3 (I/O) PE2 (I/O) PE1 (I/O) PE0 (I/O) Figure 21.5 Port E 21.6.1 Register Configuration The port E register configuration is shown in table 21.9. Table 21.9 Register Configuration Name Port E data register Abbreviation PEDR R/W R/W Initial Value H'0000 Address H'FFFFF754 Access Size 8, 16 Note: A register access is performed in four or five cycles regardless of the access size. Rev.2.0, 07/03, page 715 of 960 21.6.2 Port E Data Register (PEDR) Bit: 15 PE15 DR Initial value: R/W: Bit: 0 R/W 7 PE7 DR Initial value: R/W: 0 R/W 14 PE14 DR 0 R/W 6 PE6 DR 0 R/W 13 PE13 DR 0 R/W 5 PE5 DR 0 R/W 12 PE12 DR 0 R/W 4 PE4 DR 0 R/W 11 PE11 DR 0 R/W 3 PE3 DR 0 R/W 10 PE10 DR 0 R/W 2 PE2 DR 0 R/W 9 PE9 DR 0 R/W 1 PE1 DR 0 R/W 8 PE8 DR 0 R/W 0 PE0 DR 0 R/W The port E data register (PEDR) is a 16-bit readable/writable register that stores port E data. Bits PE15DR to PE0DR correspond to pins PE15/A15 to PE0/A0. When a pin functions as a general output, if a value is written to PEDR, that value is output directly from the pin, and if PEDR is read, the register value is returned directly regardless of the pin state. When the POD pin is driven low, general outputs go to the high-impedance state regardless of the PEDR value. When the POD pin is driven high, the written value is output from the pin. When a pin functions as a general input, if PEDR is read the pin state, not the register value, is returned directly. If a value is written to PEDR, although that value is written into PEDR it does not affect the pin state. Table 21.10 summarizes port E data register read/write operations. PEDR is initialized to H'0000 by a power-on reset (excluding a WDT power-on reset), and in hardware standby mode. It is not initialized in software standby mode or sleep mode. Rev.2.0, 07/03, page 716 of 960 Table 21.10 Port E Data Register (PEDR) Read/Write Operations Bits 15 to 0: PEIOR 0 Pin Function General input Other than general input 1 General output Read Pin state Pin state PEDR value Write Value is written to PEDR, but does not affect pin state Value is written to PEDR, but does not affect pin state Write value is output from pin (POD pin = high) High impedance regardless of PEDR value (POD pin = low) Other than general output PEDR value Value is written to PEDR, but does not affect pin state Rev.2.0, 07/03, page 717 of 960 21.7 Port F Port F is an input/output port with the 16 pins shown in figure 21.6. ROM disabled ROM enabled expansion mode expansion mode PF15 (I/O) PF14 (I/O) PF13 (I/O) PF12 (I/O) PF11 (I/O) PF10 (I/O) PF9 (I/O) PF8 (I/O) Port F PF7 (I/O) PF6 (I/O) A21 (output) A20 (output) A19 (output) A18 (output) A17 (output) A16 (output) (input) (output) (output) (output) (output) (output) (output) (input) (output) (output) PF5 (I/O) /A21 (output) / (input) PF4 (I/O) /A20 (output) PF3 (I/O) /A19 (output) PF2 (I/O) /A18 (output) PF1 (I/O) /A17 (output) PF0 (I/O) /A16 (output) Singlechip mode PF15 (I/O) PF14 (I/O) PF13 (I/O) PF12 (I/O) PF11 (I/O) PF10 (I/O) PF9 (I/O) PF8 (I/O) PF7 (I/O) PF6 (I/O) PF5 (I/O) / (input) PF4 (I/O) PF3 (I/O) PF2 (I/O) PF1 (I/O) PF0 (I/O) Figure 21.6 Port F 21.7.1 Register Configuration The port F register configuration is shown in table 21.11. Table 21.11 Register Configuration Name Port F data register Abbreviation PFDR R/W R/W Initial Value H'0000 Address H'FFFFF74E Access Size 8, 16 Note: A register access is performed in four or five cycles regardless of the access size. Rev.2.0, 07/03, page 718 of 960 21.7.2 Port F Data Register (PFDR) Bit: 15 PF15 DR Initial value: R/W: Bit: 0 R/W 7 PF7 DR Initial value: R/W: 0 R/W 14 PF14 DR 0 R/W 6 PF6 DR 0 R/W 13 PF13 DR 0 R/W 5 PF5 DR 0 R/W 12 PF12 DR 0 R/W 4 PF4 DR 0 R/W 11 PF11 DR 0 R/W 3 PF3 DR 0 R/W 10 PF10 DR 0 R/W 2 PF2 DR 0 R/W 9 PF9 DR 0 R/W 1 PF1 DR 0 R/W 8 PF8 DR 0 R/W 0 PF0 DR 0 R/W The port F data register (PFDR) is a 16-bit readable/writable register that stores port F data. Bits PF15DR to PF0DR correspond to pins PF15/BREQ to PF0/A16. When a pin functions as a general output, if a value is written to PFDR, that value is output directly from the pin, and if PFDR is read, the register value is returned directly regardless of the pin state. For pins PF0 to PF4, when the POD pin is driven low, general outputs go to the highimpedance state regardless of the PFDR value. When the POD pin is driven high, the written value is output from the pin. When a pin functions as a general input, if PFDR is read the pin state, not the register value, is returned directly. If a value is written to PFDR, although that value is written into PFDR it does not affect the pin state. Table 21.12 summarizes port F data register read/write operations. PFDR is initialized to H'0000 by a power-on reset (excluding a WDT power-on reset), and in hardware standby mode. It is not initialized in software standby mode or sleep mode. Rev.2.0, 07/03, page 719 of 960 Table 21.12 Port F Data Register (PFDR) Read/Write Operations Bits 15 to 5: PFIOR 0 Pin Function General input Other than general input 1 General output Other than general output Read Pin state Pin state PFDR value PFDR value Write Value is written to PFDR, but does not affect pin state Value is written to PFDR, but does not affect pin state Write value is output from pin Value is written to PFDR, but does not affect pin state Bits 4-0: PFIOR 0 Pin Function General input Other than general input 1 General output Read Pin state Pin state PFDR value Write Value is written to PFDR, but does not affect pin state Value is written to PFDR, but does not affect pin state Write value is output from pin (POD pin = high) High impedance regardless of PFDR value (POD pin = low) Other than general output PFDR value Value is written to PFDR, but does not affect pin state 21.8 Port G Port G is an input/output port with the 4 pins shown in figure 21.7. PG3 (I/O) / Port G PG2 (I/O) / PG1 (I/O) / (input) / (input) (input) /ADEND (output) (input) PG0 (I/O) /PULS7 (output) /HRxD0 (input) /HRxD1 (input) Figure 21.7 Port G Rev.2.0, 07/03, page 720 of 960 21.8.1 Register Configuration The port G register configuration is shown in table 21.13. Table 21.13 Register Configuration Name Port G data register Abbreviation PGDR R/W R/W Initial Value H'0000 Address H'FFFFF764 Access Size 8, 16 Note: A register access is performed in four or five cycles regardless of the access size. 21.8.2 Port G Data Register (PGDR) Bit: 15 -- Initial value: R/W: Bit: 0 R 7 -- Initial value: R/W: 0 R 14 -- 0 R 6 -- 0 R 13 -- 0 R 5 -- 0 R 12 -- 0 R 4 -- 0 R 11 -- 0 R 3 PG3 DR 0 R/W 10 -- 0 R 2 PG2 DR 0 R/W 9 -- 0 R 1 PG1 DR 0 R/W 8 -- 0 R 0 PG0 DR 0 R/W The port G data register (PGDR) is a 16-bit readable/writable register that stores port G data. Bits PG3DR to PG0DR correspond to pins PG3/IRQ3/ADTRG0 to PG0/PULS7/HRxD0/HRxD1. When a pin functions as a general output, if a value is written to PGDR, that value is output directly from the pin, and if PGDR is read, the register value is returned directly regardless of the pin state. When a pin functions as a general input, if PGDR is read the pin state, not the register value, is returned directly. If a value is written to PGDR, although that value is written into PGDR it does not affect the pin state. Table 21.14 summarizes port G data register read/write operations. PGDR is initialized to H'0000 by a power-on reset (excluding a WDT power-on reset), and in hardware standby mode. It is not initialized in software standby mode or sleep mode. * Bits 15 to 4--Reserved: These bits always read 0. The write value should always be 0. Rev.2.0, 07/03, page 721 of 960 Table 21.14 Port G Data Register (PGDR) Read/Write Operations Bits 3 to 0: PGIOR 0 Pin Function General input Other than general input 1 General output Other than general output Read Pin state Pin state PGDR value PGDR value Write Value is written to PGDR, but does not affect pin state Value is written to PGDR, but does not affect pin state Write value is output from pin Value is written to PGDR, but does not affect pin state Rev.2.0, 07/03, page 722 of 960 21.9 Port H Port H is an input/output port with the 16 pins shown in figure 21.8. ROM enabled expansion (Area 0: 8 bits) (Area 0: 16 bits) mode ROM disabled expansion mode PH15 (I/O) / D15 (I/O) PH14 (I/O) / D14 (I/O) PH13 (I/O) / D13 (I/O) PH12 (I/O) / D12 (I/O) PH11 (I/O) / D11 (I/O) PH10 (I/O) / D10 (I/O) PH9 (I/O) / D9 (I/O) PH8 (I/O) / D8 (I/O) D7 (I/O) D6 (I/O) D5 (I/O) D4 (I/O) D3 (I/O) D2 (I/O) D1 (I/O) D0 (I/O) D15 (I/O) D14 (I/O) D13 (I/O) D12 (I/O) D11 (I/O) D10 (I/O) D9 (I/O) D8 (I/O) Singlechip mode PH15 (I/O) / PH15 (I/O) D15 (I/O) PH14 (I/O) / PH14 (I/O) D14 (I/O) PH13 (I/O) / PH13 (I/O) D13 (I/O) PH12 (I/O) / PH12 (I/O) D12 (I/O) PH11 (I/O) / PH11 (I/O) D11 (I/O) PH10 (I/O) / PH10 (I/O) D10 (I/O) PH9 (I/O) / D9 (I/O) PH8 (I/O) / D8 (I/O) PH7 (I/O) / D7 (I/O) PH6 (I/O) / D6 (I/O) PH5 (I/O) / D5 (I/O) PH4 (I/O) / D4 (I/O) PH3 (I/O) / D3 (I/O) PH2 (I/O) / D2 (I/O) PH1 (I/O) / D1 (I/O) PH0 (I/O) / D0 (I/O) PH9 (I/O) PH8 (I/O) PH7 (I/O) PH6 (I/O) PH5 (I/O) PH4 (I/O) PH3 (I/O) PH2 (I/O) PH1 (I/O) PH0 (I/O) Port H Figure 21.8 Port H Rev.2.0, 07/03, page 723 of 960 21.9.1 Register Configuration The port H register configuration is shown in table 21.15. Table 21.15 Register Configuration Name Port H data register Abbreviation PHDR R/W R/W Initial Value H'0000 Address H'FFFFF72C Access Size 8, 16 Note: A register access is performed in four or five cycles regardless of the access size. 21.9.2 Port H Data Register (PHDR) Bit: 15 PH15 DR Initial value: R/W: Bit: 0 R/W 7 PH7 DR Initial value: R/W: 0 R/W 14 PH14 DR 0 R/W 6 PH6 DR 0 R/W 13 PH13 DR 0 R/W 5 PH5 DR 0 R/W 12 PH12 DR 0 R/W 4 PH4 DR 0 R/W 11 PH11 DR 0 R/W 3 PH3 DR 0 R/W 10 PH10 DR 0 R/W 2 PH2 DR 0 R/W 9 PH9 DR 0 R/W 1 PH1 DR 0 R/W 8 PH8 DR 0 R/W 0 PH0 DR 0 R/W The port H data register (PHDR) is a 16-bit readable/writable register that stores port H data. Bits PH15DR to PH0DR correspond to pins PH15/D15 to PH0/D0. When a pin functions as a general output, if a value is written to PHDR, that value is output directly from the pin, and if PHDR is read, the register value is returned directly regardless of the pin state. When the POD pin is driven low, general outputs go to the high-impedance state regardless of the PHDR value. When the POD pin is driven high, the written value is output from the pin. When a pin functions as a general input, if PHDR is read the pin state, not the register value, is returned directly. If a value is written to PHDR, although that value is written into PHDR it does not affect the pin state. Table 21.16 summarizes port H data register read/write operations. PHDR is initialized to H'0000 by a power-on reset (excluding a WDT power-on reset), and in hardware standby mode. It is not initialized in software standby mode or sleep mode. Rev.2.0, 07/03, page 724 of 960 Table 21.16 Port H Data Register (PHDR) Read/Write Operations Bits 15 to 0: PHIOR 0 Pin Function General input Other than general input 1 General output Read Pin state Pin state PHDR value Write Value is written to PHDR, but does not affect pin state Value is written to PHDR, but does not affect pin state Write value is output from pin (POD pin = high) High impedance regardless of PHDR value (POD pin = low) Other than general output PHDR value Value is written to PHDR, but does not affect pin state 21.10 Port J Port J is an input/output port with the 16 pins shown in figure 21.9. PJ15 (I/O) /TI9F (input) PJ14 (I/O) /TI9E (input) PJ13 (I/O) /TI9D (input) PJ12 (I/O) /TI9C (input) PJ11 (I/O) /TI9B (input) PJ10 (I/O) /TI9A (input) PJ9 (I/O) /TIO5D (I/O) Port J PJ8 (I/O) /TIO5C (I/O) PJ7 (I/O) /TIO2H (I/O) PJ6 (I/O) /TIO2G (I/O) PJ5 (I/O) /TIO2F (I/O) PJ4 (I/O) /TIO2E (I/O) PJ3 (I/O) /TIO2D (I/O) PJ2 (I/O) /TIO2C (I/O) PJ1 (I/O) /TIO2B (I/O) PJ0 (I/O) /TIO2A (I/O) Figure 21.9 Port J Rev.2.0, 07/03, page 725 of 960 21.10.1 Register Configuration The port J register configuration is shown in table 21.17. Table 21.17 Register Configuration Name Port J data register Port J port register Abbreviation PJDR PJPR R/W R/W R Initial Value H'0000 port J pin values Address H'FFFFF76C H'FFFFF786 Access Size 8, 16 8, 16 Note: A register access is performed in four or five cycles regardless of the access size. 21.10.2 Port J Data Register (PJDR) Bit: 15 PJ15 DR Initial value: R/W: Bit: 0 R/W 7 PJ7 DR Initial value: R/W: 0 R/W 14 PJ14 DR 0 R/W 6 PJ6 DR 0 R/W 13 PJ13 DR 0 R/W 5 PJ5 DR 0 R/W 12 PJ12 DR 0 R/W 4 PJ4 DR 0 R/W 11 PJ11 DR 0 R/W 3 PJ3 DR 0 R/W 10 PJ10 DR 0 R/W 2 PJ2 DR 0 R/W 9 PJ9 DR 0 R/W 1 PJ1 DR 0 R/W 8 PJ8 DR 0 R/W 0 PJ0 DR 0 R/W The port J data register (PJDR) is a 16-bit readable/writable register that stores port J data. Bits PJ15DR to PJ0DR correspond to pins PJ15/TI9F to PJ0/TIO2A. When a pin functions as a general output, if a value is written to PJDR, that value is output directly from the pin, and if PJDR is read, the register value is returned directly regardless of the pin state. When a pin functions as a general input, if PJDR is read the pin state, not the register value, is returned directly. If a value is written to PJDR, although that value is written into PJDR it does not affect the pin state. Table 21.18 summarizes port J data register read/write operations. PJDR is initialized to H'0000 by a power-on reset (excluding a WDT power-on reset), and in hardware standby mode. It is not initialized in software standby mode or sleep mode. Rev.2.0, 07/03, page 726 of 960 Table 21.18 Port J Data Register (PJDR) Read/Write Operations Bits 15 to 0: PJIOR 0 Pin Function General input Other than general input 1 General output Other than general output Read Pin state Pin state PJDR value PJDR value Write Value is written to PJDR, but does not affect pin state Value is written to PJDR, but does not affect pin state Write value is output from pin Value is written to PJDR, but does not affect pin state 21.10.3 Port J Port Register (PJPR) Bit: 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 PJ15 PJ14 PJ13 PJ12 PJ11 PJ10 PJ9 PJ8 PJ7 PJ6 PJ5 PJ4 PJ3 PJ2 PJ1 PJ0 PR PR PR PR PR PR PR PR PR PR PR PR PR PR PR PR Initial value: R/W: * R * R * R * R * R * R * R * R * R * R * R * R * R * R * R * R Note: * The initial value is 1 when the PJ15 to PJ0 pins are high, and it is 0 when the pins are low. The port J port register (PJPR) is a 16-bit read-only register that always stores the value of the port J pins. The CPU cannot write data to this register. Bits PJ15PR to PJ0PR correspond to pins PJ15/TI9F to PJ0/TIO2A. If PJPR is read, the corresponding pin values are returned. * Bits 15 to 0: Port J15 to J0 Port Register (PJ15PR to PJ0PR) PJ15PR to PJ0PR 0 1 Description Low-level signals are output from or input to the PJ15 to PJ0 pins. High-level signals are output from or input to the PJ15 to PJ0 pins. Rev.2.0, 07/03, page 727 of 960 21.11 Port K Port K is an input/output port with the 16 pins shown in figure 21.10. PK15 (I/O) /TO8P (output) PK14 (I/O) /TO8O (output) PK13 (I/O) /TO8N (output) PK12 (I/O) /TO8M (output) PK11 (I/O) /TO8L (output) PK10 (I/O) /TO8K (output) PK9 (I/O) /TO8J (output) Port K PK8 (I/O) /TO8I (output) PK7 (I/O) /TO8H (output) PK6 (I/O) /TO8G (output) PK5 (I/O) /TO8F (output) PK4 (I/O) /TO8E (output) PK3 (I/O) /TO8D (output) PK2 (I/O) /TO8C (output) PK1 (I/O) /TO8B (output) PK0 (I/O) /TO8A (output) Figure 21.10 Port K 21.11.1 Register Configuration The port K register configuration is shown in table 21.19. Table 21.19 Register Configuration Name Port K data register Abbreviation PKDR R/W R/W Initial Value H'0000 Address H'FFFFF778 Access Size 8, 16 Note: A register access is performed in four or five cycles regardless of the access size. Rev.2.0, 07/03, page 728 of 960 21.11.2 Port K Data Register (PKDR) Bit: 15 PK15 DR Initial value: R/W: Bit: 0 R/W 7 PK7 DR Initial value: R/W: 0 R/W 14 PK14 DR 0 R/W 6 PK6 DR 0 R/W 13 PK13 DR 0 R/W 5 PK5 DR 0 R/W 12 PK12 DR 0 R/W 4 PK4 DR 0 R/W 11 PK11 DR 0 R/W 3 PK3 DR 0 R/W 10 PK10 DR 0 R/W 2 PK2 DR 0 R/W 9 PK9 DR 0 R/W 1 PK1 DR 0 R/W 8 PK8 DR 0 R/W 0 PK0 DR 0 R/W The port K data register (PKDR) is a 16-bit readable/writable register that stores port K data. Bits PK15DR to PK0DR correspond to pins PK15/TO8P to PK0/TO8A. When a pin functions as a general output, if a value is written to PKDR, that value is output directly from the pin, and if PKDR is read, the register value is returned directly regardless of the pin state. When a pin functions as a general input, if PKDR is read the pin state, not the register value, is returned directly. If a value is written to PKDR, although that value is written into PKDR it does not affect the pin state. Table 21.20 summarizes port K data register read/write operations. PKDR is initialized to H'0000 by a power-on reset (excluding a WDT power-on reset), and in hardware standby mode. It is not initialized in software standby mode or sleep mode. Table 21.20 Port K Data Register (PKDR) Read/Write Operations Bits 15 to 0: PKIOR 0 Pin Function General input Other than general input 1 General output Other than general output Read Pin state Pin state PKDR value PKDR value Write Value is written to PKDR, but does not affect pin state Value is written to PKDR, but does not affect pin state Write value is output from pin Value is written to PKDR, but does not affect pin state Rev.2.0, 07/03, page 729 of 960 21.12 Port L Port L is an input/output port with the 14 pins shown in figure 21.11. PL13 (I/O) / PL12 (I/O) / (output) (input) PL11 (I/O) /HRxD0 (input) /HRxD1 (input) PL10 (I/O) /HTxD0 (output) /HTxD1 (output) PL9 (I/O) /SCK4 (I/O) / PL8 (I/O) /SCK3 (I/O) Port L PL7 (I/O) /SCK2 (I/O) PL6 (I/O) /ADEND (output) PL5 (I/O) / PL4 (I/O) / (input) (input) (input) PL3 (I/O) /TCLKB (I/O) PL2 (I/O) /TIO11B (I/O) / PL1 (I/O) /TIO11A (I/O) / PL0 (I/O) /TI10 (input) (input) (input) Figure 21.11 Port L 21.12.1 Register Configuration The port L register configuration is shown in table 21.21. Table 21.21 Register Configuration Name Port L data register Port L port register Abbreviation PLDR PLPR R/W R/W R Initial Value H'0000 port L pin values Address H'FFFFF75E H'FFFFF788 Access Size 8, 16 8, 16 Note: A register access is performed in four or five cycles regardless of the access size. Rev.2.0, 07/03, page 730 of 960 21.12.2 Port L Data Register (PLDR) Bit: 15 -- Initial value: R/W: Bit: 0 R 7 PL7 DR Initial value: R/W: 0 R/W 14 -- 0 R 6 PL6 DR 0 R/W 13 PL13 DR 0 R/W 5 PL5 DR 0 R/W 12 PL12 DR 0 R/W 4 PL4 DR 0 R/W 11 PL11 DR 0 R/W 3 PL3 DR 0 R/W 10 PL10 DR 0 R/W 2 PL2 DR 0 R/W 9 PL9 DR 0 R/W 1 PL1 DR 0 R/W 8 PL8 DR 0 R/W 0 PL0 DR 0 R/W The port L data register (PLDR) is a 16-bit readable/writable register that stores port L data. Bits PL13DR to PL0DR correspond to pins PL13/IRQOUT to PL0/TI10. When a pin functions as a general output, if a value is written to PLDR, that value is output directly from the pin, and if PLDR is read, the register value is returned directly regardless of the pin state. When a pin functions as a general input, if PLDR is read the pin state, not the register value, is returned directly. If a value is written to PLDR, although that value is written into PLDR it does not affect the pin state. Table 21.22 summarizes port L data register read/write operations. PLDR is initialized to H'0000 by a power-on reset (excluding a WDT power-on reset), and in hardware standby mode. It is not initialized in software standby mode or sleep mode. * Bits 15 and 14--Reserved: These bits always read 0. The write value should always be 0. Table 21.22 Port L Data Register (PLDR) Read/Write Operations Bits 13 to 0: PLIOR 0 Pin Function General input Other than general input 1 General output Other than general output Read Pin state Pin state PLDR value PLDR value Write Value is written to PLDR, but does not affect pin state Value is written to PLDR, but does not affect pin state Write value is output from pin Value is written to PLDR, but does not affect pin state Rev.2.0, 07/03, page 731 of 960 21.12.3 Port L Port Register (PLPR) Bit: 15 - 14 - 13 12 11 10 9 8 7 6 5 4 3 2 1 0 PL13 PL12 PL11 PL10 PL9 PL8 PL7 PL6 PL5 PL4 PL3 PL2 PL1 PL0 PR PR PR PR PR PR PR PR PR PR PR PR PR PR Initial value: R/W: 0 R 0 R * R * R * R * R * R * R * R * R * R * R * R * R * R * R Note: * The initial value is 1 when the PL13 to PL0 pins are high, and it is 0 when the pins are low. The port L port register (PLPR) is a 16-bit read-only register that always stores the value of the port L pins. The CPU cannot write data to this register. Bits PL13PR to PL0PR correspond to pins PL13/IRQOUT to PL0/TI10. If PLPR is read, the corresponding pin values are returned. * Bits 15 and 14: Reserved: These bits are always read as 0. * Bits 13 to 0: Port L13 to L0 Port Register (PL13PR to PL0PR) PL13PR to PL0PR 0 1 Description Low-level signals are output from or input to the PL13 to PL0 pins. High-level signals are output from or input to the PL13 to PL0 pins. 21.13 POD (Port Output Disable) Control The output port drive buffers for the address bus pins (A20 to A0) and data bus pins (D15 to D0) can be controlled by the POD (port output disable) pin input level. However, this function is enabled only when the address bus pins (A20 to A0) and data bus pins (D15 to D0) are designated as general output ports. Output buffer control by means of POD is performed asynchronously from bus cycles. POD 0 1 Address Bus Pins (A20 to A0) and Data Bus Pins (D15 to D0) (when designated as output ports) Enabled (high-impedance) Disabled (general output) Rev.2.0, 07/03, page 732 of 960 21.14 Usage Notes (1) Table 21.23 lists the differences between the SH7055F and the SH7055SF. Table 21.23 Differences between the SH7055F and the SH7055SF Item PFC SH7055F SH7055SF Notes Bits 7, 5, 3 and 1 of These bits are read These bits are read Only 0 should be as 1 after 1 is written to these PACRL: Reserved as 0 after 1 is written. See bits. written. 20.3.2(2). PAPR PBPR PDPR PJPR PLPR - If a port registers is read, the pin values are always returned regardless of the setting of other registers. See sections 21.2.3, 21.3.3, 21.5.3, 21.10.3, 21.12.3. VIH: PVcc2x0.7V(min) VIL: PVcc2x0.3V(max) See section 25.4. The pin values can be read from the port registers when the I/O pins of the ATU-II and SCI are designated as outputs.* I/O ports Electrical Characteristics DC Characteristics VIH: 2.2V(min) PG0,PL11 VIL: 0.8V(max) HCAN port characteristics Note: * The pin values cannot be read from the data registers. (2) When port pins do not function as I/O pins, the input/output direction of the pins is selected by the port control registers. (For the PJ15 to 10 pins and PA4 to PA0 pins, the IO register must also be specified.) Rev.2.0, 07/03, page 733 of 960 Rev.2.0, 07/03, page 734 of 960 Section 22 ROM 22.1 Features This LSI has 512-kbyte on-chip flash memory. The flash memory has the following features. * Two flash-memory MATs according to LSI initiation mode The on-chip flash memory has two memory spaces in the same address space (hereafter referred to as memory MATs). The mode setting in the initiation determines which memory MAT is initiated first. The MAT can be switched by using the bank-switching method after initiation. The user MAT is initiated at a power-on reset in user mode: 512 kbytes The user boot MAT is initiated at a power-on reset in user boot mode: 8 kbytes * Three on-board programming modes and one off-board programming mode On-board programming modes Boot Mode: This mode is a program mode that uses an on-chip SCI interface. The user MAT and user boot MAT can be programmed. This mode can automatically adjust the bit rate between the host and this LSI. User Program Mode: The user MAT can be programmed by using the optional interface. User Boot Mode: The user boot program of the optional interface can be made and the user MAT can be programmed. Off-board programming mode Programmer Mode: This mode uses the PROM programmer. The user MAT and user boot MAT can be programmed. * Programming/erasing interface by the download of on-chip program This LSI has a dedicated programming/erasing program. After downloading this program to the on-chip RAM, programming/erasing can be performed by setting the argument parameter. The user branch is also supported. User branch The program processing is performed in 128-byte units. It consists the program pulse application, verify read, and several other steps. Erasing is performed in one divided-block units and consists of several steps. The user processing routine can be executed between the steps, this setting for which is called the user branch addition. * Emulation function of flash memory by using the on-chip RAM As flash memory is overlapped with part of the on-chip RAM, the flash memory programming can be emulated in real time. * Protection modes There are two protection modes. Software protection by the register setting and hardware protection by the FWE pin. The protection state for flash memory programming/erasing can be set. Rev.2.0, 07/03, page 735 of 960 When abnormalities, such as runaway of programming/erasing are detected, these modes enter the error protection state and the programming/erasing processing is suspended. * Programming/erasing time The flash memory programming time is tP ms (typ) in 128-byte simultaneous programming and tP/128 ms per byte. The erasing time is tE s (typ) per block. * Number of programming The number of flash memory programming can be up to NWEC times. Rev.2.0, 07/03, page 736 of 960 22.2 22.2.1 Overview Block Diagram Internal address bus Internal data bus (32 bits) FCCS FPCS Module bus FECS FKEY FMATS FTDAR RAMER Flash memory Control unit Memory MAT unit User MAT: 512 kbytes User boot MAT: 8 kbytes FWE pin Mode pins Operating mode Legend FCCS: FPCS: FECS: FKEY: FMATS: FTDAR: RAMER: Flash code control and status register Flash program code select register Flash erase code select register Flash key code register Flash MAT select register Flash transfer destination address register RAM emulation register Figure 22.1 Block Diagram of Flash Memory Rev.2.0, 07/03, page 737 of 960 22.2.2 Operating Mode When each mode pin and the FWE pin are set in the reset state and the reset signal is released, the microcomputer enters each operating mode as shown in figure 22.2. For the setting of each mode pin and the FWE pin, see table 22.1. * Flash memory cannot be read, programmed, or erased in ROM invalid mode. The programming/erasing interface registers cannot be written to. When these registers are read, H'00 is always read. * Flash memory can be read in user mode, but cannot be programmed or erased. * Flash memory can be read, programmed, or erased on the board only in user program mode, user boot mode, and boot mode. * Flash memory can be read, programmed, or erased by means of the PROM programmer in programmer mode. ROM invalid mode =0 =0 Reset state ROM invalid mode setting Programmer mode setting Programmer mode e Us o rm progra m settin mode g =0 de se ttin g Bo ot mo =0 de se ttin g = ting set de mo oot er b Us 0 =0 FWE=0 FWE=1 User User mode Boot mode User program mode RAM emulation is enabled User boot mode On-board programming mode Figure 22.2 Mode Transition of Flash Memory Rev.2.0, 07/03, page 738 of 960 Table 22.1 Relationship between FWE and MD Pins and Operating Modes Mode Reset State 0 0/1 0/1 0/1 0/1 ROM Invalid Mode 1 0 0/1* 0 1 1 Pin RES FWE MD0 MD1 MD2 ROM Valid Mode 1 0 0/1* 1 1 2 User Program Mode 1 1 0/1* 1 1 2 User Boot Mode 1 1 0/1* 0 0 2 Boot Mode 1 1 0/1* 0 1 2 Programmer Mode 1 0/1 1 1 0 Notes: *1 MD0 = 0: 8-bit external bus, MD0 = 1: 16-bit external bus *2 MD0 = 0: External bus can be used, MD0 = 1: Single-chip mode (external bus cannot be used) 22.2.3 Mode Comparison The comparison table of programming and erasing related items about boot mode, user program mode, user boot mode, and programmer mode is shown in table 22.2. Rev.2.0, 07/03, page 739 of 960 Table 22.2 Comparison of Programming Modes Boot Mode Programming/ erasing environment Programming/ erasing enable MAT Programming/ erasing control All erasure Block division erasure Program data transfer User branch function RAM emulation Reset initiation MAT Transition to user mode On-board programming User MAT User boot MAT Command method O (Automatic) O* 1 User Program Mode On-board programming User MAT User Boot Mode On-board programming User MAT Programmer Mode Off-board programming User MAT User boot MAT Command method O (Automatic) X Via programmer X X Programming/ erasing interface O O From optional device via RAM O O User MAT Programming/ erasing interface O O From optional device via RAM O X User boot MAT* 2 From host via SCI X X Embedded program storage MAT Mode setting change and reset Embedded program storage MAT -- FWE setting change Mode setting change and reset Notes: *1 All-erasure is performed. After that, the specified block can be erased. *2 Initiation starts from the embedded program storage MAT. After checking the flashmemory related registers, initiation starts from the reset vector of the user MAT. * The user boot MAT can be programmed or erased only in boot mode and programmer mode. * The user MAT and user boot MAT are all erased in boot mode. Then, the user MAT and user boot MAT can be programmed by means of the command method. However, the contents of the MAT cannot be read until this state. Only user boot MAT is programmed and the user MAT is programmed in user boot mode or only user MAT is programmed because user boot mode is not used. * In user boot mode, the boot operation of the optional interface can be performed by a mode pin setting different from user program mode. Rev.2.0, 07/03, page 740 of 960 22.2.4 Flash Memory Configuration This LSI's flash memory is configured by the 512-kbyte user MAT and 8-kbyte user boot MAT. The start address is allocated to the same address in the user MAT and user boot MAT. Therefore, when the program execution or data access is performed between the two MATs, the MAT must be switched by using FMATS. The user MAT is divided into two 512-kbyte banks (bank 0 and bank 1). The user MAT or user boot MAT can be read in all modes if it is in ROM valid mode. However, the user boot MAT can be programmed only in boot mode and programmer mode. Address H'00,0000 Address H'00,1FFF Address H'07,FFFF Figure 22.3 Flash Memory Configuration The user MAT and user boot MAT have different memory sizes. Do not access a user boot MAT that is 8 kbytes or more. When a user boot MAT exceeding 8 kbytes is read from, an undefined value is read. 512 kbytes Rev.2.0, 07/03, page 741 of 960 22.2.5 Block Division The user MAT is divided into 64 kbytes (seven blocks), 32 kbytes (one block), and 4 kbytes (eight blocks) as shown in figure 22.4. The user MAT can be erased in this divided-block units and the erase-block number of EB0 to EB15 is specified when erasing. The RAM emulation can be performed in the eight blocks of 4 kbytes. 64kB EB9 64kB EB10 512kB 64kB EB11 64kB EB12 64kB EB13 64kB EB14 64kB Address H'07,FFFF EB15 Note: * RAM emulation can be performed in the eight blocks of 4 kbytes. Figure 22.4 Block Division of User MAT Rev.2.0, 07/03, page 742 of 960 22.2.6 Programming/Erasing Interface Programming/erasing is executed by downloading the on-chip program to the on-chip RAM and specifying the program address/data and erase block by using the interface registers/parameters. The procedure program is made by the user in user program mode and user boot mode. The overview of the procedure is as follows. For details, see section 22.5.2, User Program Mode. Start user procedure program for programming/erasing. Select on-chip program to be downloaded and set download destination Download on-chip program by setting VBR, FKEY, and SCO bits. Initialization execution (on-chip program execution) Programming (in 128-byte units) or erasing (in one-block units) (on-chip program execution) No Programming/ erasing completed? Yes End user procedure program Figure 22.5 Overview of User Procedure Program (1) Selection of On-Chip Program to be Downloaded and Setting of Download Destination This LSI has programming/erasing programs and they can be downloaded to the on-chip RAM. The on-chip program to be downloaded is selected by setting the corresponding bits in the programming/erasing interface registers. The download destination can be specified by FTDAR. Rev.2.0, 07/03, page 743 of 960 (2) Download of On-Chip Program The on-chip program is automatically downloaded by clearing VBR of the CPU to H'00000000 and then setting the SCO bit in the flash key code register (FKEY) and the flash code control and status register (FCCS), which are programming/erasing interface registers. The user MAT is replaced to the embedded program storage area when downloading. Since the flash memory cannot be read when programming/erasing, the procedure program, which is working from download to completion of programming/erasing, must be executed in a space other than the flash memory to be programmed/erased (for example, on-chip RAM). Since the result of download is returned to the programming/erasing interface parameters, whether the normal download is executed or not can be confirmed. Note that VBR can be changed after download is completed. (3) Initialization of Programming/Erasing The operating frequency and user branch are set before execution of programming/erasing. The user branch destination must be in an area other than the on-chip flash memory area and the area where the on-chip program is downloaded. These settings are performed by using the programming/erasing interface parameters. (4) Programming/Erasing Execution To program or erase, the FWE pin must be brought high and user program mode must be entered. The program data/programming destination address is specified in 128-byte units when programming. The block to be erased is specified in a erase-block unit when erasing. These specifications are set by using the programming/erasing interface parameters and the onchip program is initiated. The on-chip program is executed by using the JSR or BSR instruction to perform the subroutine call of the specified address in the on-chip RAM. The execution result is returned to the programming/erasing interface parameters. The area to be programmed must be erased in advance when programming flash memory. There are limitations and notes on the interrupt processing during programming/erasing. For details, see section 22.8.2, Interrupts during Programming/Erasing. (5) When Programming/Erasing is Executed Consecutively When the processing is not ended by the 128-byte programming or one-block erasure, the program address/data and erase-block number must be updated and consecutive programming/erasing is required. Since the downloaded on-chip program is left in the on-chip RAM after the processing, download and initialization are not required when the same processing is executed consecutively. Rev.2.0, 07/03, page 744 of 960 22.3 Pin Configuration Flash memory is controlled by the pins as shown in table 22.3. Table 22.3 Pin Configuration Pin Name Power-on reset Flash programming enable Mode 2 Mode 1 Mode 0 Transmit data Receive data Abbreviation RES FWE MD2 MD1 MD0 TxD1 RxD1 Input/Output Input Input Input Input Input Output Input Function Reset Hardware protection when programming flash memory Sets operating mode of this LSI Sets operating mode of this LSI Sets operating mode of this LSI Serial transmit data output (used in boot mode) Serial receive data input (used in boot mode) Note: For the pin configuration in programmer mode, see section 22.9, Programmer Mode. Rev.2.0, 07/03, page 745 of 960 22.4 22.4.1 Register Configuration Registers The registers/parameters which control flash memory when the on-chip flash memory is valid are shown in table 22.4. There are several operating modes for accessing flash memory, for example, read mode/program mode. There are two memory MATs: user MAT and user boot MAT. The dedicated registers/parameters are allocated for each operating mode and MAT selection. The correspondence of operating modes and registers/parameters for use is shown in table 22.5. Table 22.4 (1) Name Flash code control status register Flash program code select register Flash erase code select register Flash key code register Flash MAT select register Flash transfer destination address register RAM emulation register Register Configuration Abbreviation FCCS FPCS FECS FKEY FMATS FTDAR RAMER R/W R, W* R/W R/W R/W R/W R/W R/W 1 Initial Value H'00* 2 H'80* H'00 H'00 H'00 H'00* 3 H'AA* H'00 H'0000 3 2 Address H'FFFFE800 H'FFFFE801 H'FFFFE802 H'FFFFE804 H'FFFFE805 H'FFFFE806 H'FFFFEC26 Access Size 8 8 8 8 8 8 8, 16 Notes: All registers except for RAMER can be accessed only in bytes, and the access requires three cycles. RAMER can be accessed in bytes or words, and the access requires three cycles. *1 The bits except the SCO bit are read-only bits. The SCO bit is a programming-only bit. (The value which can be read is always 0.) *2 The initial value is H'00 when the FWE pin goes low. The initial value is H'80 when the FWE pin goes high. *3 The initial value at initiation in user mode or user program mode is H'00. The initial value at initiation in user boot mode is H'AA. Rev.2.0, 07/03, page 746 of 960 Table 22.4 (2) Name Parameter Configuration Abbreviation DPFR FPFR FMPAR FMPDR FEBS FPEFEQ FUBRA R/W R/W R/W R/W R/W R/W R/W R/W Initial Value Undefined Undefined Undefined Undefined Undefined Undefined Undefined Address On-chip RAM* R0 of CPU R5 of CPU R4 of CPU R4 of CPU R4 of CPU R5 of CPU Access Size 8, 16, 32 8, 16, 32 8, 16, 32 8, 16, 32 8, 16, 32 8, 16, 32 8, 16, 32 Download pass/fail result Flash pass/fail result Flash multipurpose address area Flash multipurpose data destination area Flash erase block select Flash program and erase frequency control Flash user branch address set parameter Note: * One byte of the start address in the on-chip RAM area specified by FTDAR is valid. Rev.2.0, 07/03, page 747 of 960 Table 22.5 Register/Parameter and Target Mode Download Programming/ erasing interface registers FCCS FPCS PECS FKEY FMATS FTDAR Programming/ erasing interface parameters DPFR FPFR FPEFEQ FUBRA FMPAR FMPDR FEBS RAM emulation RAMER O O O O -- O O O -- -- -- -- -- -- Initialization -- -- -- -- -- -- -- O O O -- -- -- -- Programming Erasure -- -- -- O O* -- -- O -- -- O O -- -- 1 Read -- -- -- -- RAM Emulation -- -- -- -- -- -- -- O O* -- -- O -- -- -- -- O -- 1 O* -- -- -- -- -- -- -- -- -- 2 -- -- -- -- -- -- -- -- -- O Notes: *1 The setting is required when programming or erasing user MAT in user boot mode. *2 The setting may be required according to the combination of initiation mode and read target MAT. 22.4.2 Programming/Erasing Interface Registers The programming/erasing interface registers are as described below. They are all 8-bit registers that can be accessed in bytes. Except for the FLER bit in FCCS and FMATS, these registers are initialized at a power-on reset, in hardware standby mode, or in software standby mode. The FLER bit or FMATS is not initialized in software standby mode. (1) Flash Code Control and Status Register (FCCS) FCCS is configured by bits which request the monitor of the FWE pin state and error occurrence during programming or erasing flash memory and the download of the on-chip program. Bit : 7 FWE Initial value : R/W : 1/0 R 6 -- 0 R 5 -- 0 R 4 FLER 0 R 3 -- 0 R 2 -- 0 R 1 -- 0 R 0 SCO 0 (R)/W Rev.2.0, 07/03, page 748 of 960 Bit 7--Flash Programming Enable (FWE): Monitors the level which is input to the FWE pin that performs hardware protection of the flash memory programming or erasing. The initial value is 0 or 1 according to the FWE pin state. Bit 7 FWE 0 1 Description When the FWE pin goes low (in hardware protection state) When the FWE pin goes high Bits 6 and 5--Reserved: These bits are always read as 0. The write value should always be 0. Bit 4--Flash Memory Error (FLER): Indicates an error occurs during programming and erasing flash memory. When FLER is set to 1, flash memory enters the error protection state. This bit is initialized at a power-on reset or in hardware standby mode. When FLER is set to 1, high voltage is applied to the internal flash memory. To reduce the damage to flash memory, the reset signal must be released after the reset period of 100 s which is longer than normal. Bit 4 FLER 0 Description Flash memory operates normally (Initial value) Programming/erasing protection for flash memory (error protection) is invalid. [Clearing condition] At a power-on reset or in hardware standby mode Indicates an error occurs during programming/erasing flash memory. Programming/erasing protection for flash memory (error protection) is valid. [Setting condition] See section 22.6.3, Error Protection. 1 Bits 3 to 1--Reserved: These bits should always be cleared to 0. Bit 0--Source Program Copy Operation (SCO): Requests the on-chip programming/erasing program to be downloaded to the on-chip RAM. When this bit is set to 1, the on-chip program which is selected by FPCS/FECS is automatically downloaded in the on-chip RAM area specified by FTDAR. In order to set this bit to 1, RAM emulation state must be canceled, H'A5 must be written to FKEY, and this operation must be in the on-chip RAM. Four NOP instructions must be executed immediately after setting this bit to 1. Rev.2.0, 07/03, page 749 of 960 For interrupts during download, see section 22.8.2, Interrupts during Programming/Erasing. For the download time, see section 22.8.3, Other Notes. Since this bit is cleared to 0 when download is completed, this bit cannot be read as 1. Download by setting the SCO bit to 1 requires a special interrupt processing that performs bank switching to the on-chip program storage area. Therefore, before issuing a download request (SCO = 1), set VBR to H'00000000. Otherwise, the CPU gets out of control. Once download end is confirmed, VBR can be changed to any other value. Bit 0 SCO 0 Description Download of the on-chip programming/erasing program to the on-chip RAM is not executed (Initial value) [Clear condition] When download is completed Request that the on-chip programming/erasing program is downloaded to the onchip RAM is generated [Set conditions] When all of the following conditions are satisfied and 1 is written to this bit * * * H'A5 is written to FKEY During execution in the on-chip RAM Not in RAM emulation mode (RAMS in RAMCR = 0) 1 (2) Flash Program Code Select Register (FPCS) FPCS selects the on-chip programming program to be downloaded. Bit : 7 -- Initial value : R/W : 0 R 6 -- 0 R 5 -- 0 R 4 -- 0 R 3 -- 0 R 2 -- 0 R 1 -- 0 R 0 PPVS 0 R/W Bits 7 to 1--Reserved: These bits are always read as 0. The write value should always be 0. Bit 0--Program Pulse Single (PPVS): Selects the programming program. Bit 0 PPVS 0 1 Description On-chip programming program is not selected [Clear condition] When transfer is completed On-chip programming program is selected (Initial value) Rev.2.0, 07/03, page 750 of 960 (3) Flash Erase Code Select Register (FECS) FECS selects download of the on-chip erasing program. Bit : 7 -- Initial value : R/W : 0 R 6 -- 0 R 5 -- 0 R 4 -- 0 R 3 -- 0 R 2 -- 0 R 1 -- 0 R 0 EPVB 0 R/W Bits 7 to 1--Reserved: These bits are always read as 0. The write value should always be 0. Bit 0--Erase Pulse Verify Block (EPVB): Selects the erasing program. Bit 0 EPVB 0 1 Description On-chip erasing program is not selected [Clear condition] When transfer is completed On-chip erasing program is selected (Initial value) (4) Flash Key Code Register (FKEY) FKEY is a register for software protection that enables download of the on-chip program and programming/erasing of flash memory. Before setting the SCO bit to 1 in order to download the on-chip program or executing the downloaded programming/erasing program, these processings cannot be executed if the key code is not written. Bit : 7 K7 Initial value : R/W : 0 R/W 6 K6 0 R/W 5 K5 0 R/W 4 K4 0 R/W 3 K3 0 R/W 2 K2 0 R/W 1 K1 0 R/W 0 K0 0 R/W Bits 7 to 0--Key Code (K7 to K0): Only when H'A5 is written, writing to the SCO bit is valid. When a value other than H'A5 is written to FKEY, 1 cannot be written to the SCO bit. Therefore downloading to the on-chip RAM cannot be executed. Only when H'5A is written, programming/erasing of flash memory can be executed. Even if the on-chip programming/erasing program is executed, flash memory cannot be programmed or erased when a value other than H'5A is written to FKEY. Rev.2.0, 07/03, page 751 of 960 Bits 7 to 0 K7 to K0 H'A5 H'5A H'00 Description Writing to the SCO bit is enabled (The SCO bit cannot be set by a value other than H'A5.) Programming/erasing is enabled (A value other than H'A5 enables software protection state.) Initial value (5) Flash MAT Select Register (FMATS) FMATS specifies whether user MAT or user boot MAT is selected. Bit : Initial value : Initial value : R/W : 7 MS7 0 1 R/W 6 MS6 0 0 R/W 5 MS5 0 1 R/W 4 MS4 0 0 R/W 3 MS3 0 1 R/W 2 MS2 0 0 R/W 1 MS1 0 1 R/W 0 MS0 0 0 R/W (When not in user boot mode) (When in user boot mode) Bits 7 to 0--MAT Select (MS7 to MS0): These bits are in user-MAT selection state when a value other than H'AA is written and in user-boot-MAT selection state when H'AA is written. The MAT is switched by writing a value in FMATS. When the MAT is switched, follow section 22.8.1, Switching between User MAT and User Boot MAT. (The user boot MAT cannot be programmed in user program mode if user boot MAT is selected by FMATS. The user boot MAT must be programmed in boot mode or in programmer mode.) Bits 7 to 0 MS7 to MS0 H'AA Description The user boot MAT is selected (in user-MAT selection state when the value of these bits are other than H'AA) Initial value when these bits are initiated in user boot mode. H'00 Initial value when these bits are initiated in a mode except for user boot mode (in user-MAT selection state) [Programmable condition] These bits are in the execution state in the on-chip RAM. Rev.2.0, 07/03, page 752 of 960 (6) Flash Transfer Destination Address Register (FTDAR) FTDAR specifies the on-chip RAM address to which the on-chip program is downloaded. Make settings for FTDAR before writing 1 to the SCO bit in FCCS. The initial value is H'00 which points to the start address (H'FFFF6000) in on-chip RAM. Bit : 7 TDER Initial value : R/W : 0 R/W 6 TDA6 0 R/W 5 TDA5 0 R/W 4 TDA4 0 R/W 3 TDA3 0 R/W 2 TDA2 0 R/W 1 TDA1 0 R/W 0 TDA0 0 R/W Bit 7--Transfer Destination Address Setting Error: This bit is set to 1 when there is an error in the download start address set by bits 6 to 0 (TDA6 to TDA0). Whether the address setting is erroneous or not is judged by checking whether the setting of TDA6 to TDA0 is between the range of H'00 and H'05 after setting the SCO bit in FCCS to 1 and performing download. Before setting the SCO bit to 1 be sure to set the FTDAR value between H'00 to H'05 as well as clearing this bit to 0. Bit 7 TDER 0 1 Description (Return Value after Download) Setting of TDA6 to TDA0 is normal (Initial value) Setting of TDER and TDA6 to TDA0 is H'06 to H'FF and download has been aborted Bits 6 to 0--Transfer Destination Address (TDA6 to TDA0): These bits specify the download start address. A value from H'00 to H'05 can be set to specify the download start address in onchip RAM in 2-kbyte units. A value from H'06 to H'7F cannot be set. If such a value is set, the TDER bit (bit 7) in this register is set to 1 to prevent download from being executed. Rev.2.0, 07/03, page 753 of 960 Bits 6 to 0 TDA6 to TDA0 H'00 H'01 H'02 H'03 H'04 H'05 H'06 to H'7F Description Download start address is set to H'FFFF6000 Download start address is set to H'FFFF6800 Download start address is set to H'FFFF7000 Download start address is set to H'FFFF7800 Download start address is set to H'FFFF8000 Download start address is set to H'FFFF8800 Setting prohibited. If this value is set, the TDER bit (bit 7) is set to 1 to abort the download processing. 22.4.3 Programming/Erasing Interface Parameters The programming/erasing interface parameters specify the operating frequency, user branch destination address, storage place for program data, programming destination address, and erase block and exchanges the processing result for the downloaded on-chip program. This parameter uses the general registers of the CPU (R4, R5, and R0) or the on-chip RAM area. The initial value is undefined at a power-on reset or in hardware standby mode. At download all CPU registers are stored, and at initialization or when the on-chip program is executed, CPU registers except for R0 are stored. The return value of the processing result is written in R0. Since the stack area is used for storing the registers or as a work area, the stack area must be saved at the processing start. (The maximum size of a stack area to be used is 128 bytes.) The programming/erasing interface parameters are used in the following four items. (1) Download control (2) Initialization before programming or erasing (3) Programming (4) Erasing These items use different parameters. The correspondence table is shown in table 22.6. The processing results of initialization, programming, and erasing are returned, but the bit contents have different meanings according to the processing program. See the description of FPFR for each processing. Rev.2.0, 07/03, page 754 of 960 Table 22.6 Usable Parameters and Target Modes Name of Parameter Download pass/fail result Flash pass/fail result Flash programming/ erasing frequency control Flash user branch address set parameter Flash multipurpose address area Flash multipurpose data destination area Flash erase block select Abbreviation DPFR FPFR FPEFEQ Down load O -- -- Initialization -- O O Programming -- O -- Erasure -- O -- R/W R/W R/W R/W Initial Value Undefined Undefined Undefined Allocation On-chip RAM* R0 of CPU R4 of CPU FUBRA -- O -- -- R/W Undefined R5 of CPU FMPAR FMPDR FEBS -- -- -- -- -- -- O O -- -- -- O R/W R/W R/W Undefined Undefined Undefined R5 of CPU R4 of CPU R4 of CPU Note: * One byte of start address of download destination specified by FTDAR (1) Download Control The on-chip program is automatically downloaded by setting the SCO bit to 1. The on-chip RAM area to be downloaded is the area as much as 2 kbytes starting from the start address specified by FTDAR. For the address map of the on-chip RAM, see figure 22.10. The download control is set by using the programming/erasing interface registers. The return value is given by the DPFR parameter. (a) Download pass/fail result parameter (DPFR: one byte of start address of on-chip RAM specified by FTDAR) This parameter indicates the return value of the download result. The value of this parameter can be used to determine if downloading is executed or not. Since the confirmation whether the SCO bit is set to 1 is difficult, the certain determination must be performed by setting one byte of the start address of the on-chip RAM area specified by FTDAR to a value other than the return value of download (for example, H'FF) before the download start (before setting the SCO bit to 1). For the checking method of download results, see section 22.5.2, User Program Mode. Bit : 7 0 6 0 5 0 4 0 3 0 2 SS 1 FK 0 SF Bits 7 to 3--Unused: Return 0. Rev.2.0, 07/03, page 755 of 960 Bit 2--Source Select Error Detect (SS): The on-chip program which can be downloaded can be specified as only one type at a time. When more than two types of the program are selected, the program is not selected, or the program is selected without mapping, an error occurs. Bit 2 SS 0 1 Description Download program can be selected normally Download error occurs (Multi-selection or program which is not mapped is selected) Bit 1--Flash Key Register Error Detect (FK): Returns the check result whether the value of FKEY is set to H'A5. Bit 1 FK 0 1 Description FKEY setting is normal (FKEY = H'A5) FKEY setting is abnormal (FKEY = value other than H'A5) Bit 0--Success/Fail (SF): Returns the result whether download has ended normally or not. Bit 0 SF 0 1 Description Downloading on-chip program has ended normally (no error) Downloading on-chip program has ended abnormally (error occurs) (2) Programming/Erasing Initialization The on-chip programming/erasing program to be downloaded includes the initialization program. The specified period pulse must be applied when programming or erasing. The specified pulse width is made by the method in which wait loop is configured by the CPU instruction. The operating frequency of the CPU must be set. Since the user branch function is supported, the user branch destination address must be set. The initial program is set as a parameter of the programming/erasing program which has downloaded these settings. Rev.2.0, 07/03, page 756 of 960 (2.1) Flash programming/erasing frequency parameter (FPEFEQ: general register R4 of CPU) This parameter sets the operating frequency of the CPU. For the range of the operating frequency of this LSI, see section 25.3.2, Clock Timing. Bit : 31 0 Bit : 23 0 Bit : 15 F15 Bit : 7 F7 30 0 22 0 14 F14 6 F6 29 0 21 0 13 F13 5 F5 28 0 20 0 12 F12 4 F4 27 0 19 0 11 F11 3 F3 26 0 18 0 10 F10 2 F2 25 0 17 0 9 F9 1 F1 24 0 16 0 8 F8 0 F0 Bits 31 to 16--Unused: Return 0. Bits 15 to 0--Frequency Set (F15 to F0): Set the operating frequency of the CPU. The setting value must be calculated as the following methods. 1. The operating frequency which is shown in MHz units must be rounded in a number to three decimal places and be shown in a number of two decimal places. 2. The centuplicated value is converted to the binary digit and is written to the FPEFEQ parameter (general register R4). For example, when the operating frequency of the CPU is 28.882 MHz, the value is as follows. 1. The number to three decimal places of 28.882 is rounded and the value is thus 28.88. 2. The formula that 28.88 x 100 = 2888 is converted to the binary digit and b'0000,1011,0100,1000 (H'0B48) is set to R4. Rev.2.0, 07/03, page 757 of 960 (2.2) Flash user branch address setting parameter (FUBRA: general register R5 of CPU) This parameter sets the user branch destination address. The user program which has been set can be executed in specified processing units when programming and erasing. Bit : 31 UA31 Bit : 23 UA23 Bit : 15 UA15 Bit : 7 UA7 30 UA30 22 UA22 14 UA14 6 UA6 29 UA29 21 UA21 13 UA13 5 UA5 28 UA28 20 UA20 12 UA12 4 UA4 27 UA27 19 UA19 11 UA11 3 UA3 26 UA26 18 UA18 10 UA10 2 UA2 25 UA25 17 UA17 9 UA9 1 UA1 24 UA24 16 UA16 8 UA8 0 UA0 Bits 31 to 0--User Branch Destination Address (UA31 to UA0): When the user branch is not required, address 0 (H'00000000) must be set. The user branch destination must be an area other than the flash memory, an area other than the RAM area in which on-chip program has been transferred, or the external bus space. Note that the CPU must not branch to an area without the execution code and get out of control. The on-chip program download area and stack area must not be overwritten. If CPU runaway occurs or the download area or stack area is overwritten, the value of flash memory cannot be guaranteed. The download of the on-chip program, initialization, initiation of the programming/erasing program must not be executed in the processing of the user branch destination. Programming or erasing cannot be guaranteed when returning from the user branch destination. The program data which has already been prepared must not be programmed. The general registers R8 to R15 are stored. The general registers R0 to R7 can be used without being stored. Moreover, the programming/erasing interface registers must not be written to or RAM emulation mode must not be entered in the processing of the user branch destination. After the processing of the user branch has ended, the programming/erasing program must be returned to by using the RTS instruction. For the execution intervals of the user branch processing, see note 2 (User branch processing intervals) in section 22.8.3, Other Notes. Rev.2.0, 07/03, page 758 of 960 (2.3) Flash pass/fail result parameter (FPFR: general register R0 of CPU) This parameter indicates the return value of the initialization result. Bit : 31 0 Bit : 23 0 Bit : 15 0 Bit : 7 0 30 0 22 0 14 0 6 0 29 0 21 0 13 0 5 0 28 0 20 0 12 0 4 0 27 0 19 0 11 0 3 0 26 0 18 0 10 0 2 BR 25 0 17 0 9 0 1 FQ 24 0 16 0 8 0 0 SF Bits 31 to 3--Unused: Return 0. Bit 2--User Branch Error Detect (BR): Returns the check result whether the specified user branch destination address is in the area other than the storage area of the programming/erasing program which has been downloaded . Bit 2 BR 0 1 Description User branch address setting is normal User branch address setting is abnormal Bit 1--Frequency Error Detect (FQ): Returns the check result whether the specified operating frequency of the CPU is in the range of the supported operating frequency. Bit 1 FQ 0 1 Description Setting of operating frequency is normal Setting of operating frequency is abnormal Bit 0--Success/Fail (SF): Indicates whether initialization is completed normally. Bit 0 SF 0 1 Description Initialization has ended normally (no error) Initialization has ended abnormally (error occurs) Rev.2.0, 07/03, page 759 of 960 (3) Programming Execution When flash memory is programmed, the programming destination address on the user MAT must be passed to the programming program in which the program data is downloaded. 1. The start address of the programming destination on the user MAT is set in general register R5 of the CPU. This parameter is called FMPAR (flash multipurpose address area parameter). Since the program data is always in 128-byte units, the lower eight bits (MOA7 to MOA0) must be H'00 or H'80 as the boundary of the programming start address on the user MAT. 2. The program data for the user MAT must be prepared in the consecutive area. The program data must be in the consecutive space which can be accessed by using the MOV.B instruction of the CPU and is not the flash memory space. When data to be programmed does not satisfy 128 bytes, the 128-byte program data must be prepared by embedding the dummy code (H'FF). The start address of the area in which the prepared program data is stored must be set in general register R4. This parameter is called FMPDR (flash multipurpose data destination area parameter). For details on the programming procedure, see section 22.5.2, User Program Mode. (3.1) Flash multipurpose address area parameter (FMPAR: general register R5 of CPU) This parameter indicates the start address of the programming destination on the user MAT. When an address in an area other than the flash memory space is set, an error occurs. The start address of the programming destination must be at the 128-byte boundary. If this boundary condition is not satisfied, an error occurs. The error occurrence is indicated by the WA bit (bit 1) in FPFR. Bit : 31 MOA31 Bit : 23 MOA23 Bit : 15 MOA15 Bit : 7 MOA7 30 29 28 27 26 MOA26 18 MOA18 10 MOA10 2 MOA2 25 24 MOA30 MOA29 22 21 MOA28 MOA27 20 19 MOA25 MOA24 17 16 MOA22 MOA21 14 13 MOA20 MOA19 12 11 MOA17 MOA16 9 MOA9 1 MOA1 8 MOA8 0 MOA0 MOA14 MOA13 6 MOA6 5 MOA5 MOA12 MOA11 4 MOA4 3 MOA3 Bits 31 to 0--MOA31 to MOA0: Store the start address of the programming destination on the user MAT. The consecutive 128-byte programming is executed starting from the specified start address of the user MAT. The MOA6 to MOA0 bits are always 0 because the start address of the programming destination is at the 128-byte boundary. Rev.2.0, 07/03, page 760 of 960 (3.2) Flash multipurpose data destination parameter (FMPDR: general register R4 of CPU) This parameter indicates the start address in the area which stores the data to be programmed in the user MAT. When the storage destination of the program data is in flash memory, an error occurs. The error occurrence is indicated by the WD bit (bit 2) in FPFR. Bit : 31 MOD31 Bit : 23 MOD23 Bit : 15 MOD15 Bit : 7 MOD7 30 29 28 27 26 25 24 MOD30 MOD29 MOD28 MOD27 MOD26 22 21 20 19 18 MOD25 MOD24 17 16 MOD22 MOD21 MOD20 MOD19 MOD18 14 13 12 11 10 MOD17 MOD16 9 MOD9 1 MOD1 8 MOD8 0 MOD0 MOD14 MOD13 MOD12 MOD11 MOD10 6 MOD6 5 MOD5 4 MOD4 3 MOD3 2 MOD2 Bits 31 to 0--MOD31 to MOD0: Store the start address of the area which stores the program data for the user MAT. The consecutive 128-byte data is programmed to the user MAT starting from the specified start address. (3.3) Flash pass/fail parameter (FPFR: general register R0 of CPU) This parameter indicates the return value of the program processing result. Bit : 31 0 Bit : 23 0 Bit : 15 0 Bit : 7 0 30 0 22 0 14 0 6 MD 29 0 21 0 13 0 5 EE 28 0 20 0 12 0 4 FK 27 0 19 0 11 0 3 0 26 0 18 0 10 0 2 WD 25 0 17 0 9 0 1 WA 24 0 16 0 8 0 0 SF Bits 31 to 7--Unused: Return 0. Bit 6--Programming Mode Related Setting Error Detect (MD): Returns the check result of whether the signal input to the FWE pin is high and whether the error protection state is entered. When a low-level signal is input to the FWE pin or the error protection state is entered, 1 is written to this bit. The input level to the FWE pin and the error protection state can be confirmed Rev.2.0, 07/03, page 761 of 960 with the FWE bit (bit 7) and the FLER bit (bit 4) in FCCS, respectively. For conditions to enter the error protection state, see section 22.6.3, Error Protection. Bit 6 MD 0 1 Description FWE and FLER settings are normal (FWE = 1, FLER = 0) FWE = 0 or FLER = 1, and programming cannot be performed Bit 5--Programming Execution Error Detect (EE): 1 is returned to this bit when the specified data could not be written because the user MAT was not erased or when flash-memory related register settings are partially changed on returning from the user branch processing. If this bit is set to 1, there is a high possibility that the user MAT is partially rewritten. In this case, after removing the error factor, erase the user MAT. If FMATS is set to H'AA and the user boot MAT is selected, an error occurs when programming is performed. In this case, both the user MAT and user boot MAT are not rewritten. Programming of the user boot MAT must be executed in boot mode or programmer mode. Bit 5 EE 0 1 Description Programming has ended normally Programming has ended abnormally (programming result is not guaranteed) Bit 4--Flash Key Register Error Detect (FK): Returns the check result of the value of FKEY before the start of the programming processing. Bit 4 FK 0 1 Description FKEY setting is normal (FKEY = H'A5) FKEY setting is error (FKEY = value other than H'A5) Bit 3--Unused: Returns 0. Rev.2.0, 07/03, page 762 of 960 Bit 2--Write Data Address Detect (WD): When an address in the flash memory area is specified as the start address of the storage destination of the program data, an error occurs. Bit 2 WD 0 1 Description Setting of write data address is normal Setting of write data address is abnormal Bit 1--Write Address Error Detect (WA): When the following items are specified as the start address of the programming destination, an error occurs. 1. The programming destination address is an area other than flash memory 2. The specified address is not at the 128-byte boundary (A6 to A0 are not 0) Bit 1 WA 0 1 Description Setting of programming destination address is normal Setting of programming destination address is abnormal Bit 0--Success/Fail (SF): Indicates whether the program processing has ended normally or not. Bit 0 SF 0 1 Description Programming has ended normally (no error) Programming has ended abnormally (error occurs) (4) Erasure Execution When flash memory is erased, the erase-block number on the user MAT must be passed to the erasing program which is downloaded. This is set to the FEBS parameter (general register R4). One block is specified from the block number 0 to 15. For details on the erasing procedure, see section 22.5.2, User Program Mode. Rev.2.0, 07/03, page 763 of 960 (4.1) Flash erase block select parameter (FEBS: general register R4 of CPU) This parameter specifies the erase-block number. Several block numbers cannot be specified. Bit : 31 0 Bit : 23 0 Bit : 15 0 Bit : 7 EBS7 30 0 22 0 14 0 6 EBS6 29 0 21 0 13 0 5 EBS5 28 0 20 0 12 0 4 EBS4 27 0 19 0 11 0 3 EBS3 26 0 18 0 10 0 2 EBS2 25 0 17 0 9 0 1 EBS1 24 0 16 0 8 0 0 EBS0 Bits 31 to 8--Unused: Return 0. Bits 7 to 0--Erase Block (EB7 to EB0): Set the erase-block number in the range from 0 to 15. 0 corresponds to the EB0 block and 15 corresponds to the EB15 block. An error occurs when a number other than 0 to 15 (H'00 to H'0F) is set. (4.2) Flash pass/fail result parameter (FPFR: general register R0 of CPU) This parameter returns the value of the erasing processing result. Bit : 31 0 Bit : 23 0 Bit : 15 0 Bit : 7 0 30 0 22 0 14 0 6 MD 29 0 21 0 13 0 5 EE 28 0 20 0 12 0 4 FK 27 0 19 0 11 0 3 EB 26 0 18 0 10 0 2 0 25 0 17 0 9 0 1 0 24 0 16 0 8 0 0 SF Bits 31 to 7--Unused: Return 0. Bit 6--Erasure Mode Related Setting Error Detect (MD): Returns the check result of whether the signal input to the FWE pin is high and whether the error protection state is entered. When a low-level signal is input to the FWE pin or the error protection state is entered, 1 is written to this bit. The input level to the FWE pin and the error protection state can be confirmed Rev.2.0, 07/03, page 764 of 960 with the FWE bit (bit 7) and the FLER bit (bit 4) in FCCS, respectively. For conditions to enter the error protection state, see section 22.6.3, Error Protection. Bit 6 MD 0 1 Description FWE and FLER settings are normal (FWE = 1, FLER = 0) FWE = 0 or FLER = 1, and erasure cannot be performed Bit 5--Erasure Execution Error Detect (EE): 1 is returned to this bit when the user MAT could not be erased or when flash-memory related register settings are partially changed on returning from the user branch processing. If this bit is set to 1, there is a high possibility that the user MAT is partially erased. In this case, after removing the error factor, erase the user MAT. If FMATS is set to H'AA and the user boot MAT is selected, an error occurs when erasure is performed. In this case, both the user MAT and user boot MAT are not erased. Erasure of the user boot MAT must be executed in boot mode or programmer mode. Bit 5 EE 0 1 Description Erasure has ended normally Erasure has ended abnormally (erasure result is not guaranteed) Bit 4--Flash Key Register Error Detect (FK): Returns the check result of FKEY value before start of the erasing processing. Bit 4 FK 0 1 Description FKEY setting is normal (FKEY = H'5A) FKEY setting is error (FKEY = value other than H'5A) Bit 3--Erase Block Select Error Detect (EB): Returns the check result whether the specified erase-block number is in the block range of the user MAT. Bit 3 EB 0 1 Description Setting of erase-block number is normal Setting of erase-block number is abnormal Rev.2.0, 07/03, page 765 of 960 Bits 2 and 1--Unused: Return 0. Bit 0--Success/Fail (SF): Indicates whether the erasing processing has ended normally or not. Bit 0 SF 0 1 Description Erasure has ended normally (no error) Erasure has ended abnormally (error occurs) 22.4.4 RAM Emulation Register (RAMER) When the realtime programming of the user MAT is emulated, RAMER sets the area of the user MAT which is overlapped with a part of the on-chip RAM. RAMER is initialized to H'0000 at a power-on reset or in hardware standby mode and is not initialized in software standby mode. The RAMER setting must be executed in user mode or in user program mode. For the division method of the user-MAT area, see table 22.7. In order to operate the emulation function certainly, the target MAT of the RAM emulation must not be accessed immediately after RAMER is programmed. If it is accessed, the normal access is not guaranteed. Bit : 15 -- Initial value : R/W : Bit 0 R 7 -- Initial value : R/W : 0 R 14 -- 0 R 6 -- 0 R 13 -- 0 R 5 -- 0 R 12 -- 0 R 4 -- 0 R 11 -- 0 R 3 RAMS 0 R/W 10 -- 0 R 2 RAM2 0 R/W 9 -- 0 R 1 RAM1 0 R/W 8 -- 0 R 0 RAM0 0 R/W : Bits 15 to 4--Reserved: These bits are always read as 0. The write value should always be 0. Rev.2.0, 07/03, page 766 of 960 Bit 3--RAM Select (RAMS): Sets whether the user MAT is emulated or not. When RAMS = 1, all blocks of the user MAT are in the programming/erasing protection state. Bit 3 RAMS 0 1 Description Emulation is not selected Programming/erasing protection of all user-MAT blocks is invalid Emulation is selected Programming/erasing protection of all user-MAT blocks is valid (Initial value) Bits 2 to 0--User MAT Area Select: These bits are used with bit 3 to select the user-MAT area to be overlapped with the on-chip RAM. (See table 22.7.) Table 22.7 Overlapping of RAM Area and User MAT Area RAM Area H'FFFF6000 to H'FFFF6FFF H'00000000 to H'00000FFF H'00001000 to H'00001FFF H'00002000 to H'00002FFF H'00003000 to H'00003FFF H'00004000 to H'00004FFF H'00005000 to H'00005FFF H'00006000 to H'00006FFF H'00007000 to H'00007FFF Note: * Don't care. Block Name RAM area (4 kbytes) EB0 (4 kbytes) EB1 (4 kbytes) EB2 (4 kbytes) EB3 (4 kbytes) EB4 (4 kbytes) EB5 (4 kbytes) EB6 (4 kbytes) EB7 (4 kbytes) RAMS 0 1 1 1 1 1 1 1 1 RAM2 * 0 0 0 0 1 1 1 1 RAM1 * 0 0 1 1 0 0 1 1 RAM0 * 0 1 0 1 0 1 0 1 Rev.2.0, 07/03, page 767 of 960 22.5 On-Board Programming Mode When the pin is set in on-board programming mode and the reset start is executed, the on-board programming state that can program/erase the on-chip flash memory is entered. On-board programming mode has three operating modes: user programming mode, user boot mode, and boot mode. For details on the pin setting for entering each mode, see table 22.1. For details on the state transition of each mode for flash memory, see figure 22.2. 22.5.1 Boot Mode Boot mode executes programming/erasing user MAT and user boot MAT by means of the control command and program data transmitted from the host using the on-chip SCI. The tool for transmitting the control command and program data must be prepared in the host. The SCI communication mode is set to asynchronous mode. When reset start is executed after this LSI's pin is set in boot mode, the boot program in the microcomputer is initiated. After the SCI bit rate is automatically adjusted, the communication with the host is executed by means of the control command method. The system configuration diagram in boot mode is shown in figure 22.6. For details on the pin setting in boot mode, see table 22.1. Interrupts are ignored in boot mode, so do not generate them. Note that the AUD cannot be used during boot mode operation. This LSI Control command, analysis execution software (on-chip) Flash memory Host Boot Control command, program data programming tool and program data Reply response RxD1 On-chip SCI1 TxD1 On-chip RAM Figure 22.6 System Configuration in Boot Mode Rev.2.0, 07/03, page 768 of 960 (1) SCI Interface Setting by Host When boot mode is initiated, this LSI measures the low period of asynchronous SCIcommunication data (H'00), which is transmitted consecutively by the host. The SCI transmit/receive format is set to 8-bit data, 1 stop bit, and no parity. This LSI calculates the bit rate of transmission by the host by means of the measured low period and transmits the bit adjustment end sign (1 byte of H'00) to the host. The host must confirm that this bit adjustment end sign (H'00) has been received normally and transmits 1 byte of H'55 to this LSI. When reception is not executed normally, boot mode is initiated again (reset) and the operation described above must be executed. The bit rate between the host and this LSI is not matched because of the bit rate of transmission by the host and system clock frequency of this LSI. To operate the SCI normally, the transfer bit rate of the host must be set to 9,600 bps or 19,200 bps. The system clock frequency which can automatically adjust the transfer bit rate of the host and the bit rate of this LSI is shown in table 22.8. Boot mode must be initiated in the range of this system clock. Start bit D0 D1 D2 D3 D4 D5 D6 D7 Stop bit Measure low period (9 bits) (data is H'00) High period of at least 1 bit Figure 22.7 Automatic Adjustment Operation of SCI Bit Rate Table 22.8 System Clock Frequency that Can Automatically Adjust Bit Rate of This LSI Host Bit Rate 9,600 bps 19,200 bps System Clock Frequency Which Can Automatically Adjust LSI's Bit Rate 20 to 40 MHz (input frequency of 5 to 10 MHz) 20 to 40 MHz (input frequency of 5 to 10 MHz) (2) State Transition The overview of the state transition after boot mode is initiated is shown in figure 22.8. For details on boot mode, see section 22.10.1, Serial Communications Interface Specification for Boot Mode. 1. Bit rate adjustment After boot mode is initiated, the bit rate of the SCI interface is adjusted with that of the host. 2. Waiting for inquiry set command For inquiries about the user-MAT size and configuration, MAT start address, and support state, the required information is transmitted to the host. 3. Automatic erasure of all user MAT and user boot MAT After inquiries have finished and a programming/erasing status transition command has been sent, all of the user MAT and user boot MAT are automatically erased. Rev.2.0, 07/03, page 769 of 960 4. Waiting for programming/erasing command * When the program selection command is received, the state for waiting program data is entered. The programming start address and program data must be transmitted following the programming command. When programming is finished, the programming start address must be set to H'FFFFFFFF and transmitted. Then the state for waiting program data is returned to the state of programming/erasing command wait. * When the erasure selection command is received, the state for waiting erase-block data is entered. The erase-block number must be transmitted following the erasing command. When the erasure is finished, the erase-block number must be set to H'FF and transmitted. Then the state for waiting erase-block data is returned to the state for waiting programming/erasing command. The erasure must be executed when reset start is not executed and the specified block is programmed after programming is executed in boot mode. When programming can be executed by only one operation, all blocks are erased before the state for waiting programming/erasing/other command is entered. The erasing operation is not required. * There are many commands other than programming/erasing. Examples are sum check, blank check (erasure check), and memory read of the user MAT/user boot MAT and acquisition of current status information. Note that memory read of the user MAT/user boot MAT can only read the program data after all user MAT/user boot MAT has automatically been erased. Rev.2.0, 07/03, page 770 of 960 (Bit rate adjustment) H'00 to H'00 reception Boot mode initiation (reset by boot mode) H'55 rece ption Bit rate adjustment 1 Inquiry command reception 2 Wait for inquiry setting command Inquiry command response Processing of inquiry setting command 3 All user MAT and user boot MAT erasure 4 Wait for programming/erasing command Read/check command reception Command response Processing of read/check command Erasure selection command reception Erasure end notice Program selection command reception Program data transmission Erase-block specification Wait for erase-block data Program end notice Wait for program data Figure 22.8 Overview of Boot Mode State Transition 22.5.2 User Program Mode The user MAT can be programmed/erased in user program mode. (The user boot MAT cannot be programmed/erased.) Programming/erasing is executed by downloading the program in the microcomputer. The overview flow is shown in figure 22.9. High voltage is applied to internal flash memory during the programming/erasing processing. Therefore, transition to reset or hardware standby mode must not be executed. Doing so may cause damage or destroy flash memory. If reset is executed accidentally, the reset signal must be released after the reset input period, which is longer than the normal 100 s. Rev.2.0, 07/03, page 771 of 960 For details on the programming procedure, see the description in 22.5.2 (2) Programming Procedure in User Program Mode. For details on the erasing procedure, see the description in 22.5.2 (3) Erasing Procedure in User Program Mode. For the overview of a processing that repeats erasing and programming by downloading the programming program and the erasing program in separate on-chip ROM areas using FTDAR, see the description in 22.5.2 (4), Erasing and Programming Procedure in User Program Mode. Programming/erasing start When programming, program data is prepared 1. RAM emulation mode must be canceled in advance. Download cannot be executed in emulation mode. 2. When the program data is made by means of emulation, the download destination must be changed by FTDAR. With the initial setting of FTDAR (H'00), the download area is overlapped with the emulation area. 3. Inputting high level to the FWE pin sets the FWE bit to 1. 4. Programming/erasing is executed only in the on-chip RAM. However, if the program data is in a consecutive area and can be accessed by the MOV.B instruction of the CPU like SRAM/ROM, the program data can be in an external space. 5. After programming/erasing is finished, low level must be input to the FWE pin for protection. FWE=1 ? Yes No Programming/erasing procedure program is transferred to the on-chip RAM and executed Programming/erasing end Figure 22.9 Programming/Erasing Overview Flow Rev.2.0, 07/03, page 772 of 960 (1) On-Chip RAM Address Map when Programming/Erasing is Executed Parts of the procedure program that are made by the user, like download request, programming/erasing procedure, and judgement of the result, must be executed in the on-chip RAM. All of the on-chip program that is to be downloaded is in on-chip RAM. Note that onchip RAM must be controlled so that these parts do not overlap. Figure 22.10 shows the program area to be downloaded. Area to be downloaded (Size: 2 kbytes) Unusable area in programming/erasing processing period FTDAR setting+16 FTDAR setting+32 RAMEND (H'FFFFDFFF) Figure 22.10 RAM Map after Download Rev.2.0, 07/03, page 773 of 960 (2) Programming Procedure in User Program Mode The procedures for download, initialization, and programming are shown in figure 22.11. Start programming procedure program 1 Select on-chip program to be downloaded and set download destination by FTDAR Set FKEY to H'A5 After clearing VBR, set SCO to 1 and execute download Clear FKEY to 0 (2.1) Programming Set FKEY to H'5A (2.9) (2.10) (2.11) (2.12) No Clear FKEY and programming error processing (2.2) (2.3) (2.4) (2.5) No Set parameter to R4 and R5 (FMPAR and FMPDR) Programming JSR FTDAR setting+16 Download FPFR=0? Yes No Required data programming is completed? DPFR=0? Yes Download error processing (2.13) (2.14) Set the FPEFEQ and FUBRA parameters (2.6) (2.7) (2.8) No Yes Clear FKEY to 0 Initialization Initialization JSR FTDAR setting+32 End programming procedure program FPFR=0? Yes Initialization error processing 1 Figure 22.11 Programming Procedure The details of the programming procedure are described below. The procedure program must be executed in an area other than the flash memory to be programmed. Especially the part where the SCO bit in FCCS is set to 1 for downloading must be executed in the on-chip RAM. The area that can be executed in the steps of the user procedure program (on-chip RAM, user MAT, and external space) is shown in section 22.10.3, Storable Area for Procedure Program and Programming Data. The following description assumes the area to be programmed on the user MAT is erased and program data is prepared in the consecutive area. When erasing has not been executed, carry out erasing before writing. 128-byte programming is performed in one program processing. When more than 128-byte programming is performed, programming destination address/program data parameter is updated in 128-byte units and programming is repeated. Rev.2.0, 07/03, page 774 of 960 When less than 128-byte programming is performed, data must total 128 bytes by adding the invalid data. If the invalid data to be added is H'FF, the program processing period can be shortened. (2.1) Select the on-chip program to be downloaded When the PPVS bit of FPCS is set to 1, the programming program is selected. Several programming/erasing programs cannot be selected at one time. If several programs are set, download is not performed and a download error is returned to the source select error detect (SS) bit in the DPFR parameter. Specify the start address of the download destination by FTDAR. (2.2) Write H'A5 in FKEY If H'A5 is not written to FKEY for protection, 1 cannot be written to the SCO bit for a download request. (2.3) VBR is cleared to 0 and 1 is written to the SCO bit of FCCS, and then download is executed. VBR must always be cleared to H'00000000 before setting the SCO bit to 1. To write 1 to the SCO bit, the following conditions must be satisfied. * RAM emulation mode is canceled. * H'A5 is written to FKEY. * The SCO bit writing is executed in the on-chip RAM. When the SCO bit is set to 1, download is started automatically. When execution returns to the user procedure program, the SCO bit is cleared to 0. Therefore, the SCO bit cannot be confirmed to be 1 in the user procedure program. The download result can be confirmed only by the return value of the DPFR parameter. Before the SCO bit is set to 1, incorrect judgement must be prevented by setting the DPFR parameter, that is one byte of the start address of the on-chip RAM area specified by FTDAR, to a value other than the return value (H'FF). When download is executed, particular interrupt processing, which is accompanied by the bank switch as described below, is performed as an internal microcomputer processing, so VBR need to be cleared to 0. Four NOP instructions are executed immediately after the instructions that set the SCO bit to 1. * The user MAT space is switched to the on-chip program storage area. * After the selection condition of the download program and the address set in FTDAR are checked, the transfer processing is executed starting from the on-chip RAM address specified by FTDAR. * The SCO bits in FPCS, FECS, and FCCS are cleared to 0. * The return value is set to the DPFR parameter. * After the on-chip program storage area is returned to the user MAT space, execution returns to the user procedure program. After download is completed and the user procedure program is running, the VBR setting can be changed. The notes on download are as follows. Rev.2.0, 07/03, page 775 of 960 In the download processing, the values of the general registers of the CPU are retained. During the download processing, the interrupt processing cannot be executed. However, the NMI, UBC, and H-UDI interrupt requests are retained, so that on returning to the user procedure program, the interrupt processing starts. For details on the relationship between download and interrupts, see section 22.8.2, Interrupts during Programming/Erasing. Since a stack area of maximum 128 bytes is used, an area of at least 128 bytes must be saved before setting the SCO bit to 1. If flash memory is accessed by the DMAC or AUD during downloading, operation cannot be guaranteed. Therefore, access by the DMAC or AUD must not be executed. (2.4) FKEY is cleared to H'00 for protection. (2.5) The value of the DPFR parameter must be checked to confirm the download result. A recommended procedure for confirming the download result is shown below. * Check the value of the DPFR parameter (one byte of start address of the download destination specified by FTDAR). If the value is H'00, download has been performed normally. If the value is not H'00, the source that caused download to fail can be investigated by the description below. * If the value of the DPFR parameter is the same as before downloading (e.g. H'FF), the address setting of the download destination in FTDAR may be abnormal. In this case, confirm the setting of the TDER bit (bit 7) in FTDAR. * If the value of the DPFR parameter is different from before downloading, check the SS bit (bit 2) and the FK bit (bit 1) in the DPFR parameter to ensure that the download program selection and FKEY register setting were normal, respectively. (2.6) The operating frequency is set to the FPEFEQ parameter and the user branch destination is set to the FUBRA parameter for initialization. * The current frequency of the CPU clock is set to the FPEFEQ parameter (general register R4). For the settable range of the FPEFEQ parameter, see section 25.3.2, Clock Timing. For the settable range of the FPEFEQ parameter, see section 25.3.2, Clock Timing. When the frequency is set out of this range, an error is returned to the FPFR parameter of the initialization program and initialization is not performed. For details on the frequency setting, see the description in 22.4.3 (2.1) Flash programming/erasing frequency parameter (FPEFEQ). * The start address in the user branch destination is set to the FUBRA parameter (general register R5). When the user branch processing is not required, 0 must be set to FUBRA. When the user branch is executed, the branch destination is executed in flash memory other than the one that is to be programmed. The area of the on-chip program that is downloaded cannot be set. The program processing must be returned from the user branch processing by the RTS instruction. Rev.2.0, 07/03, page 776 of 960 See the description in 22.4.3 (2.2) Flash user branch address setting parameter (FUBRA). (2.7) Initialization When a programming program is downloaded, the initialization program is also downloaded to on-chip RAM. There is an entry point of the initialization program in the area from (download start address set by FTDAR) + 32 bytes. The subroutine is called and initialization is executed by using the following steps. MOV.L JSR NOP #DLTOP+32,R1 @R1 ; Set entry address to R1 ; Call initialization routine The general registers other than R0 are saved in the initialization program. R0 is a return value of the FPFR parameter. Since the stack area is used in the initialization program, a stack area of maximum 128 bytes must be reserved in RAM. Interrupts can be accepted during the execution of the initialization program. However, the program storage area and stack area in on-chip RAM and register values must not be destroyed. (2.8) The return value of the initialization program, FPFR (general register R0) is judged. (2.9) FKEY must be set to H'5A and the user MAT must be prepared for programming. (2.10) The parameter which is required for programming is set. The start address of the programming destination of the user MAT (FMPAR) is set to general register R5. The start address of the program data storage area (FMPDR) is set to general register R4. * FMPAR setting FMPAR specifies the programming destination start address. When an address other than one in the user MAT area is specified, even if the programming program is executed, programming is not executed and an error is returned to the return value parameter FPFR. Since the unit is 128 bytes, the lower eight bits (MOA7 to MOA0) must be in the 128-byte boundary of H'00 or H'80. * FMPDR setting If the storage destination of the program data is flash memory, even when the program execution routine is executed, programming is not executed and an error is returned to the FPFR parameter. In this case, the program data must be transferred to on-chip RAM and then programming must be executed. (2.11) Programming There is an entry point of the programming program in the area from (download start address set by FTDAR) + 16 bytes of on-chip RAM. The subroutine is called and programming is executed by using the following steps. Rev.2.0, 07/03, page 777 of 960 MOV.L JSR NOP #DLTOP+16,R1 @R1 ; Set entry address to R1 ; Call programming routine The general registers other than R0 are saved in the programming program. R0 is a return value of the FPFR parameter. Since the stack area is used in the programming program, a stack area of maximum 128 bytes must be reserved in RAM. (2.12) The return value in the programming program, FPFR (general register R0) is judged. (2.13) Determine whether programming of the necessary data has finished. If more than 128 bytes of data are to be programmed, specify FMPAR and FMPDR in 128byte units, and repeat steps (2.10) to (2.13). Increment the programming destination address by 128 bytes and update the programming data pointer correctly. If an address which has already been programmed is written to again, not only will a programming error occur, but also flash memory will be damaged. (2.14) After programming finishes, clear FKEY and specify software protection. If this LSI is restarted by a power-on reset immediately after user MAT programming has finished, secure a reset period (period of RES = 0) that is at least as long as the normal 100 s. Rev.2.0, 07/03, page 778 of 960 (3) Erasing Procedure in User Program Mode The procedures for download, initialization, and erasing are shown in figure 22.12. Start erasing procedure program Select on-chip program to be downloaded and set download destination by FTDAR Set FKEY to H'A5 After clearing VBR, set SCO to 1 and execute download Clear FKEY to 0 1 (3.1) Set FKEY to H'5A Set FEBS parameter Erasing JSR FTDAR setting+16 (3.2) (3.3) (3.4) No Download Erasing FPFR=0 ? Yes DPFR = 0? Clear FKEY and erasing error processing No Download error processing No Yes Required block erasing is completed? (3.5) (3.6) Set the FPEFEQ and FUBRA parameters Yes Clear FKEY to 0 Initialization Initialization JSR FTDAR setting+32 End erasing procedure program FPFR=0 ? No Yes Initialization error processing 1 Figure 22.12 Erasing Procedure The details of the erasing procedure are described below. The procedure program must be executed in an area other than the user MAT to be erased. Especially the part where the SCO bit in FCCS is set to 1 for downloading must be executed in onchip RAM. The area that can be executed in the steps of the user procedure program (on-chip RAM, user MAT, and external space) is shown in section 22.10.3, Storable Area for Procedure Program and Programming Data. For the downloaded on-chip program area, see the RAM map for programming/erasing in figure 22.10. Rev.2.0, 07/03, page 779 of 960 A single divided block is erased by one erasing processing. For block divisions, see figure 22.4. To erase two or more blocks, update the erase block number and perform the erasing processing for each block. (3.1) Select the on-chip program to be downloaded Set the EPVB bit in FECS to 1. Several programming/erasing programs cannot be selected at one time. If several programs are set, download is not performed and a download error is returned to the source select error detect (SS) bit in the DPFR parameter. Specify the start address of the download destination by FTDAR. The procedures to be carried out after setting FKEY, e.g. download and initialization, are the same as those in the programming procedure. For details, see the description in 22.5.2 (2) Programming Procedure in User Program Mode. (3.2) Set the FEBS parameter necessary for erasure Set the erase block number of the user MAT in the flash erase block select parameter (FEBS: general register R4). If a value other than an erase block number of the user MAT is set, no block is erased even though the erasing program is executed, and an error is returned to the return value parameter FPFR. (3.3) Erasure Similar to as in programming, there is an entry point of the erasing program in the area from (download start address set by FTDAR) + 16 bytes of on-chip RAM. The subroutine is called and erasing is executed by using the following steps. MOV.L JSR NOP #DLTOP+16,R1 @R1 ; Set entry address to R1 ; Call erasing routine The general registers other than R0L are saved in the erasing program. R0 is a return value of the FPFR parameter. Since the stack area is used in the erasing program, a stack area of maximum 128 bytes must be reserved in RAM. (3.4) The return value in the erasing program, FPFR (general register R0) is judged. (3.5) Determine whether erasure of the necessary blocks has finished. If more than one block is to be erased, update the FEBS parameter and repeat steps (3.2) to (3.5). Blocks that have already been erased can be erased again. (3.6) After erasure finishes, clear FKEY and specify software protection. If this LSI is restarted by a power-on reset immediately after user MAT programming has finished, secure a reset period (period of RES = 0) that is at least as long as the normal 100 s. Rev.2.0, 07/03, page 780 of 960 (4) Erasing and Programming Procedure in User Program Mode By changing the on-chip RAM address of the download destination in FTDAR, the erasing program and programming program can be downloaded to separate on-chip RAM areas. Figure 22.13 shows an example of repetitively executing RAM emulation, erasing, and programming. 1 Start procedure program Enter RAM emulation mode and tune data in on-chip RAM Emulation/Erasing/Programming Erasing program download Set FTDAR to H'02 (Specify H'FFFF7000 as download destination) Cancel RAM emulation mode Download erasing program Initialize erasing program Erase relevant block (execute erasing program) Programming program download Set FTDAR to H'03 (Specify H'FFFF7800 as download destination) Set FMPDR to H'FFFF6000 to program relevant block (execute programming program) Download programming program Initialize programming program Confirm operation End? Yes No 1 End procedure program Figure 22.13 Sample Procedure of Repeating RAM Emulation, Erasing, and Programming (Overview) In the above example, the erasing program and programming program are downloaded to areas excluding the 4 kbytes (H'FFFF6000 to H'FFFF6FFF) from the start of on-chip ROM. Download and initialization are performed only once at the beginning. In this kind of operation, note the following: * Be careful not to damage on-chip RAM with overlapped settings. In addition to the RAM emulation area, erasing program area, and programming program area, Rev.2.0, 07/03, page 781 of 960 areas for the user procedure programs, work area, and stack area are reserved in on-chip RAM. Do not make settings that will overwrite data in these areas. * Be sure to initialize both the erasing program and programming program. Initialization by setting the FPEFEQ and FUBRA parameters must be performed for both the erasing program and the programming program. Initialization must be executed for both entry addresses: (download start address for erasing program) + 32 bytes (H'FFFF7020 in this example) and (download start address for programming program) + 32 bytes (H'FFFF7820 in this example). 22.5.3 User Boot Mode This LSI has user boot mode which is initiated with different mode pin settings than those in user program mode or boot mode. User boot mode is a user-arbitrary boot mode, unlike boot mode that uses the on-chip SCI. Only the user MAT can be programmed/erased in user boot mode. Programming/erasing of the user boot MAT is only enabled in boot mode or programmer mode. (1) User Boot Mode Initiation For the mode pin settings to start up user boot mode, see table 22.1, Relationship between FWE and MD Pins and Operating Modes. When the reset start is executed in user boot mode, the check routine for flash-memory related registers runs. While the check routine is running, the RAM area about 1.2 kbytes from H'FFFF6800 is used by the routine and 4 bytes from H'FFFFDFFC is used as a stack area. NMI and all other interrupts cannot be accepted. Neither can the AUD be used in this period. This period is approximately 100 s while operating at an internal frequency of 40 MHz. Next, processing starts from the execution start address of the reset vector in the user boot MAT. At this point, H'AA is set to the flash MAT select register (FMATS) because the execution MAT is the user boot MAT. (2) User MAT Programming in User Boot Mode For programming the user MAT in user boot mode, additional processings made by setting FMATS are required: switching from user-boot-MAT selection state to user-MAT selection state, and switching back to user-boot-MAT selection state after programming completes. Figure 22.14 shows the procedure for programming the user MAT in user boot mode. Rev.2.0, 07/03, page 782 of 960 Start programming procedure program Select on-chip program to be downloaded and set download destination by FTDAR 1 MAT switchover Set FKEY to H'A5 After clearing VBR, set SCO to 1 and execute download Set FMATS to value other than H'AA to select user MAT User-boot-MAT selection state Download Set FKEY to H'A5 User-MAT selection state Clear FKEY to 0 Set parameter to R4 and R5 (FMPAR and FMPDR) DPFR=0 ? Yes No Programming Programming JSR FTDAR setting+16 FPFR=0 ? Download error processing Initialization Set the FPEFEQ and FUBRA parameters Initialization JSR FTDAR setting+32 FPFR=0 ? No Yes Clear FKEY and programming error processing* No Required data programming is completed? Yes No Clear FKEY to 0 Yes Initialization error processing 1 Set FMATS to H'AA to select user boot MAT End programming procedure program MAT switchover User-boot-MAT selection state Note: * The MAT must be switched by FMATS to perform the programming error processing in the user boot MAT. Figure 22.14 Procedure for Programming User MAT in User Boot Mode The difference between the programming procedures in user program mode and user boot mode is whether the MAT is switched or not as shown in figure 22.14. In user boot mode, the user boot MAT can be seen in the flash memory space with the user MAT hidden in the background. The user MAT and user boot MAT are switched only while the user MAT is being programmed. Because the user boot MAT is hidden while the user MAT is being programmed, the procedure program must be located in an area other than flash memory. After programming finishes, switch the MATs again to return to the first state. MAT switchover is enabled by writing a specific value to FMATS. However note that while the MATs are being switched, the LSI is in an unstable state, e.g. access to a MAT is not allowed until MAT switching is completely finished, and if an interrupt occurs, from which MAT the interrupt vector is read from is undetermined. Perform MAT switching in accordance with the description in section 22.8.1, Switching between User MAT and User Boot MAT. Rev.2.0, 07/03, page 783 of 960 Except for MAT switching, the programming procedure is the same as that in user program mode. The area that can be executed in the steps of the user procedure program (on-chip RAM, user MAT, and external space) is shown in section 22.10.3, Storable Area for Procedure Program and Programming Data. (3) User MAT Erasing in User Boot Mode For erasing the user MAT in user boot mode, additional processings made by setting FMATS are required: switching from user-boot-MAT selection state to user-MAT selection state, and switching back to user-boot-MAT selection state after erasing completes. Figure 22.15 shows the procedure for erasing the user MAT in user boot mode. Start erasing procedure program Select on-chip program to be downloaded and set download destination by FTDAR 1 MAT switchover Set FKEY to H'A5 Set FMATS to value other than H'AA to select user MAT Download User-boot-MAT selection state After clearing VBR, set SCO to 1 and execute download Set FKEY to H'5A User-MAT selection state Clear FKEY to 0 Set FEBS parameter Programming JSR FTDAR setting+16 FPFR=0 ? DPFR=0 ? Yes No Download error processing Erasing Initialization Set the FPEFEQ and FUBRA parameters Initialization JSR FTDAR setting+32 FPFR=0 ? No No Yes Clear FKEY and erasing error processing* Required block erasing is completed? Yes No Clear FKEY to 0 Yes Initialization error processing 1 Set FMATS to H'AA to select user boot MAT End erasing procedure program MAT switchover User-boot-MAT selection state Note: * The MAT must be switched by FMATS to perform the erasing error processing in the user boot MAT. Figure 22.15 Procedure for Erasing User MAT in User Boot Mode The difference between the erasing procedures in user program mode and user boot mode depends on whether the MAT is switched or not as shown in figure 22.15. Rev.2.0, 07/03, page 784 of 960 MAT switching is enabled by writing a specific value to FMATS. However note that while the MATs are being switched, the LSI is in an unstable state, e.g. access to a MAT is not allowed until MAT switching is completed finished, and if an interrupt occurs, from which MAT the interrupt vector is read from is undetermined. Perform MAT switching in accordance with the description in section 22.8.1, Switching between User MAT and User Boot MAT. Except for MAT switching, the erasing procedure is the same as that in user program mode. The area that can be executed in the steps of the user procedure program (on-chip RAM, user MAT, and external space) is shown in section 22.10.3, Storable Area for Procedure Program and Programming Data. 22.6 Protection There are three kinds of flash memory program/erase protection: hardware, software, and error protection. 22.6.1 Hardware Protection Programming and erasing of flash memory is forcibly disabled or suspended by hardware protection. In this state, the downloading of an on-chip program and initialization of the flash memory are possible. However, an activated program for programming or erasure cannot program or erase locations in a user MAT, and the error in programming/erasing is reported in the FPFR parameter. Rev.2.0, 07/03, page 785 of 960 Table 22.9 Hardware Protection Function to be Protected Item FWE-pin protection Description The input of a low-level signal on the FWE pin clears the FWE bit of FCCS and the LSI enters a programming/erasing-protected state. * A power-on reset (including a poweron reset by the WDT) and entry to standby mode initializes the programming/erasing interface registers and the LSI enters a programming/erasing-protected state. Resetting by means of the RES pin after power is initially supplied will not make the LSI enter the reset state unless the RES pin is held low until oscillation has stabilized. In the case of a reset during operation, hold the RES pin low for the RES pulse width that is specified in the section on AC characteristics. If the LSI is reset during programming or erasure, data in the flash memory is not guaranteed. In this case, execute erasure and then execute programming again. Download -- Programming/ Erasure O Reset/standby protection O O * 22.6.2 Software Protection Software protection is set up in any of three ways: by disabling the downloading of on-chip programs for programming and erasing, by means of a key code, and by the RAM emulation register (RAMER). Rev.2.0, 07/03, page 786 of 960 Table 22.10 Software Protection Function to be Protected Item Protection by the SCO bit Description Clearing the SCO bit in FCCS disables downloading of the programming/erasing program, thus making the LSI enter a programming/erasing-protected state. Downloading and programming/erasing are disabled unless the required key code is written in FKEY. Different key codes are used for downloading and for programming/erasing. Setting the RAMS bit in RAMER to 1 makes the LSI enter a programming/erasing-protected state. Download O Programming/ Erasure O Protection by FKEY O O Emulation protection O O 22.6.3 Error Protection Error protection is a mechanism for aborting programming or erasure when an error occurs, in the form of the microcomputer getting out of control during programming/erasing of the flash memory or operations that are not in accordance with the established procedures for programming/erasing. Aborting programming or erasure in such cases prevents damage to the flash memory due to excessive programming or erasing. If the microcomputer malfunctions during programming/erasing of the flash memory, the FLER bit in FCCS is set to 1 and the LSI enters the error protection state, thus aborting programming or erasure. The FLER bit is set to 1 in the following conditions: * When the relevant block area of flash memory is read during programming/erasing (including a vector read or an instruction fetch) * When a SLEEP instruction (including software standby mode) is executed during programming/erasing Error protection is cancelled (FLER bit is cleared) only by a power-on reset or in hardwarestandby mode. Note that the reset signal should only be released after providing a reset input over a period longer than the normal 100 s. Since high voltages are applied during programming/erasing of the flash memory, some voltage may still remain even after the error protection state has been entered. For Rev.2.0, 07/03, page 787 of 960 this reason, it is necessary to reduce the risk of damage to the flash memory by extending the reset period so that the charge is released. The state-transition diagram in figure 22.16 shows transitions to and from the error protection state. Program mode Erase mode Read disabled Programming/erasing enabled FLER=0 = 0 or =0 Reset or standby (Hardware protection) Read enabled Programming/erasing disabled FLER=0 Er ror (S Error occurred cu oft rred wa re sta oc =0 or =0 =0 or =0 Programming/erasing interface register is in its initial state. nd by ) Error protection mode (Software standby) Error protection mode Read enabled Programming/erasing disabled FLER=1 Software standby mode Read disabled Cancel Programming/erasing disabled software standby mode FLER=1 Programming/erasing interface register is in its initial state. Figure 22.16 Transitions to and from Error Protection State Rev.2.0, 07/03, page 788 of 960 22.7 Flash Memory Emulation in RAM To provide real-time emulation in RAM of data that is to be written to the flash memory, a part of the RAM can be overlaid on an area of flash memory (user MAT) that has been specified by the RAM emulation register (RAMER). After the RAMER setting is made, the RAM is accessible in both the user MAT area and as the RAM area that has been overlaid on the user MAT area. Such emulation is possible in user mode and user program mode. Figure 22.17 shows an example of the emulation of realtime programming of the user MAT area. Start of emulation program Set RAMER Write the data for tuning to the overlapped RAM area Execute application program No Tuning OK? Yes Cancel RAMER setting Program the emulation block in the user MAT End of emulation program Figure 22.17 Emulation of Flash Memory in RAM Rev.2.0, 07/03, page 789 of 960 This area is accessible as both a RAM area and as a flash memory area. H'00000 H'01000 H'02000 H'03000 H'04000 H'05000 H'06000 H'07000 H'08000 EB0 EB1 EB2 EB3 EB4 EB5 EB6 EB7 H'FFFF6000 H'FFFF6FFF Flash memory (user MAT) On-chip RAM EB8 to EB15 H'7FFFF H'FFFFDFFF Figure 22.18 Example of Overlapped RAM Operation Figure 22.18 shows an example of an overlap on block area EB0 of the flash memory. Emulation is possible for a single area selected from among the eight areas, from EB0 to EB7, of the user MAT. The area is selected by the setting of the RAM2 to RAM0 bits in RAMER. (1) To overlap a part of the RAM on area EB0, to allow realtime programming of the data for this area, set the RAMS bit in RAMER to 1, and each of the RAM2 to RAM0 bits to 0. (2) Realtime programming is carried out using the overlaid area of RAM. In programming or erasing the user MAT, it is necessary to run a program that implements a series of procedural steps, including the downloading of an on-chip program. In this process, set the download area with FTDAR so that the overlaid RAM area and the area where the on-chip program is to be downloaded do not overlap. The initial setting (H'00) of FTDAR causes the tuned data area to overlap with the download area. When using the initial setting of FTDAR, the data that is to be programmed must be saved beforehand in an area that is not used by the system. Figure 22.19 shows an example of programming data that has been emulated to the EB0 area in the user MAT. Rev.2.0, 07/03, page 790 of 960 H'00000 H'01000 H'02000 H'03000 H'04000 H'05000 H'06000 H'07000 H'08000 EB0 EB1 EB2 EB3 EB4 EB5 EB6 EB7 (1) Cancel the emulation mode. (2) Transfer the user programming/erasing procedure program. (3) Download the on-chip programming/ erasing program to the destination set by FTDAR without overlapping the tuned data area. (4) Execute programming after erasing. Tuned data area Flash memory (user MAT) EB8 to EB15 H'FFFF6000 H'FFFF6FFF FTDAR setting Download area Programming/erasing procedure program area H'FFFFDFFF H'7FFFF Figure 22.19 Programming of Tuned Data 1. After the data to be programmed has fixed values, clear the RAMS bit to 0 to cancel the overlap of RAM. Emulation mode is canceled and emulation protection is also cleared. 2. Transfer the user programming/erasing procedure program to RAM. 3. Run the programming/erasing procedure program in RAM and download the on-chip programming/erasing program. Specify the download start address with FTDAR so that the tuned data area does not overlap with the download area. 4. When the EB0 area of the user MAT has not been erased, erasing must be performed before programming. Set the parameters FMPAR and FMPDR so that the tuned data is designated, and execute programming. Note: Setting the RAMS bit to 1 puts all the blocks in flash memory in the programming/erasing-protected state regardless of the values of the RAM2 to RAM0 bits (emulation protection). Clear the RAMS bit to 0 before actual programming or erasure. RAM emulation can be performed when the user boot MAT is selected. However, programming/erasing user boot MAT can be performed only in boot mode or program mode. Rev.2.0, 07/03, page 791 of 960 22.8 22.8.1 Usage Notes Switching between User MAT and User Boot MAT It is possible to switch between the user MAT and user boot MAT. However, the following procedure is required because these MATs are allocated to address 0. (Switching to the user boot MAT disables programming and erasing. Programming of the user boot MAT must take place in boot mode or programmer mode.) (1) MAT switching by FMATS should always be executed from the on-chip RAM. The SH microcomputer prefetches execution instructions. Therefore, a switchover during program execution in the user MAT causes an instruction code in the user MAT to be prefetched or an instruction in the newly selected user boot MAT to be prefetched, thus resulting in unstable operation. (2) To ensure that the MAT that has been switched to is accessible, execute four NOP instructions in on-chip RAM immediately after writing to FMATS of on-chip RAM (this prevents access to the flash memory during MAT switching). (3) If an interrupt occurs during switching, there is no guarantee of which memory MAT is being accessed. Always mask the maskable interrupts before switching MATs. In addition, configuring the system so that NMI interrupts do not occur during MAT switching is recommended. (4) After the MATs have been switched, take care because the interrupt vector table will also have been switched. If the same interrupt processings are to be executed before and after MAT switching or interrupt requests cannot be disabled, transfer the interrupt processing routine to on-chip RAM, and use the VBR setting to place the interrupt vector table in on chip RAM. In this case, make sure the VBR setting change does not conflict with the interrupt occurrence. (5) Memory sizes of the user MAT and user boot MAT are different. When accessing the user boot MAT, do not access addresses exceeding the 8-kbyte memory space. If access goes beyond the 8-kbyte space, the values read are undefined. Rev.2.0, 07/03, page 792 of 960 Procedure for switching to the user boot MAT Procedure for switching to the user MAT Procedure for switching to the user boot MAT (1) Mask interrupts. (2) Write H'AA to FMATS. (3) Execute four NOP instructions before accessing the user boot MAT. Procedure for switching to the user MAT (1) Mask interrupts. (2) Write a value other than H'AA to FMATS. (3) Execute four NOP instructions before accessing the user MAT. Figure 22.20 Switching between User MAT and User Boot MAT 22.8.2 Interrupts during Programming/Erasing (1) Download of On-Chip Program (1.1) VBR setting change Before downloading the on-chip program, VBR must be set to H'00000000 (initial value). If VBR is set to a value other than the initial value, the interrupt vector table is placed in the user MAT (FMATS is not H'AA) or the user boot MAT (FMATS is H'AA) on initialization of VBR. When VBR setting change conflicts with interrupt occurrence, whether the vector table before or after VBR is changed is referenced may cause an error. Therefore, for cases where VBR setting change may conflict with interrupt occurrence, prepare a vector table to be referenced when VBR is H'00000000 at the start of the user MAT or user boot MAT. (1.2) SCO download request and interrupt request Download of the on-chip programming/erasing program that is initiated by setting the SCO bit in FCCS to 1 generates a particular interrupt processing accompanied by MAT switchover. Operation when the SCO download request and interrupt request conflicts is described below. 1. Contention between SCO download request and interrupt request Figure 22.21 shows the timing of contention between execution of the instruction that sets the SCO bit in FCCS to 1 and interrupt acceptance. Rev.2.0, 07/03, page 793 of 960 CPU cycle CPU operation for instruction that sets SCO bit to 1 n Fetch n+1 Decoding n+2 Execution n+3 Execution n+4 Execution Interrupt acceptance (a) (b) (c) (a) When the interrupt is accepted at or before the (n + 1) cycle After the interrupt processing completes, the SCO bit is set to 1 and download is executed. (b) When the interrupt is accepted at the (n + 2) cycle The interrupt conflicts with the SCO download request. For details on operation in this case, see 2. Operation when contention occurs. (c) When the interrupt is accepted at or after the (N + 3) cycle The SCO download request occurs prior to the interrupt request, and download is executed. During download, no other interrupt processing can be handled. If an interrupt is still being requested after download completes, the interrupt processing starts. For details on interrupt requests during download, see 3. Interrupt requests generated during download. Figure 22.21 Timing of Contention between SCO Download Request and Interrupt Request 2. Operation when contention occurs Operation differs according to the type of interrupt with which the SCO download request has conflicted. NMI, UBC, and H-UDI interrupt requests Operation for when these interrupts conflict with the SCO download request is described below. Main processing SCO download processing Contention between SCO and interrupt Interrupt processing, e.g. NMI Figure 22.22 Contention between Interrupts (e.g. NMI) Rev.2.0, 07/03, page 794 of 960 * The NMI, UBC, or H-UDI interrupt processing is started. Processing proceeds up to the point where SR and PC are saved, the vector is fetched, and the start instruction of the interrupt processing routine is fetched. * At this point, the SCO download request with a higher priority occurs. The SCO download processing is started. * After the download processing has ended, the interrupt processing routine (e.g. NMI) that was in the middle of execution resumes from the point of fetching the start instruction of the interrupt processing routine. * The interrupt processing routine is ended, and execution returns to the main processing. IRQ and on-chip peripheral module interrupt requests Operation for when these interrupts conflict with the SCO download request is described below. Main processing SCO download processing Contention between SCO and interrupt Interrupt processing, e.g. IRQ Figure 22.23 Contention between Interrupts (e.g. IRQ) * An IRQ interrupt or interrupt from an on-chip peripheral module is replaced with the SCO download request and download is executed. * If the IRQ or on-chip peripheral module interrupt is still being requested when the download processing has ended, the interrupt processing is executed. If these interrupt requests have been canceled, execution returns to the main processing. * An interrupt request is canceled when the IRQ signal, for which low-level detection is set, has been driven high before download ends. Also refer to the description below (3. Interrupt requests generated during download). 3. Interrupt requests generated during download Rev.2.0, 07/03, page 795 of 960 Even though an interrupt is requested during SCO download, the interrupt processing is not executed until download ends. Note that interrupt requests are basically retained, so that on completion of download, the interrupt processing starts. When more than one type of interrupts are requested, their priorities are judged by the interrupt controller (INTC), and execution starts from the interrupt processing with higher priority. NMI, UBC, and H-UDI interrupt requests When these interrupt requests occur during SCO download, their interrupt sources are retained. IRQ interrupt request Falling-edge detection or low-level detection can be specified for an IRQ interrupt. * Falling-edge detection is selected: When the falling-edge of IRQ is detected during SCO download, the interrupt source is retained. * Low-level detection is selected: When the low-level of IRQ is detected during SCO download, if the IRQ remains low when download ends, the interrupt processing starts. If the IRQ is high when download ends, the interrupt source will be canceled. On-chip peripheral module interrupt request An interrupt from an on-chip peripheral module is requested by input of the specified level. Since the interrupt signal continues to be output unless the interrupt flag is cleared, the interrupt source is retained. (2) Interrupts during programming/erasing Though an interrupt processing can be executed at realtime during programming/erasing of the downloaded on-chip program, the following limitations and notes are applied. 1. When flash memory is being programmed or erased, both the user MAT and user boot MAT cannot be accessed. Prepare the interrupt vector table and interrupt processing routine in onchip RAM or external memory. Make sure the flash memory being programmed or erased is not accessed by the interrupt processing routine. If flash memory is read, the read values are not guaranteed. If the relevant bank in flash memory that is being programmed or erased is accessed, the error protection state is entered, and programming or erasing is aborted. If a bank other than the relevant bank is accessed, the error protection state is not entered but the read values are not guaranteed. 2. Do not rewrite the program data specified by the FMPDR parameter. If new program data is to provided by the interrupt processing, temporarily save the new program data in another area. After confirming the completion of programming, save the new program data in the area specified by FMPDR or change the setting in FMPDR to indicated the other area in which the new program data was temporarily saved. 3. Make sure the interrupt processing routine does not rewrite the contents of the flash-memory related registers or data in the downloaded on-chip program area. During the interrupt processing, do not simultaneously perform RAM emulation, download of the on-chip program by an SCO request, or programming/erasing. 4. At the beginning of the interrupt processing routine, save the CPU register contents. Before returning from the interrupt processing, write the saved contents in the CPU registers again. Rev.2.0, 07/03, page 796 of 960 5. When a transition is made to sleep mode or software standby mode in the interrupt processing routine, the error protection state is entered and programming/erasing is aborted. If a transition is made to the reset state, the reset signal should only be released after providing a reset input over a period longer than the normal 100 s to reduce the damage to flash memory. 22.8.3 Other Notes 1. Download time of on-chip program The programming program that includes the initialization routine and the erasing program that includes the initialization routine are each 2 kbytes or less. Accordingly, when the CPU clock frequency is 40 MHz, the download for each program takes approximately 75 s at maximum. 2. User branch processing intervals The intervals for executing the user branch processing differs in programming and erasing. The processing phase also differs. Table 22.11 lists the maximum and minimum intervals for initiating the user branch processing when the CPU clock frequency is 40 MHz. Table 22.11 Initiation Intervals of User Branch Processing Processing Name Programming Erasing Maximum Interval Approximately 1 ms Approximately 5 ms Minimum Interval Approximately 19 s Approximately 19 s Table 22.12 lists the maximum and minimum periods until the user branch processing is initiated when the CPU clock frequency is 40 MHz. Table 22.12 Required Period for Initiating User Branch Processing Processing Programming Erasing Max. Approximately 113 s Approximately 85 s Min. Approximately 113 s Approximately 45 s 3. Write to flash-memory related registers by AUD or DMAC While an instruction in on-chip RAM is being executed, the AUD or DMAC can write to the SCO bit in FCCS that is used for a download request or FMATS that is used for MAT switching. Make sure that these registers are not accidentally written to, otherwise an on-chip program may be downloaded and damage RAM or a MAT switchover may occur and the CPU get out of control. 4. State in which AUD operation is disabled and interrupts are ignored In the following modes or period, the AUD is in module standby mode and cannot operate. The NMI or maskable interrupt requests are ignored; they are not executed and the interrupt sources are not retained. Rev.2.0, 07/03, page 797 of 960 Boot mode Programmer mode Checking the flash-memory related registers immediately after user boot mode is initiated (Approximately 100 s when operation with internal frequency of 40 MHz is carried out after the reset signal is released.) 5. Compatibility with programming/erasing program of conventional F-ZTAT SH microcomputer A programming/erasing program for flash memory used in the conventional F-ZTAT SH microcomputer which does not support download of the on-chip program by a SCO transfer request cannot run in this LSI. Be sure to download the on-chip program to execute programming/erasing of flash memory in this LSI. 6. Monitoring runaway by WDT Unlike the conventional F-ZTAT SH microcomputer, no countermeasures are available for a runaway by WDT during programming/erasing by the downloaded on-chip program. Prepare countermeasures (e.g. use of the user branch routine and periodic timer interrupts) for WDT while taking the programming/erasing time into consideration as required. 22.9 Programmer Mode Along with its on-board programming mode, this LSI also has programmer mode as another mode for writing and erasing of programs and data. Programmer mode supports memory-read mode, auto-program mode, auto-erase mode, and status-read mode. Programming/erasing is possible on the user MAT and user boot MAT. A status-polling system is adopted for operation in auto-program mode, auto-erase mode, and status-read mode. In status-read mode, details of the system's internal state are output after execution of automatic programming or automatic erasure. In programmer mode, set the mode pins as shown in table 22.13, and provide a 6-MHz input-clock signal. Rev.2.0, 07/03, page 798 of 960 Table 22.13 Programmer Mode Pin Settings Pin Name Mode pins: MD2, MD1, and MD0 FWE RES EXTAL, XTAL, PLLVCC, PLLVSS, PLLCAP VCL Settings 0, 1, 1 High-level input (automatic programming and automatic erasure) Power-on reset circuit Oscillation circuit and PLL circuit Internal stepdown stabilization capacitor 22.9.1 Pin Arrangement of Socket Adapter Attach the socket adapter to the LSI in the way shown in figure 22.25. This allows conversion to 40 pins. Figure 22.24 shows the memory mapping of on-chip ROM, and figure 22.25 shows the arrangement of the socket adapter's pins. Address in MCU mode H'0000,0000 Address in PROM mode H'0,0000 Address in MCU mode H'0000,0000 Address in PROM mode H'0,0000 On-chip ROM space (user boot MAT) 8 kbytes H'0000,1FFF H'0,1FFF On-chip ROM space (user MAT) 512 kbytes H'0007,FFFF H'7,FFFF Figure 22.24 Mapping of On-Chip Flash Memory Rev.2.0, 07/03, page 799 of 960 SH7055SF Pin No. 7 8 9 10 12 14 15 16 17 18 19 21 23 24 25 26 27 28 29 31 63 64 65 66 67 68 69 71 218 230 226 56 11,20,37,39,42,43,46,49,52,55, 57,59,70,75,83,100,101,119, 120,128,139,148,172,187,194, 203,212,237,247 13,22,32,41,44,47,50,54,72,77, 84,85,99,121,126,141,150,163, 174,185,196,205,214,227,239, 249 58 53 51 60 61 62 30,161,225 Other FWE Vcc Pin Name A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 A16 A17 A18 A19 D0 D1 D2 D3 D4 D5 D6 D7 Socket Adapter (40-Pin Conversion) HN27C4096HG (40 pins) Pin No. Pin Name 21 22 23 24 25 26 27 28 29 31 32 33 34 35 36 37 38 39 10 9 19 18 17 16 15 14 13 12 2 20 3 4 1,40 11,30 5,6,7 8 FWE Vcc Vss NC A20 A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 A16 A17 A18 A19 I/O0 I/O1 I/O2 I/O3 I/O4 I/O5 I/O6 I/O7 Vss Power-on reset circuit XTAL EXTAL PLLVcc PLLCAP PLLVss VCL N.C.(OPEN) Oscillator circuit PLL circuit Capacitor Figure 22.25 Pin Arrangement of Socket Adapter Rev.2.0, 07/03, page 800 of 960 22.9.2 Programmer Mode Operation Table 22.14 shows the settings for the operating modes of programmer mode, and table 22.15 lists the commands used in programmer mode. The following sections provide detailed information on each mode. * Memory-read mode Supports reading from the user MAT or user boot MAT in bytes. * Auto-program mode Supports the simultaneous programming of the user MAT and user boot MAT in 128-byte units. Status polling is used to confirm the end of automatic programming. * Auto-erase mode Supports only automatic erasure of the entire user MAT or user boot MAT. Status polling is used to confirm the end of automatic erasure. * Status-read mode Status polling is used with automatic programming and automatic erasure. Normal completion can be detected by reading the signal on the I/O6 pin. In status-read mode, error information is output when an error has occurred. Table 22.14 Settings for Each Operating Mode of Programmer Mode Pin Name Mode Read Output disable Command write Chip disable FWE H or L H or L H or L H or L CE L L L H OE L H H X WE H H L X I/O7 to I/O0 Data output Hi-Z Data input Hi-Z A19 to A0 Ain X Ain* X Notes: 1. The chip-disable mode is not a standby state; internally, it is an operational state. 2. To write commands when making a transition to auto-program or auto-erase mode, input a high-level signal on the FWE pin. * Ain indicates that there is also an address input in auto-program mode. Rev.2.0, 07/03, page 801 of 960 Table 22.15 Commands in Programmer Mode 1st Cycle Memory Number MAT to be of Cycles Accessed 1+n User MAT User boot MAT 129 User MAT User boot MAT 2 User MAT User boot MAT 2 2nd Cycle Command Memory-read mode Mode Write Write Write Write Write Write Address X X X X X X X Command H'00 H'05 H'40 H'45 H'20 H'25 H'71 Mode Read Address RA Data Dout Auto-program mode Write WA Din Auto-erase mode Write X H'20 H'25 Status-read mode Common to Write both MATs Write X H'71 Notes 1. In auto-program mode, 129 cycles are required in command writing because of the simultaneous 128-byte write. 2. In memory read mode, the number of cycles varies with the number of address writing cycles (n). 3. In an automatic erasure command, input the same command code for the 1st and 2nd cycles (for erasing of the user boot MAT, input H'25 for the 1st and 2nd cycles). 22.9.3 Memory-Read Mode (1) On completion of automatic programming, automatic erasure, or status read, the LSI enters a command input wait state. So, to read the contents of memory after these operations, issue the command to transit to memory-read mode before reading from the memory. (2) In memory-read mode, the writing of commands is possible in the same way as in command input wait state. (3) After entering memory-read mode, continuous reading is possible. (4) After power has first been supplied, the LSI enters memory-read mode of the user MAP. For the AC characteristics in memory read mode, see section 22.10.2, AC Characteristics and Timing in programmer Mode. Rev.2.0, 07/03, page 802 of 960 22.9.4 Auto-Program Mode (1) In auto-program mode, programming is in 128-byte units. That is, 128 bytes of data are transferred in succession. (2) Even in the programming of less than 128 bytes, 128 bytes of data must be transferred. H'FF should be written to those addresses that are unnecessarily written to. (3) Set the lower seven bits of the address to be transferred to low level. Inputting an invalid address will result in a programming error, although processing will proceed to the memoryprogramming operation. (4) The memory address is transferred in the 2nd cycle. Do not transfer addresses in the 3rd or later cycles. (5) Do not issue commands while programming is in progress. (6) When programming, execute automatic programming once for each 128-byte block of addresses. Programming the block at an address where programming has already been performed is not possible. (7) To confirm the end of automatic programming, check the signal on the I/O6 pin. Confirmation in status-read mode is also possible (status polling of the I/O7 pin is used to check the end status of automatic programming). (8) Status-polling information on the I/O6 and I/O7 pins is retained until the next command is written. As long as no command is written, the information is made readable by enabling CE and OE. For the AC characteristics in auto-program mode, see section 22.10.2, AC Characteristics and Timing in programmer Mode. 22.9.5 Auto-Erase Mode (1) Auto-erase mode only supports erasing of the entire memory. (2) Do not perform command writing while auto erasing is in progress. (3) To confirm the end of automatic erasure, check the signal on the I/O6 pin. Confirmation in the status-read mode is also possible (status polling of the I/O7 pin is used to check the end status of automatic erasure). (4) Status polling information on the I/O6 and I/O7 pins is retained until the next command writing. As long as no command is written, the information is made readable by enabling CE and OE. For the AC characteristics in auto-erase mode, see section 22.10.2, AC Characteristics and Timing in programmer Mode. Rev.2.0, 07/03, page 803 of 960 22.9.6 Status-Read Mode (1) Status-read mode is used to determine the type of an abnormal termination. Use this mode when automatic programming or automatic erasure ends abnormally. (2) The return code is retained until writing of a command that selects a mode other than statusread mode. Table 22.16 lists the return codes of status-read mode. For the AC characteristics in status-read mode, see section 22.10.2, AC Characteristics and Timing in programmer Mode. Table 22.16 Return Codes of Status-Read Mode Pin Name Attribute I/O7 Normal end indicator 0 Normal end: 0 Abnorma l end: 1 I/O6 Command error 0 Command error: 1 Otherwise :0 I/O5 Programming error 0 Programming error: 1 Otherwise: 0 I/O4 Erasure error 0 Erasure error:1 Otherwise :0 I/O3 -- I/O2 -- I/O1 Programming or erase count exceeded 0 Count exceeded: 1 Otherwise: 0 I/O0 Invalid address error 0 Invalid address error: 1 Otherwise :0 Initial value Indication 0 -- 0 -- Note: I/O2 and I/O3 are undefined pins. 22.9.7 Status Polling (1) The I/O7 status-polling output is a flag that indicates the operating status in auto-program or auto-erase mode. (2) The I/O6 status-polling output is a flag that indicates normal/abnormal end of auto-program or auto-erase mode. Table 22.17 Truth Table of Status-Polling Output Pin Name I/O7 I/O6 I/O0 to I/O5 In Progress 0 0 0 Abnormal End 1 0 0 -- 0 1 0 Normal End 1 1 0 Rev.2.0, 07/03, page 804 of 960 22.9.8 Time Taken in Transition to Programmer Mode Until oscillation has stabilized and while programmer mode is being set up, the LSI is unable to accept commands. After the programmer-mode setup time has elapsed, the LSI enters memoryread mode. For details, see section 22.10.2, AC Characteristics and Timing in Programmer Mode. 22.9.9 Notes on Programming in Programmer Mode (1) When programming addresses which have previously been programmed, apply auto-erasing before auto-programming. (2) When using programmer mode to program a chip that has been programmed/erased in an onboard programming mode, auto-erasing before auto-programming is recommended. (3) Do not take the chip out of the PROM programmer or reset the chip during programming or erasure. Flash memory is susceptible to permanent damage since a high voltage is being applied during the programming/erasing. When the reset signal is accidentally input to the chip, the period in the reset state until the reset signal is released should be longer than the normal 100 s. Notes: 1. The flash memory is initially in the erased state when the device is shipped by Renesas. For other chips for which the history of erasure is unknown, auto-erasing as a check and supplement for the initialization (erase) level is recommended. 2. Automatic programming to a single address block can only be performed once. Additional programming to an address block that has already been programmed is not allowed. Rev.2.0, 07/03, page 805 of 960 22.10 Further Information 22.10.1 Serial Communication Interface Specification for Boot Mode Initiating boot mode enables the boot program to communicate with the host by using the on-chip SCI. The serial communication interface specifications are shown below. * Status The boot program has three states. (1) Bit-rate-adjustment state In this state, the boot program adjusts the bit rate to communicate with the host. Initiating boot mode enables starting of the boot program and entry to the bit-rate-adjustment state. The program receives the command from the host to adjust the bit rate. After adjusting the bit rate, the program enters the inquiry/selection state. (2) Inquiry/Selection state In this state, the boot program responds to inquiry commands from the host. The device name, clock mode, and bit rate are selected. After selection of these settings, the program is made to enter the programming/erasing state by the command for a transition to the programming/erasing state. The boot program transfers the erasure program to RAM and erases the user MATs and user boot MATs before the transition. (3) Programming/erasing state Programming and erasure by the boot program take place in this state. The boot program is made to transfer the programming/erasing program to RAM by commands from the host. Sum checks and blank checks are executed by sending these commands from the host. These boot program states are shown in figure 22.26. Rev.2.0, 07/03, page 806 of 960 Reset Bit-rate-adjustment state Bit rate adjustment Inquiry/Selection state Inquiry/Selection wait Inquiry Inquiry processing Transition to programming/ erasing state Selection Selection processing Programming/Erasing state User MAT/User boot MAT erasing processing Programming/Erasing selection wait Programming Programming processing Erasing Erasing processing Check Check processing Figure 22.26 Boot Program Processing Flow * Bit-rate-adjustment state The bit rate is calculated by measuring the period of transfer of a low-level byte (H'00) from the host. The bit rate can be changed by the command for a new bit rate selection. After the bit rate has been adjusted, the boot program enters the inquiry/selection state. The bit-rateadjustment sequence is shown in figure 22.27. Rev.2.0, 07/03, page 807 of 960 Host H'00 (30 times maximum) Boot Program Measuring the 1-bit length H'00 (Completion of adjustment) H'55 H'E6 (Response to boot) H'FF (Error) Figure 22.27 Bit-Rate-Adjustment Sequence * Communications protocol After adjustment of the bit rate, the protocol for serial communications between the host and the boot program is as shown below. (1) One-byte commands and one-byte responses These commands and responses are comprised of a single byte. These consists of the inquiries and ACK for successful completion. (2) n-byte commands or n-byte responses These commands and responses are comprised of n bytes of data. These are selections and responses to inquiries. The amount of programming data is not included under this heading because it is determined in another command. (3) Error response The error response is a response to inquiries. It consists of an error response and an error code and which take up two bytes. (4) Programming of 128 bytes The size is not specified in commands. The data size is indicated in response to the programming unit inquiry. (5) Memory read response This response consists of four bytes of data. Rev.2.0, 07/03, page 808 of 960 1-byte command or 1-byte response n-byte command or n-byte response Command or response Data Data size Command or response Checksum Error response Error code Error response 128-byte programming Address Command Data (n bytes) Checksum Memory read response Data size Response Data Checksum Figure 22.28 Communications Protocol Format Command (one byte): Commands including inquiries, selection, programming, erasing, and checking Response (one byte): Response to an inquiry Size (one or two bytes): The amount of data for transmission excluding the command, amount of data, and checksum Data (n bytes): Detailed data of a command or response Checksum (one byte): The checksum is calculated so that the total of all values from the command byte to the SUM byte becomes H'00. Error Response (one byte): Error response to a command Error Code (one byte): Type of the error Address (four bytes): Address for programming Data (n bytes): Data to be programmed. n is indicated in the response to the programming unit inquiry. Data Size (four bytes): Four-byte response to a memory read * Inquiry/Selection State The boot program returns information from the flash memory in response to the host's inquiry commands and sets the device code, clock mode, and bit rate in response to the host's selection command. Table 22.18 lists the inquiry and selection commands. Rev.2.0, 07/03, page 809 of 960 Table 22.18 Inquiry and Selection Commands Command H'20 H'10 H'21 H'11 H'22 Command Name Supported Device Inquiry Device Selection Clock Mode Inquiry Clock Mode Selection Multiplication Ratio Inquiry Description Inquiry regarding device codes and product names of F-ZTAT Selection of device code Inquiry regarding numbers of clock modes and values of each mode Indication of the selected clock mode Inquiry regarding the number of clock types, the number of multiplication/division ratios, and the multiplication/division ratios Inquiry regarding the maximum and minimum values of the main clock and peripheral clocks Inquiry regarding the number of user boot MATs and the start and last addresses of each MAT Inquiry regarding the a number of user MATs and the start and last addresses of each MAT Inquiry regarding the number of blocks and the start and last addresses of each block Inquiry regarding the unit of programming data Inquiry into whether or not simultaneous two-MAT programming is allowed Selection of new bit rate Erasing of user MAT and user boot MAT, and entry to programming/erasing state Inquiry into the operation status of the boot program H'23 Operating Clock Frequency Inquiry H'24 User Boot MAT Information Inquiry H'25 User MAT Information Inquiry H'26 Block for Erasing Information Inquiry H'27 H'28 H'3F H'40 Programming Unit Inquiry Two-MAT Simultaneous Programming Information Inquiry New Bit Rate Selection Transition to Programming/Erasing State Boot Program Status Inquiry H'4F The selection commands, which are device selection (H'10), clock mode selection (H'11), and new bit rate selection (H'3F), should be sent from the host in this order. These commands are certainly required. When two or more selection commands are sent at once, the last command will be valid. All of these commands, except for the boot program status inquiry command (H'4F), will be valid until the boot program receives the programming/erasing transition (H'40). The host can choose the needed commands out of the commands and inquiries listed above. The boot program status Rev.2.0, 07/03, page 810 of 960 inquiry command (H'4F) is valid after the boot program has received the programming/erasing transition command (H'40). (1) Supported device inquiry The boot program will return the device codes of supported devices in response to the supported device inquiry. Command H'20 Command: H'20 (one byte): Inquiry regarding supported devices Response H'30 Number of characters ... SUM Size Number of devices Product name Device code Response: H'30 (one byte): Response to the supported device inquiry Size (one byte): Number of bytes to be transmitted, excluding the command, amount of data, and checksum, that is, the amount of data consists of the product names, the number of devices, characters, and device codes Number of devices (one byte): Number of device types supported by the boot program Number of characters (one byte): Number of characters in the device code and boot program's name Device code (four bytes): Supporting product (ASCII code) Product name (n bytes): Type name of the boot program (ASCII code) SUM (one byte): Checksum The checksum is calculated so that the total number of all values from the command byte to the SUM byte becomes H'00. (2) Device Selection The boot program will set the supported device to the specified device code. The program will return the selected device code in response to the inquiry after this setting has been made. Command H'10 Size Device code SUM Command: H'10 (one byte): Device selection Size (one byte): Number of characters in the device code (fixed at 2) Device code (four bytes): Device code returned in response to the supported device inquiry (ASCII code) SUM (one byte): Checksum Response H'06 Response: H'06, (one byte): Response to the device selection command ACK will be returned when the device code matches. Rev.2.0, 07/03, page 811 of 960 Error response H'90 ERROR Error response: H'90 (one byte): Error response to the device selection command ERROR: (one byte): Error code H'11: Sum check error H'21: Device code mismatch error (3) Clock Mode Inquiry The boot program will return the supported clock modes in response to the clock mode inquiry. Command H'21 Command: H'21 (one byte): Inquiry regarding clock mode Response H'31 Size Number of modes Mode SUM Response: H'31 (one byte): Response to the clock-mode inquiry Size (one byte): Amount of data that represents the number of modes and modes Number of modes (one byte): Number of supported clock modes H'00 indicates no clock mode or the device allows the clock mode to be read. Mode (one byte): Supported clock modes (i.e. H'01 means clock mode 1.) SUM (one byte): Checksum (4) Clock Mode Selection The boot program will set the specified clock mode. The program will return the selected clock-mode information after this setting has been made. The clock-mode selection command should be sent after the device selection command. Command H'11 Size Mode SUM Command: H'11 (one byte): Selection of clock mode Size (one byte): Number of characters that represents the mode (fixed at 1) Mode (one byte): Clock mode returned in reply to the supported clock mode inquiry. SUM (one byte): Checksum Response H'06 Response: H'06 (one byte): Response to the clock-mode selection command ACK will be returned when the clock mode matches. Error response H'91 ERROR Error response: H'91 (one byte): Error response to the clock-mode selection command ERROR (one byte): Error code H'11: Sum check error H'22: Clock mode mismatch error (5) Multiplication Ratio Inquiry The boot program will return the supported multiplication/division ratios. Rev.2.0, 07/03, page 812 of 960 Command H'22 Command: H'22 (one byte): Inquiry regarding multiplication ratio Response H'32 Number of multiplication ratios ... SUM Size Multiplication ratio Number of clock types ??? Response: H'32 (one byte): Response to the multiplication ratio inquiry Size (one byte): Amount of data that represents the number of clock types, the number of multiplication ratios, and the multiplication ratios Number of clock types (one byte): Number of supported multiplied clock types (e.g. when there are two multiplied clock types, which are the main operating frequency and the peripheral module operating frequency, the number of types will be H'02) Number of multiplication ratios (one byte): Number of multiplication ratios for each operating frequency (e.g. the number of multiplication ratios to which the main operating frequency can be set and the peripheral module operating frequency can be set) Multiplication ratio (one byte) Multiplication ratio : Value of the multiplication ratio (e.g. when the clock-frequency multiplier is four, the value of multiplication ratio will be H'04) Division ratio: Value of the division ratio, inverted to be a negative number (e.g. when the clock is divided by two, the value of division ratio will be H'FE. H'FE = -2) The number of multiplication ratios returned is the same as the number of multiplication ratios and as many groups of data are returned as there are types. SUM (one byte): Checksum (6) Operating Clock Frequency Inquiry The boot program will return the number of operating clock frequencies, and the maximum and minimum values. Command H'23 Command: H'23, (one byte): Inquiry regarding operating clock frequencies Response H'33 Size Number of operating clock frequencies Maximum value of operating clock frequency Minimum value of operating clock frequency ... SUM Response: H'33 (one byte): Response to operating clock frequency inquiry Rev.2.0, 07/03, page 813 of 960 Size (one byte): Number of bytes that represents the number of types, minimum values, and maximum values of operating clock frequencies. Number of types (one byte): Number of supported operating clock frequency types (e.g. when there are two operating clock frequency types, which are the main and peripheral clocks, the number of types will be H'02) Minimum value of operating clock frequency (two bytes): Minimum value for each multiplied or divided clock frequency. The minimum and maximum values represent the values in MHz, valid to the hundredths place of MHz, and multiplied by 100. (e.g. when the value is 20.00 MHz, it will be multiplied by 100 to be 2000 which is H'07D0) Maximum value of operating clock frequency (two bytes): Maximum value for each multiplied or divided clock frequency. There are as many pairs of minimum and maximum values as there are operating clock frequencies. SUM (one byte): Checksum (7) User Boot MAT Information Inquiry The boot program will return the number of user boot MATs and their addresses. Command H'24 Command: H'24 (one byte): Inquiry regarding user boot MAT information Response H'34 Size Number of areas Last address of area Start address of area ... SUM Response: H'34 (one byte): Response to user boot MAT information inquiry Size (one byte): Amount of data that represents the number of areas, the start address of each area, and the last address of each area Number of areas (one byte): Number of non-consecutive user boot MAT areas When user boot MAT areas are consecutive, the number of areas returned is H'01. Start address of area (four bytes): Start address of the area Last address of area (four bytes): Last address of the area There are as many groups of data representing the start and last addresses as there are areas. SUM (one byte): Checksum (8) User MAT Information Inquiry The boot program will return the number of user MATs and their addresses. Command H'25 Command: H'25 (one byte): Inquiry regarding user MAT information Rev.2.0, 07/03, page 814 of 960 Response H'35 Size Number of areas Last address of area Start address of area ... SUM Response: H'35 (one byte): Response to the user MAT information inquiry Size (one byte): Amount of data that represents the number of areas, the start address of each area, and the last address of each area Number of areas (one byte): Number of non-consecutive user MAT areas When user MAT areas are consecutive, the number of areas returned is H'01. Start address of area (four bytes): Start address of the area Last address of area (four bytes): Last address of the area There are as many groups of data representing the start and last addresses as there are areas. SUM (one byte): Checksum (9) Erased Block Information Inquiry The boot program will return the number of erased blocks and their addresses. Command H'26 Command: H'26 (one byte): Inquiry regarding erased block information Response H'36 Size Number of blocks Last address of block Start address of block ... SUM Response: H'36 (one byte): Response to the number of erased blocks and addresses Size (two bytes): Amount of data that represents the number of blocks, the start address of each block, and the last address of each block Number of blocks (one byte): Number of erased blocks in flash memory Start address of block (four bytes): Start address of the block Last address of block (four bytes): Last address of the block There are as many groups of data representing the start and last addresses as there are blocks. SUM (one byte): Checksum (10) Programming Unit Inquiry The boot program will return the programming unit used to program data. Command H'27 Command: H'27 (one byte): Inquiry regarding programming unit Rev.2.0, 07/03, page 815 of 960 Response H'37 Size Programming unit SUM Response: H'37 (one byte): Response to programming unit inquiry Size (one byte): Number of characters that indicate the programming unit (fixed at 2) Programming unit (two bytes): Unit for programming This is the unit for reception of program data. SUM (one byte): Checksum (11) Two-MAT Simultaneous Programming Information Inquiry The boot program will return an indication whether or not two-MAT simultaneous programming is allowed and the start address. Command H'28 Command: H'28 (one byte): Inquiry regarding two-MAT simultaneous programming information Response H'38 Size Programming method Start address of 2nd MAT Start address of 1st MAT SUM Response: H'38 (one byte): Response to 2-MAT simultaneous programming information inquiry Size (one byte): Amount of data that represents the programming method and start addresses, which is fixed at five bytes for one-MAT programming and at nine bytes for two-MAT simultaneous programming. Programming method (one byte): H'01 = one-MAT programming H'02 = two-MAT simultaneous programming Start address of 1st MAT (four bytes): Start address of the first MAT Start address of 2nd MAT (four bytes): Start address of the second MAT The start address of the second MAT is included only when the two-MAT simultaneous programming method is allowed. SUM (one byte): Checksum (12) New Bit Rate Selection The boot program will set a new bit rate and return the new bit rate. This selection should be sent after sending the clock-mode selection command. Command H'3F Number of multiplication ratios SUM Size Multiplication ratio 1 Bit rate Multiplication ratio 2 Input frequency Command: H'3F (one byte): Selection of new bit rate Size (one byte): Amount of data that represents the bit rate, input frequency, number of multiplication ratios, and multiplication ratios Rev.2.0, 07/03, page 816 of 960 Bit rate (two bytes): New bit rate One hundredth of the value (e.g. when the value is 19200 bps, the bit rate is 192, which is H'00C0) Input frequency (two bytes): Frequency of the clock input to the boot program This value is valid to the hundredths place and represents the value in MHz multiplied by 100. (e.g. when the value is 28.882 MHz, it will be multiplied by 100 to be 2888 which is H'0B48. Number of multiplication ratios (one byte): Number of multiplication ratios to which the device can be set. Multiplication ratio 1 (one byte): Value of the multiplication or division ratio for the main operating frequency Multiplication ratio: Value of the multiplication ratio (e.g. when the clock frequency is multiplied by four, the multiplication ratio will be H'04.) Division ratio: Value of the division ratio, inverted to be a negative number (e.g. when the clock is divided by two, the value of division ratio will be H'FE. H'FE = -2) Multiplication ratio 2 (one byte): Value of the multiplication or division ratio for the peripheral operating frequency Multiplication ratio: Value of the multiplication ratio (e.g. when the clock frequency is multiplied by four, the multiplication ratio will be H'04.) Division ratio: Value of the division ratio, inverted to be a negative number (e.g. when the clock is divided by two, the value of division ratio will be H'FE. H'FE = -2) SUM (one byte): Checksum Response H'06 Response: H'06 (one byte): Response to selection of a new bit rate When it is possible to set the bit rate, the response will be ACK. Error response H'BF ERROR Error response: H'BF (one byte): Error response to selection of new bit rate ERROR: (one byte): Error code H'11: Sum check error H'24: Bit-rate selection error This bit rate is not available. H'25: Input frequency error This input frequency is not within the range set by the minimum and maximum values. H'26: Multiplication ratio error This ratio does not match an available ratio. H'27: Operating frequency error This operating frequency is not within the range set by the minimum and maximum values. The methods for checking of received data are listed below. Rev.2.0, 07/03, page 817 of 960 * Input frequency The received value of the input frequency is checked to ensure that it is within the range of minimum to maximum frequencies which matches the clock modes of the specified device. When the value is out of this range, an input frequency error is generated. * Multiplication ratio The received value of the multiplication ratio or division ratio is checked to ensure that it matches the clock modes of the specified device. When the value is out of this range, a multiplication error is generated. * Operating frequency error The operating frequency is calculated from the received value of the input frequency and the multiplication or division ratio. The input frequency is input to the LSI and the LSI is actually operated at the operating frequency. The expression is given below. Operating frequency = Input frequency Multiplication ratio, or Operating frequency = Input frequency/Division ratio The calculated operating frequency should be checked to ensure that it is within the range of minimum to maximum frequencies which are available with the clock modes of the specified device. When it is out of this range, an operating frequency error is generated. * Bit rate From peripheral operating clock () and bit rate (B), the clock select (CKS) value (n) in the serial mode register (SMR) and the bit rate register (BRR) value (N) are obtained. The error between n and N that is calculated by the method below is checked to ensure that it is less than 4%. When it is 4% or more, a bit-rate selection error is generated. Error (%) = {[ x 106 (N + 1) x B x 64 x 2(2xn-1) ] - 1} x 100 When the new bit rate is selectable, the new bit rate will be set in the register after sending ACK in response. The host will send ACK with the new bit rate for confirmation and the boot program will response with that rate. Confirmation H'06 Confirmation: H'06 (one byte): Confirmation of a new bit rate Response H'06 Response: H'06 (one byte): Response to confirmation of a new bit rate The sequence of new bit-rate selection is shown in figure 22.29. Rev.2.0, 07/03, page 818 of 960 Host Setting a new bit rate Waiting for one-bit period at the specified bit rate Setting a new bit rate H'06 (ACK) with the new bit rate H'06 (ACK) with the new bit rate H'06 (ACK) Boot program Setting a new bit rate Figure 22.29 New Bit-Rate Selection Sequence (13) Transition to Programming/Erasing State To enter the programming/erasing state, the boot program will transfer the erasing program, and erase the user MATs and user boot MATs in that order. On completion of this erasure, ACK will be returned and a transition is made to the programming/erasing state. The host should select the device code, clock mode, and new bit rate with device selection, clock-mode selection, and new bit-rate selection commands, and then send the command for the transition to programming/erasing state. This procedure should be carried out before transferring the programming selection command or program data. Command H'40 Command: H'40 (one byte): Transition to programming/erasing state Response H'06 Response: H'06 (one byte): Response to transition to programming/erasing state The boot program will send ACK when the user MATs and user boot MATs have been erased by the transferred erasing program. Error response H'C0 H'51 Error response: H'C0 (one byte): Error response to transition to programming/erasing state Error code: H'51 (one byte): Erasing error An error occurred and erasure was not completed. Command Error: A command error will occur when a command is undefined, the order of commands is incorrect, or a command is unacceptable. Issuing a clock-mode selection command before a device selection or issuing an inquiry command after the command for transition to the programming/erasing state, are examples. Error response H'80 H'xx Error response: H'80 (one byte): Command error Command: H'xx (one byte): Received command Rev.2.0, 07/03, page 819 of 960 Command Order: The order for commands in the inquiry selection state is shown below. (1) A supported device inquiry (H'20) should be made to inquire about the supported devices. (2) The device should be selected from among those described by the returned information and set with a device selection (H'10) command. (3) A clock-mode inquiry (H'21) should be made to inquire about the supported clock modes. (4) The clock mode should be selected from among those described by the returned information and set with a clock-mode selection (H'11) command. (5) After selection of the device and clock mode, inquiries for other required information should be made, such as the multiplication ratio inquiry (H'22) or operating frequency inquiry (H'23). (6) A new bit rate should be selected with the new bit-rate selection (H'3F) command, according to the returned information on multiplication ratios and operating frequencies. (7) After selection of the device and clock mode, the information of the user boot MAT and user MAT should be made to inquire about the user boot MAT information inquiry (H'24), user MAT information inquiry (H'25), erased block information inquiry (H'26), programming unit inquiry (H'27), and two-MAT simultaneous programming information inquiry (H'28). (8) After making inquiries and selecting a new bit rate, issue the command for transition to the programming/erasing state (H'40). The boot program will then enter the programming/erasing state. Programming/Erasing State: In the programming/erasing state, a programming selection command makes the boot program select the programming method, a 128-byte programming command makes it program the memory with data, and an erasing selection command and block erasing command make it erase the block. Table 22.19 lists the programming/erasing commands. Rev.2.0, 07/03, page 820 of 960 Table 22.19 Programming/Erasing Commands Command H'42 H'43 H'44 H'50 H'48 H'58 H'52 H'4A H'4B H'4C H'4D H'4F Command Name User boot MAT programming selection User MAT programming selection Two-user-MAT simultaneous programming selection 128-byte programming Erasing selection Block erasing Memory read User boot MAT sum check User MAT sum check User boot MAT blank check User MAT blank check Boot program status inquiry Description Transfers the user boot MAT programming program Transfers the user MAT programming program Transfers the two-user-MAT simultaneous programming program Programs 128 bytes of data Transfers the erasing program Erases a block of data Reads the contents of memory Checks the checksum of the user boot MAT Checks the checksum of the user MAT Checks whether the contents of the user boot MAT are blank Checks whether the contents of the user MAT are blank Inquires into the boot program's state Programming: Programming is executed by a programming selection command and a 128-byte programming command. First, the host should send the programming selection command and select the programming method and programming MATs. There are three programming selection commands used according to the area and method for programming. (1) User boot MAT programming selection (2) User MAT programming selection (3) Two-user-MAT simultaneous programming selection After issuing the programming selection command, the host should send the 128-byte programming command. The 128-byte programming command that follows the selection command represents the data programmed according to the method specified by the selection command. When more than 128-byte data is programmed, 128-byte commands should repeatedly be executed. Sending a 128-byte programming command with H'FFFFFFFF as the address will stop the programming. On completion of programming, the boot program will wait for selection of programming or erasing. Rev.2.0, 07/03, page 821 of 960 To continue programming with another method or of another MAT, the procedure must be repeated from the programming selection command. The programming selection command and sequence for the 128-byte programming commands are shown in figure 22.30. Host Programming selection (H'42, H'43, H'44) Boot program Transfer of the programming program ACK 128-byte programming (address, data) Repeat ACK 128-byte programming (H'FFFFFFFF) ACK Programming Figure 22.30 Programming Sequence (1) User boot MAT programming selection The boot program will transfer a programming program. The data is programmed to the user boot MATs by the transferred programming program. Command H'42 Command: H'42 (one byte): User boot MAT programming selection Response H'06 Response: H'06 (one byte): Response to user boot MAT programming selection When the programming program has been transferred, the boot program will return ACK. Error response H'C2 ERROR Error response: H'C2 (one byte): Error response to user boot MAT programming selection ERROR: (one byte): Error code H'54: Selection processing error (transfer error occurs and processing is not completed) (2) User MAT programming selection The boot program will transfer a programming program. The data is programmed to the user MATs by the transferred programming program. Rev.2.0, 07/03, page 822 of 960 Command H'43 Command: H'43 (one byte): User MAT programming selection Response H'06 Response: H'06 (one byte): Response to user MAT programming selection When the programming program has been transferred, the boot program will return ACK. Error response H'C3 ERROR Error response: H'C3 (one byte): Error response to user MAT programming selection ERROR: (one byte): Error code H'54: Selection processing error (transfer error occurs and processing is not completed) (3) Two-user-MAT simultaneous programming selection The boot program will transfer the two-user-MAT simultaneous programming program. Data is simultaneously programmed to the two user MATs by the transferred two-user-MAT simultaneous programming program. The host must alternately send addresses and data that correspond to each MAT for simultaneous programming to two user MATs. The boot program will return one ACK for one 128-byte programming command, however, programming of the data will start when the boot program has received data for both MATs. Command H'44 Command: H'44 (one byte): Two-user-MAT simultaneous programming selection Response H'06 Response: H'06 (one byte): Response to two-user-MAT simultaneous programming selection After the two-user-MAT simultaneous programming program has been transferred, the boot program will return ACK. Error response H'C4 ERROR Error response: H'C4 (one byte): Error response to two-user-MAT simultaneous programming selection ERROR: (one byte): Error code H'54: Selection processing error (transfer error occurs and processing is not completed) (4) 128-byte programming The boot program will use the programming program transferred by the programming selection command for programming the user boot MATs or user MATs. When two-userMAT simultaneous programming command is selected, programming will start after the boot program has received data for both MATs. Command H'50 Data ... SUM Programming address ... Command: H'50 (one byte): 128-byte programming Rev.2.0, 07/03, page 823 of 960 Programming address (four bytes): Start address for programming Multiple of the size specified in response to the programming unit inquiry; a 128-byte boundary (e.g. H'00, H'01, H'00, H'00: H'01000000) Data (n bytes): Data to be programmed The size is specified in response to the programming unit inquiry. SUM (one byte): Checksum Response H'06 Response: H'06 (one byte): Response to 128-byte programming On completion of programming, the boot program will return ACK. In two-MAT programming, when all data for the first MAT has been received, the boot program will return ACK. Error response H'D0 ERROR Error response: H'D0 (one byte): Error response to 128-byte programming ERROR: (one byte): Error code H'11: Sum check error H'2A: Address error (address is not within the specified range) H'53: Programming error (a programming error has occurred and programming cannot be continued) The specified address should match the unit for programming of data. For example, when the programming is in 128-byte units, the lower byte of the address should be H'00 or H'80. When there are less than 128 bytes of data to be programmed, the host should fill the rest with H'FF. In two-user-MAT simultaneous programming, the host should alternately send the data for each MAT address. Sending the 128-byte programming command with the address of H'FFFFFFFF will stop the programming operation. The boot program will interpret this as the end of programming and wait for selection of programming or erasing. When the most recently received data has not been programmed in two-user-MAT simultaneous programming, the most recent data is programmed before programming is stopped. Command H'50 Programming address SUM Command: H'50 (one byte): 128-byte programming Programming address (four bytes): End code is H'FF, H'FF, H'FF, H'FF. SUM (one byte): Checksum Error response H'D0 ERROR Error response: H'D0 (one byte): Error response to 128-byte programming Rev.2.0, 07/03, page 824 of 960 ERROR: (one byte): Error code H'11: Sum check error H'53: Programming error An error has occurred in programming, and programming cannot be continued (in twouser-MAT simultaneous programming, when programming to the last MAT has not been completed.) Erasure: Erasure is performed with the erasing selection and block erasing command. First, erasure is selected by the erasing selection command and the boot program then erases the block specified by the block erasing command. The command should be repeatedly executed if two or more blocks are to be erased. Sending a block erasing command from the host with the block number H'FF will stop erasure. On completion of erasing, the boot program will wait for selection of programming or erasing. The erasing selection command and sequence for erasing data are shown in figure 22.31. Host Preparation for erasure (H'48) Transfer of erasure program ACK Erasure (Erased block number) ACK Erasure (H'FF) ACK Boot program Repeat Erasure Figure 22.31 Erasing Sequence (1) Erasing selection The boot program will transfer the erasing program. User MAT data is erased by the transferred erasing program. Command H'48 Command: H'48 (one byte): Erasing selection Rev.2.0, 07/03, page 825 of 960 Response H'06 Response: H'06 (one byte): Response to erasing selection After the erasing program has been transferred, the boot program will return ACK. Error response H'C8 ERROR Error response: H'C8 (one byte): Error response to erasing selection ERROR: (one byte): Error code H'54: Selection processing error (transfer error occurs and processing is not completed) (2) Block erasing The boot program will erase the contents of the specified block. Command H'58 Size Block number SUM Command: H'58 (one byte): Erasing Size (one byte): Number of characters that represents the erasure block number (fixed at 1) Block number (one byte): Number of the block whose data is to be erased SUM (one byte): Checksum Response H'06 Response: H'06 (one byte): Response to erasing After erasure has been completed, the boot program will return ACK. Error response H'D8 ERROR Error response: H'D8 (one byte): Error response to erasing H'11: Sum check error H'29: Block number error Block number is incorrect. H'51: Erasure error An error has occurred during erasure. On receiving block number H'FF, the boot program will stop erasure and wait for a selection command. Command H'58 Size Block number SUM Command: H'58 (one byte): Erasure Size (one byte): Number of characters that represents the block number (fixed at 1) Block number (one byte): H'FF (stop code for erasure) SUM (one byte): Checksum Response H'06 Response: H'06 (one byte): Response to end of erasure (ACK) When erasure is to be performed again after the block number H'FF has been sent, the procedure should be executed from the erasure selection command. (3) Memory read The boot program will return the data in the specified address. Rev.2.0, 07/03, page 826 of 960 Command H'52 Size Area Read address SUM Read size Command: H'52 (one byte): Memory read Size (one byte): Amount of data that represents the area, read address, and read size (fixed at 9) Area (one byte) H'00: User boot MAT H'01: User MAT An address error occurs when the area setting is incorrect. Read start address (four bytes): Start address to be read from Read size (four bytes): Size of data to be read SUM (one byte): Checksum Response H'52 Data SUM Read size ... Response: H'52 (one byte): Response to memory read Read size (four bytes): Size of data to be read Data (n bytes): Data for the read size from the read address SUM (one byte): Checksum Error response H'D2 ERROR Error response: H'D2 (one byte): Error response to memory read ERROR: (one byte): Error code H'11: Sum check error H'2A: Address error The start address for reading is not in the MAT. H'2B: Size error The read size exceeds the MAT, the last address for reading calculated from the start address for reading and the read size is not in the MAT, or read size is 0. (4) User boot MAT sum check The boot program will add the amount of data in user boot MATs and return the result. Command H'4A Command: H'4A (one byte): Sum check of user boot MATs Response H'5A Size MAT checksum SUM Response: H'5A (one byte): Response to sum check of user boot MATs Size (one byte): Number of characters in checksum data (fixed at 4) MAT checksum (four bytes): Checksum of user boot MATs The total amount of data is obtained in byte units. SUM (one byte): Checksum (for transmit data) Rev.2.0, 07/03, page 827 of 960 (5) User MAT sum check The boot program will add the amount of data in user MATs and return the result. Command H'4B Command: H'4B (one byte): Sum check of user MATs Response H'5B Size MAT checksum SUM Response: H'5B (one byte): Response to sum check of user MATs Size (one byte): Number of characters in checksum data (fixed at 4) MAT checksum (four bytes): Checksum of user MATs The total amount of data is obtained in byte units. SUM (one byte): Checksum (for transmit data) (6) User boot MAT blank check The boot program will check whether or not all user boot MATs are blank and return the result. Command H'4C Command: H'4C (one byte): Blank check of user boot MATs Response H'06 Response: H'06 (one byte): Response to blank check of user boot MATs If all user boot MATs are blank (H'FF), the boot program will return ACK. Error response H'CC H'52 Error response: H'CC (one byte): Error response to blank check of user boot MATs Error code: H'52 (one byte): Erasure has not been completed (7) User MAT blank check The boot program will check whether or not all user MATs are blank and return the result. Command H'4D Command: H'4D (one byte): Blank check of user MATs Response H'06 Response: H'06 (one byte): Response to blank check of user MATs If all user MATs are blank (H'FF), the boot program will return ACK. Error response H'CD H'52 Error response: H'CD (one byte): Error response to blank check of user MATs Error code: H'52 (one byte): Erasure has not been completed. (8) Boot program status inquiry The boot program will return indications of its present state and error condition. This inquiry can be made in the inquiry/selection state or the programming/erasing state. Command H'4F Command: H'4F (one byte): Inquiry regarding boot program status Rev.2.0, 07/03, page 828 of 960 Response H'5F Size STATUS ERROR SUM Response: H'5F (one byte): Response to inquiry regarding boot program status Size (one byte): Number of characters in data (fixed at 2) STATUS (one byte): Standard boot program status For details, see table 22.20, Status Code. ERROR (one byte): Error state ERROR = 0 indicates normal operation. ERROR = 1 indicates error has occurred. For details, see table 22.21, Error Code. SUM (one byte): Checksum Table 22.20 Status Code Code H'11 H'12 H'13 H'1F H'31 H'3F H'4F H'5F Description Device Selection Wait Clock Mode Selection Wait Bit Rate Selection Wait Programming/Erasing State Transition Wait (bit rate selection is completed) Programming State for Erasing User MAT and User Boot MAT Programming/Erasing Selection Wait (Erasure is completed) Programming Data Receive Wait Erasure Block Specification Wait (erasure is completed) Rev.2.0, 07/03, page 829 of 960 Table 22.21 Error Code Code H'00 H'11 H'21 H'22 H'24 H'25 H'26 H'27 H'29 H'2A H'2B H'51 H'52 H'53 H'54 H'80 H'FF Description No Error Sum Check Error Device Code Mismatch Error Clock Mode Mismatch Error Bit Rate Selection Error Input Frequency Error Multiplication Ratio Error Operating Frequency Error Block Number Error Address Error Data Length Error Erasure Error Erasure Incompletion Error Programming Error Selection Error Command Error Bit-Rate-Adjustment Confirmation Error 22.10.2 AC Characteristics and Timing in Programmer Mode Table 22.22 AC Characteristics in Memory Read Mode Condition: VCC = 3.3 V 0.3 V, VSS = 0 V, Ta = 25C 5C Code Command write cycle CE hold time CE setup time Data hold time Data setup time Programming pulse width WE rise time WE fall time Symbol tnxtc tceh tces tdh tds twep tr tf Min 20 0 0 50 50 70 30 30 Max Unit s ns ns ns ns ns ns ns Note Rev.2.0, 07/03, page 830 of 960 Command write A19-A0 tces tceh tnxtc Memory read mode Address stable twep tf tr tds I/O7-I/O0 tdh Note : Data is latched at the rising edge of . Figure 22.32 Memory Read Timing after Command Write Table 22.23 AC Characteristics in Transition from Memory Read Mode to Others Condition: VCC = 3.3 V 0.3 V, VSS = 0 V, Ta = 25C 5C Code Command write cycle CE hold time CE setup time Data hold time Data setup time Programming pulse width WE rise time WE fall time Symbol tnxtc tceh tces tdh tds twep tr tf Min 20 0 0 50 50 70 30 30 Max Unit s ns ns ns ns ns ns ns Note Rev.2.0, 07/03, page 831 of 960 Memory read mode A19-A0 Command write in another mode Address stable tnxtc tces tceh tf twep tr tds I/O7-I/O0 tdh Note : and should not be enabled simultaneously. Figure 22.33 Timing at Transition from Memory Read Mode to Other Modes Table 22.24 AC Characteristics in Memory Read Mode Condition: VCC = 3.3 V 0.3 V, VSS = 0 V, Ta = 25C 5C Code Access time CE output delay time OE output delay time Output disable delay time Data output hold time Symbol tacc tce toe tdf toh 5 Min Max 20 150 150 100 Unit s ns ns ns ns Note A19-A0 Address stable Address stable VIL VIL VIH I/O7-I/O0 tacc toh tacc toh Figure 22.34 CE OE Enable State Read CE/OE Rev.2.0, 07/03, page 832 of 960 A19-A0 Address stable tce Address stable tce toe toe VIH I/O7-I/O0 tacc tacc toh tdf toh tdf Figure 22.35 CE OE Clock Read CE/OE Table 22.25 AC Characteristics in Auto-Program Mode Condition: VCC = 3.3 V 0.3 V, VSS = 0 V, Ta = 25C 5C Code Command write cycle CE hold time CE setup time Data hold time Data setup time Programming pulse width Status polling start time Status polling access time Address setup time Address hold time Memory programming time Programming setup time Programming end setup time WE rise time WE fall time Symbol tnxtc tceh tces tdh tds twep twsts tspa tas tah twrite tpns tpnh tr tf 0 60 1 100 100 30 30 3000 Min 20 0 0 50 50 70 1 150 Max Unit s ns ns ns ns ns ms ns ns ns ms ns ns ns ns Note Rev.2.0, 07/03, page 833 of 960 FWE A19-A0 tpnh Address stable tpns tces tceh tnxtc tnxtc tf twep tr tas tah Data transfer 1 byte to 128 bytes twsts tspa tds I/O7 tdh twrite Programming end identification signal I/O6 Programming normal end confirmation signal I/O5-I/O0 H'40 or H'45 H'00 1st-byte Din 128th-byte Din Figure 22.36 Timing in Auto-Program Mode Table 22.26 AC Characteristics in Auto-Erase Mode Condition: VCC = 3.3 V 0.3 V, VSS = 0 V, Ta = 25C 5C Code Command write cycle CE hold time CE setup time Data hold time Data setup time Programming pulse width Status polling start time Status polling access time Memory erase time Erase setup time Erase end setup time WE rise time WE fall time Symbol tnxtc tceh tces tdh tds twep tests tspa terase tens tenh tr tf 100 100 100 30 30 Min 20 0 0 50 50 70 1 150 40000 Max Unit s ns ns ns ns ns ms ns ms ns ns ns ns Note Rev.2.0, 07/03, page 834 of 960 FWE A19-A0 tenh tens tces tceh tnxtc tnxtc tf twep tr tests tspa tds I/O7 tdh terase Erase end identification signal Erase normal end confirmation signal I/O6 I/O5-I/O0 H'20 or H'25 H'20 or H'25 H'00 Figure 22.37 Timing in Auto-Erase Mode Table 22.27 AC Characteristics Status Read Mode Condition: VCC = 3.3 V 0.3 V, VSS = 0 V, Ta = 25C 5C Code Command write cycle CE hold time CE setup time Data hold time Data setup time Programming pulse width OE output delay time Disable delay time CE output delay time WE rise time WE fall time Symbol tnxtc tceh tces tdh tds twep toe tdf tce tr tf Min 20 0 0 50 50 70 150 100 150 30 30 Max Unit s ns ns ns ns ns ns ns ns ns ns Note Rev.2.0, 07/03, page 835 of 960 A19-A0 tces tceh tnxtc tces tceh tnxtc tnxtc tce tf twep tr tf twep tr toe tdf tds I/O7-I/O0 H'71 tdh tds H'71 tdh Note: I/O3 and I/O2 are undefined. Figure 22.38 Timing in Status Read Mode Table 22.28 Stipulated Transition Times to Command Wait State Condition: VCC = 3.3 V 0.3 V, VSS = 0 V, Ta = 25C 5C Code Standby release (oscillation stabilization time) Programmer mode setup time VCC hold time Symbol tosc1 Min 30 Max Unit ms Note tbmv tdwn 10 0 ms ms tosc1 VCC tbmv Memory read mode Command wait state Auto-program mode Auto-erase mode Command wait state Normal/abnormal end identification tdwn FWE Note: Set the FWE input pin to low level, except in the auto-program and auto-erase modes. Figure 22.39 Oscillation Stabilization Time, Programmer Mode Setup Time, and PowerDown Sequence Rev.2.0, 07/03, page 836 of 960 22.10.3 Storable Area for Procedure Program and Programming Data In the descriptions in the previous section, storable areas for the programming/erasing procedure programs and program data are assumed to be in on-chip RAM. However, the procedure programs and data can be stored in and executed from other areas (e.g. external address space) as long as the following conditions are satisfied. (1) The on-chip programming/erasing program is downloaded from the address set by FTDAR in on-chip RAM, therefore, this area is not available for use. (2) The on-chip programming/erasing program will use 128 bytes or more as a stack. Make sure this area is reserved. (3) Since download by setting the SCO bit to 1 will cause the MATs to be switched, it should be executed in on-chip RAM. (4) The flash memory is accessible until the start of programming or erasing, that is, until the result of downloading has been judged. When in a mode in which the external address space is not accessible, such as single-chip mode, the required procedure programs, interrupt vector table, interrupt processing routine, and user branch program should be transferred to on-chip RAM before programming/erasing of the flash memory starts. (5) The flash memory is not accessible during programming/erasing operations. Therefore, the programming/erasing program must be downloaded to on-chip RAM in advance. Areas for executing each procedure program for initiating programming/erasing, the user program at the user branch destination for programming/erasing, the interrupt vector table, and the interrupt processing routine must be located in on-chip memory other than flash memory or the external address space. (6) After programming/erasing, access to flash memory is inhibited until FKEY is cleared. A reset state (RES = 0) for more than at least 100 s must be taken when the LSI mode is changed to reset on completion of a programming/erasing operation. Transitions to the reset state or hardware standby mode during programming/erasing are inhibited. When the reset signal is accidentally input to the LSI, a longer period in the reset state than usual (100 s) is needed before the reset signal is released. (7) Switching of the MATs by FMATS is needed for programming/erasing of the user MAT in user boot mode. The program which switches the MATs should be executed from the on-chip RAM. For details, see section 22.8.1, Switching between User MAT and User Boot MAT. Please make sure you know which MAT is selected when switching the MATs. (8) When the program data storage area indicated by the FMPDR parameter in the programming processing is within the flash memory area, an error will occur. Therefore, temporarily transfer the program data to on-chip RAM to change the address set in FMPDR to an address other than flash memory. Based on these conditions, tables 22.29 and 22.30 show the areas in which the program data can be stored and executed according to the operation type and mode. Rev.2.0, 07/03, page 837 of 960 Table 22.29 Executable MAT Initiated Mode Operation Programming Erasing User Program Mode Table 22.30 (1) Table 22.30 (2) User Boot Mode* Table 22.30 (3) Table 22.30 (4) Note: * Programming/Erasing is possible to user MATs. Rev.2.0, 07/03, page 838 of 960 Table 22.30 (1) Usable Area for Programming in User Program Mode Storable /Executable Area External Space (Expanded Mode with MD0 = 0) O O Selected MAT Embedded Program Storage MAT -- Item Program data storage area Selecting on-chip program to be downloaded Writing H'A5 to key register Writing 1 to SCO in FCCS (download) Key register clearing Judging download result Programming procedure Download error processing Setting initialization parameters Initialization Judging initialization result Initialization error processing Interrupt processing routine Writing H'5A to key register Setting programming parameters Programming Judging programming result Programming error processing Key register clearing On-Chip RAM O O User MAT X* O User MAT -- O O O O O O O O O O O O O O O O O O X O O O O X O O X O X X X X X O X O O O O X O O O O O X O O O O O O O O O O O O O O O O O O O Note: * If the data has been transferred to on-chip RAM in advance, this area can be used. Rev.2.0, 07/03, page 839 of 960 Table 22.30 (2) Usable Area for Erasure in User Program Mode Storable /Executable Area External Space (Expanded Mode with MD0 = 0) O Selected MAT Embedded Program Storage MAT Item Selecting on-chip program to be downloaded Writing H'A5 to key register Writing 1 to SCO in FCCS (download) Key register clearing Judging download result Download error processing Erasing procedure Setting initialization parameters Initialization Judging initialization result Initialization error processing Interrupt processing routine Writing H'5A to key register Setting erasure parameters Erasure Judging erasure result Erasing error processing Key register clearing On-Chip RAM O User MAT O User MAT O O O O O O O O O O O O O O O O O O X O O O O X O O X O X X X X X O X O O O O X O O O O O X O O O O O O O O O O O O O O O O O O O Rev.2.0, 07/03, page 840 of 960 Table 22.30 (3) Usable Area for Programming in User Boot Mode Storable/Executable Area External Space (Expanded Mode with MD0 = 0) O O Selected MAT Embedded Program Storage Area -- Item Program data storage area Selecting on-chip program to be downloaded Writing H'A5 to key register Writing 1 to SCO in FCCS (download) Key register clearing Judging download result Programming procedure Download error processing Setting initialization parameters Initialization Judging initialization result Initialization error processing Interrupt processing routine Switching MATs by FMATS Writing H'5A to Key Register OnChip RAM O O User MAT X* O 1 User MAT -- User Boot Mat -- O O O O O O O O O O O O O O X O O O O X O O X X X O X O O O O X O O O X O O O O O O O O O O O O O Rev.2.0, 07/03, page 841 of 960 Storable/Executable Area External Space (Expanded Mode with MD0 = 0) O X O 2 Selected MAT Embedded Program Storage Area Item Setting programming parameters Programming Programming procedure Judging programming result Programming error processing Key register clearing Switching MATs by FMATS OnChip RAM O O O O O O User MAT X X X X* X X User MAT O O O O O User Boot Mat O O X O Notes *1 If the data has been transferred to on-chip RAM in advance, this area can be used. *2 If the MATs have been switched by FMATS in on-chip RAM, this MAT can be used. Rev.2.0, 07/03, page 842 of 960 Table 22.30 (4) Usable Area for Erasure in User Boot Mode Storable/Executable Area External Space (Expanded Mode with MD0 = 0) O Selected MAT Embedded Program Storage Area Item Selecting on-chip program to be downloaded Writing H'A5 to key register Writing 1 to SCO in FCCS (download) Key register clearing Judging download result Download error processing Erasing procedure Setting initialization parameters Initialization Judging initialization result Initialization error processing Interrupt processing routine Switching MATs by FMATS Writing H'5A to key register Setting erasure parameters OnChip RAM O User MAT O User MAT User Boot Mat O O O O O O O O O O O O O O O X O O O O X O O X X X X O X O O O O X O O O X O O O O O O O O O O O O O O O Rev.2.0, 07/03, page 843 of 960 Storable/Executable Area External Space (Expanded Mode with MD0 = 0) X O O O X Selected MAT Embedded Program Storage Area Item Erasure Judging erasure result Erasing error processing Key register clearing Switching MATs by FMATS OnChip RAM O O O O O User MAT X X X* X X User MAT O O O O User Boot Mat Erasing procedure O Note: * If the MATs have been switched by FMATS in on-chip RAM, this MAT can be used. Rev.2.0, 07/03, page 844 of 960 Section 23 RAM 23.1 Overview The SH7055SF has 32 kbytes of on-chip RAM. The on-chip RAM is linked to the CPU, direct memory access controller (DMAC), and advanced user debugger (AUD) with a 32-bit data bus (figure 23.1). The CPU, DMAC, and AUD can access data in the on-chip RAM in 8, 16, or 32 bit widths. Onchip RAM data can always be accessed in one state, making the RAM ideal for use as a program area, stack area, or data area, which require high-speed access. The contents of the on-chip RAM are held in both the sleep and software standby modes. When the RAME bit (see below) is cleared to 0, the on-chip RAM contents are also held in hardware standby mode. The on-chip RAM is allocated to addresses H'FFFF6000 to H'FFFFDFFF. SH7055SF Internal data bus (32 bits) 8 bits 8 bits 8 bits 8 bits H'FFFF6000 H'FFFF6004 H'FFFF6001 H'FFFF6005 H'FFFF6002 H'FFFF6006 H'FFFF6003 H'FFFF6007 On-chip RAM H'FFFFDFFC H'FFFFDFFD H'FFFFDFFE H'FFFFDFFF Figure 23.1 Block Diagram of RAM Rev.2.0, 07/03, page 845 of 960 23.2 Operation The on-chip RAM is controlled by means of the system control register (SYSCR). When the RAME bit in SYSCR is set to 1, the on-chip RAM is enabled. Accesses to addresses H'FFFF6000-H'FFFFDFFF are then directed to the on-chip RAM. When the RAME bit in SYSCR is cleared to 0, the on-chip RAM is not accessed. A read will return an undefined value, and a write is invalid. If a transition is made to hardware standby mode after the RAME bit in SYSCR is cleared to 0, the contents of the on-chip RAM are held. For details of SYSCR, see 24.2.2, System Control Register (SYSCR), in section 24, Power-Down State. Rev.2.0, 07/03, page 846 of 960 Section 24 Power-Down State 24.1 Overview Three modes are provided as power-save modes, namely, the hardware standby, software standby and sleep modes. Also, a module stop function is available to stop some modules. These standby modes can be selected depending on applications to reduce the power consumption of the SH7055SF. 24.1.1 Power-Down States The power-down state is effected by the following modes: 1. Hardware standby mode A transition to hardware standby mode is made according to the input level of the RES and HSTBY pins. In hardware standby mode, all SH7055SF functions are halted. This state is exited by means of a power-on reset. 2. Software standby mode A transition to software standby mode is made by means of software (a CPU instruction). In software standby mode, all SH7055SF functions are halted. This state is exited by means of a power-on reset or an NMI interrupt. 3. Sleep mode A transition to sleep mode is made by means of a CPU instruction. In software standby mode, basically only the CPU is halted, and all on-chip peripheral modules operate. This state is exited by means of a power-on reset, a manual reset, interrupt, or DMA address error. 4. Module standby mode Operation of the on-chip peripheral modules* which can be placed in a standby mode can be stopped by stopping the clock supply. Clock supply to the individual modules can be controlled by setting bits in the module standby control register (MSTCR). Note: * AUD, H-UDI, FPU, and UBC Rev.2.0, 07/03, page 847 of 960 Table 24.1 shows the transition conditions for entering the modes from the program execution state, as well as the CPU and peripheral function status in each mode and the procedures for canceling each mode. Table 24.1 Power-Down State Conditions State Entering Procedure On-Chip CPU Peripheral Registers Modules RAM 2 Mode Clock CPU Pins Canceling Procedure Hardware Low-level standby input at HSTBY pin Software standby Halted Halted Halted Undefined Held* Initialized High-level input at HSTBY pin, executing power-on reset 1 Halted* Execute Halted Halted Held SLEEP instruction with SSBY bit set to 1 in SBYCR Execute Runs SLEEP instruction with SSBY bit cleared to 0 in SBYCR Halted Held Held Held or high imped3 ance* * * NMI interrupt Power-on reset Interrupt DMA address error Power-on reset Manual reset Sleep Run Held Held * * * * Notes: SBYCR: Standby control register SSBY: Software standby bit *1 Some bits within on-chip peripheral module registers are initialized in software standby mode, and some are not. See table A.2, Register States in Reset and Power-Down States. Also refer to the register descriptions for each peripheral module. *2 Clear the RAME bit of the SYSCR to 0 in advance when changing the state from the program execution state to the hardware standby state. *3 The state of the I/O ports in standby mode is set by the port high impedance bit (HIZ) in SBYCR. See section 24.2.1, Standby Control Register (SBYCR). For details of other pin states, refer to appendix B, Pin States. Rev.2.0, 07/03, page 848 of 960 24.1.2 Pin Configuration Pins related to power-down modes are shown in table 24.2. Table 24.2 Pin Configuration Pin Name Hardware standby input pin Power-on reset input pin Abbreviation HSTBY RES I/O Input Input Function Input level determines transition to hardware standby mode Power-on reset signal input pin 24.1.3 Related Registers Table 24.3 shows the registers used for power-down state control. Table 24.3 Related Registers Initial Value Write H'1F H'01* H'01 4 Address Read H'FFFFEC14 H'FFFFF708 2 3 Name Standby control register System control register Module standby control register Abbreviation 1 SBYCR* R/W R/W R/W R/W Access Size 8 8 SYSCR* 1 1 MSTCR* H'FFFFF70A* H'FFFFF70B* 8, 16 Notes: *1 SBYCR is accessed in three cycles, SYSCR and MSTCR in four or five cycles. *2 Write data in word units. Data cannot be written in byte or longword units. *3 Read data in byte units. Values cannot be read correctly if data is read in word or longword units. *4 The initial value of bit 7 in SYSCR is not defined. Rev.2.0, 07/03, page 849 of 960 24.2 24.2.1 Register Descriptions Standby Control Register (SBYCR) The standby control register (SBYCR) is an 8-bit readable/writable register that sets the transition to standby mode, and the port state in standby mode. SBYCR is initialized to H'1F by a power-on reset. Bit: 7 SSBY Initial value: R/W: 0 R/W 6 HIZ 0 R/W 5 -- 0 R 4 -- 1 R 3 -- 1 R 2 -- 1 R 1 -- 1 R 0 -- 1 R * Bit 7--Software Standby (SSBY): Specifies transition to software standby mode. The SSBY bit cannot be set to 1 while the watchdog timer is running (when the timer enable bit (TME) in the WDT timer control/status register (TCSR) is set to 1). To enter software standby mode, always halt the WDT by clearing the TME bit to 0, then set the SSBY bit. Bit 7: SSBY 0 1 Description Executing SLEEP instruction puts the SH7055SF into sleep mode (Initial value) Executing SLEEP instruction puts the SH7055SF into standby mode * Bit 6--Port High Impedance (HIZ): In software standby mode, this bit selects whether to set I/O port pins to high impedance or hold the pin state. The HIZ bit cannot be set to 1 when the TME bit of the WDT timer control/status register (TCSR) is set to 1. When making the I/O port pin state high impedance, always clear the TME bit to 0 before setting the HIZ bit. Bit 6: HIZ 0 1 Description Pin states held in software standby mode Pins go to high impedance in software standby mode (Initial value) * Bit 5--Reserved: This bit always reads 0. The write value should always be 0. * Bits 4 to 0--Reserved: These bits always read 1. The write value should always be 1. Rev.2.0, 07/03, page 850 of 960 24.2.2 System Control Register (SYSCR) Bit: 7 -- 6 -- 0 R 5 -- 0 R 4 -- 0 R 3 -- 0 R 2 -- 0 R 1 AUDSRST 0 R/W 0 RAME 1 R/W Initial value: R/W: 0 R The system control register (SYSCR) is an 8-bit readable/writable register that performs AUD software reset control and enables or disables access to the on-chip RAM. SYSCR is initialized to H'01 by a power-on reset. * Bit 7--Reserved: The read value is not defined. The write value should always be 0. * Bits 6 to 2--Reserved: These bits always read 0. The write value should always be 0. * Bit1-- AUD Software Reset (AUDSRST): This bit controls AUD reset using software. Setting AUDSRST bit to 1 places, the AUD module in the power-on reset state. Bit 1: AUDSRST Description 0 1 AUD reset state cleared AUD reset state entered (Initial value) * Bit 0--RAME Enable (RAME): Selects enabling or disabling of the on-chip RAM. When RAME is set to 1, on-chip RAM is enabled. When RAME is cleared to 0, on-chip RAM cannot be accessed. In this case, a read or instruction fetch from on-chip RAM will return an undefined value, and a write to on-chip RAM will be ignored. The initial value of RAME is 1. When on-chip RAM is disabled by clearing RAME to 0, do not place an instruction that attempts to access on-chip RAM immediately after the SYSCR write instruction, as normal access cannot be guaranteed in this case. When on-chip RAM is enabled by setting RAME to 1, place an SYSCR read instruction immediately after the SYSCR write instruction. Normal access cannot be guaranteed if an onchip RAM access instruction is placed immediately after the SYSCR write instruction. Bit 0: RAME 0 1 Description On-chip RAM disabled On-chip RAM enabled (Initial value) Rev.2.0, 07/03, page 851 of 960 24.2.3 Module Standby Control Register (MSTCR) Bit: 7 -- 6 -- 0 R 5 -- 0 R 4 -- 0 R 3 2 1 0 MSTOP3 MSTOP2 MSTOP1 MSTOP0 0 R/W 0 R/W 0 R/W 1 R/W Initial value: R/W: 0 R The module standby control register (MSTCR) is an 8-bit readable/writable register that controls the standby state of the AUD, H-UDI, FPU, and UBC on-chip modules. MSTCR is initialized to H'01 by a power-on reset. Note: The method of writing to MSTCR is different from that of ordinary registers to prevent inadvertent rewriting. See section 24.2.4, Notes on Register Access, for more information. * Bits 7 to 4--Reserved: These bits always read 0. The write value should always be 0. * Bit 3--Module Stop 3 (MSTOP3): Specifies halting of the clock supply to the AUD on-chip peripheral module. Setting the MSTOP3 bit to 1 stops the clock supply to the AUD. To cancel halting of the clock supply to the AUD, first set the AUD software reset bit (AUDSRST) in the system control register (SYSCR) to the AUD reset state value. Use of the AUD will then be enabled by clearing the AUD reset. Bit 3: MSTOP3 0 1 Description AUD operates Clock supply to AUD stopped (Initial value) * Bit 2--Module Stop 2 (MSTOP2): Specifies halting of the clock supply to the H-UDI on-chip peripheral module. Setting the MSTOP2 bit to 1 stops the clock supply to the H-UDI. Bit 2: MSTOP2 0 1 Description H-UDI operates Clock supply to H-UDI stopped (Initial value) Rev.2.0, 07/03, page 852 of 960 * Bit 1--Module Stop 1 (MSTOP1): Specifies halting of the clock supply to the FPU on-chip peripheral module. Setting the MSTOP1 bit to 1 stops the clock supply to the FPU. The MSTOP1 bit cannot be cleared by writing 0 after it has been set to 1. In other words, once the MSTOP1 bit has been set to 1 and the clock supply to the FPU has been stopped, the clock supply to the FPU cannot be resumed by clearing the MSTOP1 bit to 0. An SH7055SF power-on reset is necessary to restart the FPU clock supply after it has been stopped. Bit 1: MSTOP1 0 1 Description FPU operates Clock supply to FPU stopped (Initial value) * Bit 0--Module Stop 0 (MSTOP0): Specifies halting of the clock supply stop to the UBC onchip peripheral module. Clearing the MSTOP0 bit to 0 starts the clock supply to the UBC. Stopping clock supply to the UBC will reset the internal state of the UBC including its registers. Bit 0: MSTOP0 0 1 Description UBC operates Clock supply to UBC stopped (Initial value) 24.2.4 Notes on Register Access The method of writing to the module standby control register (MSTCR) is different from that of ordinary registers to prevent inadvertent rewriting. Be certain to use a word transfer instruction when writing data to MSTCR. Data cannot be written by a byte transfer instruction. As shown in figure 24.1, set the upper byte to H'3C and transfer data using the lower byte as write data. Data can be read by the same method as for ordinary registers. MSTCR is allocated to address H'FFFFF70A. Always use a byte transfer instruction to read data. When writing to MSTCR 15 Address: H'FFFFF70A H'3C 8 7 Write data 0 Figure 24.1 Writing to MSTCR Rev.2.0, 07/03, page 853 of 960 24.3 24.3.1 Hardware Standby Mode Transition to Hardware Standby Mode The chip enters hardware standby mode when the HSTBY and RES pins go low. Set the pins following to mode setup pin shown in section 4, Operating modes. Operation with other pin set up are not guaranteed. Hardware standby mode reduces power consumption drastically by halting all SH7055SF functions. As the transition to hardware standby mode is made by means of external pin input, the transition is made asynchronously, regardless of the current state of the SH7055SF, and therefore the chip state prior to the transition is not preserved. However, on-chip RAM data is retained as long as the specified voltage is supplied. To retain on-chip RAM data, clear the RAM enable bit (RAME) to 0 in the system control register (SYSCR) before driving the HSTBY pin low. See appendix B, Pin States, for the pin states in hardware standby mode. 24.3.2 Canceling Hardware Standby Mode Hardware standby mode is canceled by means of the HSTBY pin and RES pin. When HSTBY is driven high while RES is low, the clock oscillator starts running. The RES pin should be held low long enough for clock oscillation to stabilize. When RES is driven high, power-on reset exception processing is started and a transition is made to the program execution state. 24.3.3 Hardware Standby Mode Timing Figure 24.2 shows sample pin timings for hardware standby mode. A transition to hardware standby mode is made by driving the HSTBY pin low after driving the RES pin low. Hardware standby mode is canceled by driving HSTBY high, waiting for clock oscillation to stabilize, then switching RES from low to high. Rev.2.0, 07/03, page 854 of 960 Oscillator pulse width tRESW Oscillation settling time + pulse width Reset exception processing Figure 24.2 Hardware Standby Mode Timing Rev.2.0, 07/03, page 855 of 960 24.4 24.4.1 Software Standby Mode Transition to Software Standby Mode To enter software standby mode, set the software standby bit (SSBY) to 1 in SBYCR, then execute the SLEEP instruction. The SH7055SF switches from the program execution state to software standby mode. In software standby mode, power consumption is greatly reduced by halting not only the CPU, but the clock and on-chip peripheral modules as well. CPU register contents and on-chip RAM data are held as long as the prescribed voltages are applied (when the RAME bit in SYSCR is 0). The register contents of some on-chip peripheral modules are initialized, but some are not. For details on the register states, refer to appendix A.2, Register States in Reset and Power-Down States. The I/O port state can be selected as held or high impedance by the port high impedance bit (HIZ) in SBYCR. For other pin states, refer to appendix B, Pin States. 24.4.2 Canceling Software Standby Mode Software standby mode is canceled by an NMI interrupt or a power-on reset. Cancellation by NMI: Clock oscillation starts when a rising edge or falling edge (selected by the NMI edge select bit (NMIE) in the interrupt control register (ICR) of the INTC) is detected in the NMI signal. This clock is supplied only to the oscillation settling counter which counts the oscillation stablizing time. The oscillation settling counter overflows when it counts 2 =65536 with the input clock frequency. Since the frequency of this counting clock is unstable until the PLL multiply curcuit is locked in the absolute time is not fixed, and the CK pin signal output is in the high level for the meantime. Counting the oscillation settling time by the oscillation settling counter is used to indicate that the clock has stabilized, so the clock is supplied to the entire chip, software standby mode is canceled, and NMI exception processing begins. When canceling standby mode with an NMI pin set for falling edge, be sure that the NMI pin level upon entering software standby (when the clock is halted) is high, and that the NMI pin level upon returning from software standby (when the clock starts after oscillation stabilization) is low. When canceling software standby mode with an NMI pin set for rising edge, be sure that the NMI pin level upon entering software standby (when the clock is halted) is low, and that the NMI pin level upon returning from software standby (when the clock starts after oscillation stabilization) is high. Cancellation by Power-On Reset: A power-on reset of the SH7055SF caused by driving the RES pin low cancels software standby mode. Rev.2.0, 07/03, page 856 of 960 16 24.4.3 Software Standby Mode Application Example This example describes a transition to software standby mode on the falling edge of the NMI signal, and cancellation on the rising edge of the NMI signal. The timing is shown in figure 24.3. When the NMI pin is changed from high to low level while the NMI edge select bit (NMIE) in ICR is set to 0 (falling edge detection), the NMI interrupt is accepted. When the NMIE bit is set to 1 (rising edge detection) by the NMI exception service routine, the software standby bit (SSBY) in SBYCR is set to 1, and a SLEEP instruction is executed, software standby mode is entered. Thereafter, software standby mode is canceled when the NMI pin is changed from low to high level. Oscillator CK NMI pin NMIE bit SSBY bit SH7055 state Program execution NMI exception processing Exception service routine Software standby mode Oscillation settling time NMI exception processing Figure 24.3 Software Standby Mode NMI Timing (Application Example) Rev.2.0, 07/03, page 857 of 960 24.5 24.5.1 Sleep Mode Transition to Sleep Mode Executing the SLEEP instruction after the software standby bit (SSBY) in SBYCR has been cleared to 0 causes a transition from the program execution state to sleep mode. Although the CPU halts immediately after executing the SLEEP instruction, the contents of its internal registers remain unchanged. The on-chip peripheral modules continue to run during sleep mode. 24.5.2 Canceling Sleep Mode Cancellation by Interrupt: When an interrupt occurs, sleep mode is canceled and interrupt exception processing is executed. The sleep mode is not canceled if the interrupt cannot be accepted because its priority level is equal to or less than the mask level set in the CPU's status register (SR) or if an interrupt by an on-chip peripheral module is disabled at the peripheral module. Cancellation by DMA Address Error: If a DMA address error occurs, sleep mode is canceled and DMA address error exception processing is executed. Cancellation by Manual Reset: When an internal manual reset is triggered by the WDT and the CPU acquires the bus during the internal manual reset period, the state of the SH7055SF changes to the manual reset state and sleep mode will be released. Cancellation by Power-On Reset: A power-on reset of the SH7055SF resulting from driving the RES pin low, or caused by the WDT, cancels sleep mode. Rev.2.0, 07/03, page 858 of 960 Section 25 Reliability 25.1 Reliability A failure rate curve represents an index of the reliability of a semiconductor device. The failure rate curve traces a bathtub shape over the course of time, as is shown in figure 25.1. The curve is divided into three periods according to the type of failure phenomena: an initial failure period, a random failure period (functional lifetime), and a wear-out failure period. Initial failures, which occur during the initial failure period, are caused by contamination with foreign matter and localized chemical pollution; these can be eliminated by screening. Wear-out failures in the final period are caused by the deterioration of materials that make up semiconductor devices during long periods of usage. Random failures, which occur during the random failure period, are thought to occur in cases where a device with a minor failure is not removed by screening, and so is shipped, and then fails during the customer's production process or in the field, and in cases where a failure which should normally not have occurred until the wear-out period occurs earlier because of variations in production. Therefore, the reliability of semiconductor device is secured by appropriate screening to reduce the presence of initial failures and high reliability design to prevent the occurrence of wear-out failures. The reliability of a product is confirmed by producing a large quantity of prototypes for checking of the initial failure rate and executing accelerated life testing to identify the wear-out failure time in a realistic environment. Initial failure period Functional lifetime Wear-out failure period Failure rate Screening Random failure period Time Figure 25.1 Failure Rate Curve (Bathtub Curve) Rev. 2.0, 07/03, page 859 of 960 The reliability of products is estimated on the assumption that products developed for the automotive sector are used in a tougher environment than products for the consumer and industrial sectors. The representative failure phenomena of semiconductor devices, such as the dielectric breakdown of oxide films and electromigration in wiring, constitute wear-out failures. The stress factors in such failures are the voltage, current, and temperature applied to devices while they are in use. Since the temperature range for the guaranteed operation of products for use in automobiles is conventionally -40C to 85C, their reliability in terms of the above failure phenomena has to be confirmed by accelerated life testing at all temperatures in this range. Operation at temperatures in excess of 85C leads to failure within a short time, since high temperatures induce failures in semiconductor devices. Figure 25.2 shows the temperature dependence of semiconductor device lifetimes. The type of failure in this figure is a wear-out failure, i.e. the dielectric breakdown of oxide film. According to figure 25.2, the life at 125C is 1/10 of life at 85C, and operation at the higher temperature leads to a correspondingly higher probability of a failure in the field. Therefore, the reliability of operation at a temperature in excess of 85C is checked on the assumption that the period of operation at the upper-limit temperature of the range for guaranteed operation is 3000 hours. 100 Activation energy 0.6eV 10 Lifetime (log t) 1 0.1 0.01 125 85 50 Temperature (C) Figure 25.2 Temperature Reliability of Dielectric Breakdown of Oxide Film Rev. 2.0, 07/03, page 860 of 960 Section 26 Electrical Characteristics 26.1 Absolute Maximum Ratings Table 26.1 shows the absolute maximum ratings. Table 26.1 Absolute Maximum Ratings Item Power supply voltage* VCC and PLLVCC pins Symbol VCC Rating -0.3 to +4.3 Unit V Remarks The PLLCAP, EXTAL, XTAL, CK, and H-UDI pins are concerned. (VCC and PLLVCC are the same voltage) Except for the PLLCAP, EXTAL, XTAL, CK, and H-UDI pins and the analog input pin PVCC1 and PVCC2 pins PVCC -0.3 to +6.5 V Input voltage EXTAL and H-UDI pins All pins other than analog input, EXTAL, and H-UDI pins Vin Vin -0.3 to VCC + 0.3 -0.3 to PVCC + 0.3 V V Refer to table 26.2, Correspondence between Power Supply Names and Pins Analog supply voltage Analog reference voltage Analog input voltage AVCC AVref VAN -0.3 to +7.0 -0.3 to AVCC + 0.3 -0.3 to AVCC + 0.3 -40 to +125 V V V C Topr Operating temperature ** (except writing or erasing onchip flash memory) Operating temperature (writing or erasing on-chip flash memory) Storage temperature TWEopr -40 to +85 C Tstg -55 to +125 C [Operating precautions] Operating the LSI in excess of the absolute maximum ratings may result in permanent damage. The two power supply voltages of PVCC of 5V and VCC of 3V may be used simultaneously with the LSI. Be sure to use the LSI in compliance with the connection of power pins, combination conditions of applicable power supply voltages, voltage applicable to each pin, and conditions of output voltage, as specified in the manual. Connecting a non-specified power supply or using the LSI at an incorrect voltage may result in permanent damage of the LSI or the system that contains the LSI. Rev.2.0, 07/03, page 861 of 960 Note: * Do not apply any power supply voltage to the VCL pin. Connect to GND through an external capacitor. ** When this LSI is used at temperatures in excess of the range from -40 to +85 C, it can be operated within following accumulated hours. Temperature Range for Operation 85 to 105 C Accumulated Time 3000 hours Rev.2.0, 07/03, page 862 of 960 26.2 DC Characteristics Table 26.2 shows the correspondence between power supply names and pins. Table 26.4 shows DC characteristics. Table 26.2 Correspondence between Power Supply Names and Pins Power Supply Pin Power Supply Dedicated Function Name Pin 1 PD8 PD9 PD10 PD11 PD12 PD13 PE0 PE1 PE2 PE3 VCC PE4 VSS PE5 PE6 PE7 PE8 PE9 PE10 PVCC1 PE11 VSS PE12 A12 PVCC1 PVCC1+0.3 A11 PVCC1 PVCC1+0.3 A5 A6 A7 A8 A9 A10 PVCC1 PVCC1 PVCC1 PVCC1 PVCC1 PVCC1 PVCC1+0.3 PVCC1+0.3 PVCC1+0.3 PVCC1+0.3 PVCC1+0.3 PVCC1+0.3 A4 PVCC1 PVCC1+0.3 Output Circuit Power Function Function Function Supply 2 3 4 Name User Pin PULS0 PULS1 PULS2 PULS3 PULS4 PULS6 A0 A1 A2 A3 HTxD0 HTxD1 PVCC2 PVCC2 PVCC2 PVCC2 PVCC2 PVCC2 PVCC1 PVCC1 PVCC1 PVCC1 Pin No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 Input Voltage Upper Limit (V) PVCC2+0.3 PVCC2+0.3 PVCC2+0.3 PVCC2+0.3 PVCC2+0.3 PVCC2+0.3 PVCC1+0.3 PVCC1+0.3 PVCC1+0.3 PVCC1+0.3 Notes Rev.2.0, 07/03, page 863 of 960 Table 26.2 Correspondence between Power Supply Names and Pins (cont) Power Supply Pin Power Supply Dedicated Function Name Pin 1 PE13 PE14 PE15 PF0 PF1 PF2 VCL PF3 VSS PF4 PF5 PF6 PF7 PF8 PF9 PVCC1 PF10 VSS PF11 PF12 PF13 PF14 PF15 VSS CK VCC MD2 EXTAL VCC XTAL VCC 5.5+0.3 VCC+0.3 VCC CS1 CS2 CS3 BACK BREQ PVCC1 PVCC1 PVCC1 PVCC1 PVCC1 PVCC1+0.3 PVCC1+0.3 PVCC1+0.3 PVCC1+0.3 PVCC1+0.3 CS0 PVCC1 PVCC1+0.3 A20 A21 WRL WRH WAIT RD POD PVCC1 PVCC1 PVCC1 PVCC1 PVCC1 PVCC1 PVCC1+0.3 PVCC1+0.3 PVCC1+0.3 PVCC1+0.3 PVCC1+0.3 PVCC1+0.3 A19 PVCC1 PVCC1+0.3 Output Circuit Power Function Function Function Supply 2 3 4 Name User Pin A13 A14 A15 A16 A17 A18 PVCC1 PVCC1 PVCC1 PVCC1 PVCC1 PVCC1 Pin No. 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 Input Voltage Upper Limit (V) PVCC1+0.3 PVCC1+0.3 PVCC1+0.3 PVCC1+0.3 PVCC1+0.3 PVCC1+0.3 Notes Rev.2.0, 07/03, page 864 of 960 Table 26.2 Correspondence between Power Supply Names and Pins (cont) Power Supply Pin Power Supply Dedicated Function Name Pin 1 VSS MD1 FWE HSTBY RES MD0 PLLVCC PLLCAP PLLVSS PH0 PH1 PH2 PH3 PH4 PH5 PH6 PVCC1 PH7 VSS PH8 PH9 VCC PH10 VSS PH11 PH12 PH13 PH14 PH15 PVCC1 D11 D12 D13 D14 D15 PVCC1 PVCC1 PVCC1 PVCC1 PVCC1 PVCC1+0.3 PVCC1+0.3 PVCC1+0.3 PVCC1+0.3 PVCC1+0.3 D10 PVCC1 PVCC1+0.3 D8 D9 PVCC1 PVCC1 PVCC1+0.3 PVCC1+0.3 D7 PVCC1 PVCC1+0.3 D0 D1 D2 D3 D4 D5 D6 PVCC1 PVCC1 PVCC1 PVCC1 PVCC1 PVCC1 PVCC1 PVCC1+0.3 PVCC1+0.3 PVCC1+0.3 PVCC1+0.3 PVCC1+0.3 PVCC1+0.3 PVCC1+0.3 5.5+0.3 5.5+0.3 5.5+0.3 5.5+0.3 5.5+0.3 Output Circuit Power Function Function Function Supply 2 3 4 Name User Pin Pin No. 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 Input Voltage Upper Limit (V) Notes Rev.2.0, 07/03, page 865 of 960 Table 26.2 Correspondence between Power Supply Names and Pins (cont) Power Supply Pin Power Supply Dedicated Function Name Pin 1 NMI VSS AN0 AN1 AN2 AN3 AN4 AN5 AN6 AN7 AN8 AN9 AN10 AN11 AN12 AVSS AVref AVCC AN13 AN14 AN15 AN16 AN17 AN18 AN19 AN20 AN21 AN22 AN23 AN24 AVCC+0.3 AVCC+0.3 AVCC+0.3 AVCC+0.3 AVCC+0.3 AVCC+0.3 AVCC+0.3 AVCC+0.3 AVCC+0.3 AVCC+0.3 AVCC+0.3 AVCC+0.3 AVCC+0.3 AVCC+0.3 AVCC+0.3 AVCC+0.3 AVCC+0.3 AVCC+0.3 AVCC+0.3 AVCC+0.3 AVCC+0.3 AVCC+0.3 AVCC+0.3 AVCC+0.3 AVCC+0.3 Output Circuit Power Function Function Function Supply 2 3 4 Name User Pin Pin No. 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 Input Voltage Upper Limit (V) 5.5+0.3 Notes Rev.2.0, 07/03, page 866 of 960 Table 26.2 Correspondence between Power Supply Names and Pins (cont) Power Supply Pin Power Supply Dedicated Function Name Pin 1 AN25 AN26 AN27 AN28 AN29 AVCC AVref AVSS AN30 AN31 WDTOVF PA0 TI0A PVCC2 PVCC2 PVCC2+0.3 Schmitttrigger input pin AVCC+0.3 AVCC+0.3 Output Circuit Power Function Function Function Supply 2 3 4 Name User Pin Pin No. 114 115 116 117 118 119 120 121 122 123 124 125 Input Voltage Upper Limit (V) AVCC+0.3 AVCC+0.3 AVCC+0.3 AVCC+0.3 AVCC+0.3 Notes 126 127 VSS PA1 TI0B PVCC2 PVCC2+0.3 Schmitttrigger input pin 128 129 130 131 132 133 134 135 136 137 138 139 PVCC2 PA2 PA3 PA4 PA5 PA6 PA7 PA8 PA9 PA10 PA11 VCC TI0C TI0D TIO3A TIO3B TIO3C TIO3D TIO4A TIO4B TIO4C TIO4D PVCC2 PVCC2 PVCC2 PVCC2 PVCC2 PVCC2 PVCC2 PVCC2 PVCC2 PVCC2 PVCC2+0.3 PVCC2+0.3 PVCC2+0.3 PVCC2+0.3 PVCC2+0.3 PVCC2+0.3 PVCC2+0.3 PVCC2+0.3 PVCC2+0.3 PVCC2+0.3 Schmitttrigger input pin Rev.2.0, 07/03, page 867 of 960 Table 26.2 Correspondence between Power Supply Names and Pins (cont) Power Supply Pin Power Supply Dedicated Function Name Pin 1 PA12 Output Circuit Power Function Function Function Supply 2 3 4 Name User Pin TIO5A PVCC2 Pin No. 140 Input Voltage Upper Limit (V) PVCC2+0.3 Notes Schmitttrigger input pin 141 142 VSS PA13 TIO5B PVCC2 PVCC2+0.3 Schmitttrigger input pin 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 VSS PVCC2 PA14 PA15 PB0 PB1 PB2 TxD0 RxD0 TO6A TO6B TO6C PVCC2 PVCC2 PVCC2 PVCC2 PVCC2 PVCC2+0.3 PVCC2+0.3 PVCC2+0.3 PVCC2+0.3 PVCC2+0.3 PB3 TO6D PVCC2 PVCC2+0.3 PB4 PB5 PB6 PB7 PB8 PB9 PB10 PB11 PB12 TO7A TO7B TO7C TO7D TxD3 RxD3 TxD4 RxD4 TCLKA TO8A TO8B TO8C TO8D TO8E TO8F HTxD0 HRxD0 UBCTRG TO8G TO8H PVCC2 PVCC2 PVCC2 PVCC2 PVCC2 PVCC2 PVCC2 PVCC2 PVCC2 PVCC2+0.3 PVCC2+0.3 PVCC2+0.3 PVCC2+0.3 PVCC2+0.3 PVCC2+0.3 PVCC2+0.3 PVCC2+0.3 PVCC2+0.3 Schmitttrigger input pin 160 161 162 VCL PB13 SCK0 PVCC2 PVCC2+0.3 PB14 SCK1 TCLKB TI10 PVCC2 PVCC2+0.3 Schmitttrigger input pin 163 VSS Rev.2.0, 07/03, page 868 of 960 Table 26.2 Correspondence between Power Supply Names and Pins (cont) Power Supply Pin Power Supply Dedicated Function Name Pin 1 PB15 Output Circuit Power Function Function Function Supply 2 3 4 Name User Pin PULS5 SCK2 PVCC2 Pin No. 164 Input Voltage Upper Limit (V) PVCC2+0.3 Notes Schmitttrigger input pin 165 166 167 168 169 PC0 PC1 PC2 PC3 PC4 TxD1 RxD1 TxD2 RxD2 IRQ0 PVCC2 PVCC2 PVCC2 PVCC2 PVCC2 PVCC2+0.3 PVCC2+0.3 PVCC2+0.3 PVCC2+0.3 PVCC2+0.3 Schmitttrigger input pin 170 171 PG0 PG1 PULS7 IRQ1 HRxD0 HRxD1 PVCC2 PVCC2 PVCC2+0.3 PVCC2+0.3 Schmitttrigger input pin 172 173 PVCC2 PG2 IRQ2 ADEND PVCC2 PVCC2+0.3 Schmitttrigger input pin 174 175 176 177 178 179 180 181 182 183 184 185 186 VSS PG3 PJ0 PJ1 PJ2 PJ3 PJ4 PJ5 PJ6 PJ7 PJ8 VSS PJ9 TIO5D PVCC2 PVCC2+0.3 Schmitttrigger input pin IRQ3 TIO2A TIO2B TIO2C TIO2D TIO2E TIO2F TIO2G TIO2H TIO5C ADTRG0 PVCC2 PVCC2 PVCC2 PVCC2 PVCC2 PVCC2 PVCC2 PVCC2 PVCC2 PVCC2 PVCC2+0.3 PVCC2+0.3 PVCC2+0.3 PVCC2+0.3 PVCC2+0.3 PVCC2+0.3 PVCC2+0.3 PVCC2+0.3 PVCC2+0.3 PVCC2+0.3 Schmitttrigger input pin Rev.2.0, 07/03, page 869 of 960 Table 26.2 Correspondence between Power Supply Names and Pins (cont) Power Supply Pin Power Supply Dedicated Function Name Pin 1 VCC PJ10 PJ11 PJ12 PJ13 PJ14 PJ15 PVCC2 PK0 VSS PK1 PK2 PK3 PK4 PK5 PK6 VCC PK7 VSS PK8 PK9 PK10 PK11 PK12 PK13 PVCC2 PK14 VSS PK15 TO8P PVCC2 PVCC2+0.3 TO8O PVCC2 PVCC2+0.3 TO8I TO8J TO8K TO8L TO8M TO8N PVCC2 PVCC2 PVCC2 PVCC2 PVCC2 PVCC2 PVCC2+0.3 PVCC2+0.3 PVCC2+0.3 PVCC2+0.3 PVCC2+0.3 PVCC2+0.3 TO8H PVCC2 PVCC2+0.3 TO8B TO8C TO8D TO8E TO8F TO8G PVCC2 PVCC2 PVCC2 PVCC2 PVCC2 PVCC2 PVCC2+0.3 PVCC2+0.3 PVCC2+0.3 PVCC2+0.3 PVCC2+0.3 PVCC2+0.3 TO8A PVCC2 PVCC2+0.3 TI9A TI9B TI9C TI9D TI9E TI9F PVCC2 PVCC2 PVCC2 PVCC2 PVCC2 PVCC2 PVCC2+0.3 PVCC2+0.3 PVCC2+0.3 PVCC2+0.3 PVCC2+0.3 PVCC2+0.3 Schmitttrigger input pin Output Circuit Power Function Function Function Supply 2 3 4 Name User Pin Pin No. 187 188 189 190 191 192 193 194 195 196 197 198 199 200 201 202 203 204 205 206 207 208 209 210 211 212 213 214 215 Input Voltage Upper Limit (V) Notes Rev.2.0, 07/03, page 870 of 960 Table 26.2 Correspondence between Power Supply Names and Pins (cont) Power Supply Pin Power Supply Dedicated Function Name Pin 1 PL0 PL1 PL2 PL3 PL4 PL5 PL6 PL7 PL8 VCL PL9 SCK4 IRQ5 PVCC2 PVCC2+0.3 Schmitttrigger input pin Output Circuit Power Function Function Function Supply 2 3 4 Name User Pin TI10 TIO11A TIO11B TCLKB ADTRG0 ADTRG1 ADEND SCK2 SCK3 IRQ6 IRQ7 PVCC2 PVCC2 PVCC2 PVCC2 PVCC2 PVCC2 PVCC2 PVCC2 PVCC2 Pin No. 216 217 218 219 220 221 222 223 224 225 226 Input Voltage Upper Limit (V) PVCC2+0.3 PVCC2+0.3 PVCC2+0.3 PVCC2+0.3 PVCC2+0.3 PVCC2+0.3 PVCC2+0.3 PVCC2+0.3 PVCC2+0.3 Notes Schmitttrigger input pin Schmitttrigger input pin 227 228 229 230 VSS PL10 PL11 PL12 HTxD0 HRxD0 IRQ4 HTxD1 HRxD1 HTxD0 and 1 PVCC2 PVCC2+0.3 PVCC2+0.3 PVCC2+0.3 Schmitttrigger input pin HRxD0, 1 PVCC2 PVCC2 231 232 233 234 235 236 237 238 239 VSS VCC PL13 TMS TRST TDI TDO TCK AUDRST IRQOUT IRQOUT PVCC2 PVCC2+0.3 VCC+0.3 VCC+0.3 VCC+0.3 VCC VCC+0.3 PVCC2+0.3 Rev.2.0, 07/03, page 871 of 960 Table 26.2 Correspondence between Power Supply Names and Pins (cont) Power Supply Pin Power Supply Dedicated Function Name Pin 1 AUDMD AUDATA0 AUDATA1 AUDATA2 AUDATA3 AUDCK AUDSYNC PVCC2 PD0 TIO1A PVCC2 PVCC2+0.3 Schmitttrigger input pin PVCC2 PVCC2 PVCC2 PVCC2 PVCC2 PVCC2 Output Circuit Power Function Function Function Supply 2 3 4 Name User Pin Pin No. 240 241 242 243 244 245 246 247 248 Input Voltage Upper Limit (V) PVCC2+0.3 PVCC2+0.3 PVCC2+0.3 PVCC2+0.3 PVCC2+0.3 PVCC2+0.3 PVCC2+0.3 Notes 249 250 251 252 253 254 255 256 VSS PD1 PD2 PD3 PD4 PD5 PD6 PD7 TIO1B TIO1C TIO1D TIO1E TIO1F TIO1G TIO1H PVCC2 PVCC2 PVCC2 PVCC2 PVCC2 PVCC2 PVCC2 PVCC2+0.3 PVCC2+0.3 PVCC2+0.3 PVCC2+0.3 PVCC2+0.3 PVCC2+0.3 PVCC2+0.3 Schmitttrigger input pin Rev.2.0, 07/03, page 872 of 960 Usage Notes Set power supply voltages during LSI operation as shown below. VCC = PLLVCC = 3.3 V 0.3 V, PVCC1 = 5.0 V 0.5 V/3.3 V 0.3 V, PVCC2 = 5.0 V 0.5 V, AVCC = 5.0 V 0.5 V, AVref = 4.5 V to AVCC, VSS = PLLVSS = AVSS = 0 V When PVCC1 = 3.3 V 0.3 V, VCC = PVCC1 The PVCC1 power supply voltage depends on the operating mode as shown below. Operation cannot be guaranteed with other PVCC1 power supply voltages. Table 26.3 PVCC1 Voltage in Each Operating Mode Operating Mode No. Pin Setting FEW Mode 0 Mode 1 Mode 2 Mode 3 Mode 4 Mode 5 Mode 6 Mode 7 Mode 8 Mode 9 0 0 0 0 1 1 1 1 1 1 MD2 1 1 1 1 1 1 1 1 0 0 MD1 0 0 1 1 0 0 1 1 0 0 MD0 0 1 0 1 0 1 0 1 0 1 User boot mode User program mode MCU Single-chip mode 5.0 V 0.5 V Boot mode 3.3 V 0.3 V 5.0 V 0.5 V 3.3 V 0.3 V 5.0 V 0.5 V 3.3 V 0.3 V 5.0 V 0.5 V MCU expanded mode 3.3 V 0.3 V Mode Name PVCC1 Voltage Rev.2.0, 07/03, page 873 of 960 Table 26.4 DC Characteristics Conditions: VCC = PLLVCC = 3.3 V 0.3 V, PVCC1 = 5.0 V 0.5 V/3.3 V 0.3 V, PVCC2 = 5.0 V 0.5 V, AVCC = 5.0 V 0.5 V, AVref = 4.5 V to AVCC, VSS = PLLVSS = AVSS = 0 V, Ta = -40C to 125C. When PVCC1 = 3.3 V 0.3 V, VCC = PVCC1. When writing or erasing on-chip flash memory, Ta = -40C to 85C. Item Input highlevel voltage (except Schmitt trigger input voltage) RES, NMI, FWE, MD2-0, HSTBY EXTAL D15-D0, WAIT, BREQ (When in MCU expansion mode) PE15-PE0, PF15- PF0, PH15-PH0 (When in MCU expansion mode) TRST TMS, TDI, TCK AUDRST, AUDMD PG0, PL11 Other input pins Input lowlevel voltage (except Schmitt trigger input voltage) RES, NMI, FWE, MD2-0, HSTBY, TRST, AUDRST, AUDMD PG0, PL11 Other input pins VIL Symbol VIH Min VCC - 0.5 VCC x 0.7 2.2 Typ -- -- -- Max 5.8 VCC + 0.3 Unit V V PVCC1 = 3.3 V 0.3 V PVCC1 = 3.3 V 0.3 V Measurement Conditions 2.7 V VCC 3.6V PVCC1 + V 0.3 PVCC1 + V 0.3 2.2 -- VCC - 0.5 2.2 VCC - 0.5 PVCC x 0.7 2.2 -0.3 -- -- -- -- -- -- VCC + 0.3 VCC + 0.3 V V PVCC2 + V 0.3 PVCC2 + V 0.3 PVcc + 0.3 0.5 V V 2.7 V VCC 3.6V -0.3 -0.3 -- -- PVCC2 x V 0.3 0.8 V Rev.2.0, 07/03, page 874 of 960 Table 26.4 DC Characteristics (cont) Conditions: VCC = PLLVCC = 3.3 V 0.3 V, PVCC1 = 5.0 V 0.5 V/3.3 V 0.3 V, PVCC2 = 5.0 V 0.5 V, AVCC = 5.0 V 0.5 V, AVref = 4.5 V to AVCC, VSS = PLLVSS = AVSS = 0 V, Ta = -40C to 125C. When PVCC1 = 3.3 V 0.3 V, VCC = PVCC1. When writing or erasing on-chip flash memory, Ta = -40C to 85C. Item Schmitt trigger input voltage Symbol TI0A-TI0D, (VIH) + TIO1A-TIO1H, VT TIO2A-TIO2H, TIO3A-TIO3D, TIO4A-TIO4D, TIO5A-TIO5D, TI9A-TI9F, TI10, TIO11A-TIO11B, TCLKA, TCLKB, ADTRG0, ADTRG1, SCK0-SCK4, IRQ0-IRQ7 and when thses pins are selected as I/O ports (VIL) - VT VT - VT Input leak current RES, NMI, FWE, MD2-0, HSTBY, EXTAL (Standby) TMS, TRST, TDI, TCK (Standby) AUDMD, AUDCK, AUDSYNC, AUDATA3-0 (Standby) AUDRST (Standby) | lin | + - Min 4.0 Typ -- Max Unit Measurement Conditions Refer to table 26.2, Correspondence between Power Supply Names and Pins (PVCC2 V + 0.3) (-0.3) 0.4 -- -- -- -- 1.0 -- 3.0* 6.0* 1 2 V V A A A A Vin = 0.5 V to 5.8 V Vin = 0.5 V to VCC - 0.5 V Vin = 0.5 V to VCC - 0.5 V Vin = 0.5 V to PVCC2 - 0.5 V -- -- 3.0* 6.0* 1 2 1 -- -- 3.0* 6.0* 2 1 2 -- -- 3.0* 6.0* -- -- 3.0* 6.0* 1 A A 2 1 Vin = 0.5 V to PVCC2 - 0.5 V Vin = 0 to AVCC A/D port -- -- 0.2* 0.4* 2 Rev.2.0, 07/03, page 875 of 960 Table 26.4 DC Characteristics (cont) Conditions: VCC = PLLVCC = 3.3 V 0.3 V, PVCC1 = 5.0 V 0.5 V/3.3 V 0.3 V, PVCC2 = 5.0 V 0.5 V, AVCC = 5.0 V 0.5 V, AVref = 4.5 V to AVCC, VSS = PLLVSS = AVSS = 0 V, Ta = -40C to 125C. When PVCC1 = 3.3 V 0.3 V, VCC = PVCC1. When writing or erasing on-chip flash memory, Ta = -40C to 85C. Item Input leak current Symbol D15-D0, WAIT, BREQ | lin | Min -- Typ -- Max 3.0* 6.0* PE15-PE0, PF15- PF0, PH15-PH0 (When in MCU expansion mode) Other input pins Input pull-up TMS, TRST, TDI, TCK -Ipu MOS current (pull-up characteristic) AUDMD, AUDCK, AUDSYNC, AUDATA3-0 (pull-up characteristic) Input pulldown MOS current Three-state leak current (while OFF) AUDRST (pull-down characteristic) A21-A0, D15-D0, CS3-CS0, WRH, WRL, RD, BACK (When in MCU expansion mode) A21-A0, D15-D0, CS3-CS0, WRH, WRL, RD, BACK (When in MCU expansion mode) PE15-PE0, PF15- PF0, PH15-PH0 (When in MCU expansion mode) CK, TDO Ipd -- -- 3.0* 6.0* 1 Unit A Measurement Conditions Vin = 0.5 V to PVCC1 - 0.5 V PVCC1 = 3.3 V 0.3 V Vin = 0.5 V to PVCC1 - 0.5 V PVCC1 = 3.3 V 0.3 V Vin = 0.5 V to PVCC2 - 0.5 V Vin = 0 V Vin = 0 V 2 1 A 2 -- -- 3.0* 6.0* 1 A A A 2 -- -- -- -- 350 800 -- -- 500 A Vin = PVCC2 l Its l -- -- 3.0* 6.0* 1 A 2 Vin = 0.5 to PVCC1 - 0.5 V PVCC1 = 3.3 V 0.3 V IOH = 200 A PVCC1 = 3.3 V 0.3 V Output highlevel voltage VOH PVcc1- -- 0.5 -- V PVcc1- -- 0.5 -- V IOH = 200 A PVCC1 = 3.3 V 0.3 V IOH = 200 A VCC - 0.5 -- -- V Rev.2.0, 07/03, page 876 of 960 Table 26.4 DC Characteristics (cont) Conditions: VCC = PLLVCC = 3.3 V 0.3 V, PVCC1 = 5.0 V 0.5 V/3.3 V 0.3 V, PVCC2 = 5.0 V 0.5 V, AVCC = 5.0 V 0.5 V, AVref = 4.5 V to AVCC, VSS = PLLVSS = AVSS = 0 V, Ta = -40C to 125C. When PVCC1 = 3.3 V 0.3 V, VCC = PVCC1. When writing or erasing on-chip flash memory, Ta = -40C to 85C. Item Output highlevel voltage Other output pins Symbol VOH Min PVCC - 0.5 PVCC - 1.0 Output lowlevel voltage A21-A0, D15-D0, CS3-CS0, WRH, WRL, RD, BACK (When in MCU expansion mode) PE15-PE0, PF15- PF0, PH15-PH0 (When in MCU expansion mode) Other output pins (except XTAL) Input capacitance RES NMI All other input pins Current Normal operation consumption Sleep Standby ICC Cin VOL -- Typ -- -- -- Max -- -- 0.4 Unit V V V Measurement Conditions IOH = 200 A IOH = 1 mA IOL = 1.6 mA PVCC1 = 3.3 V 0.3 V -- -- 0.4 V IOL = 1.6 mA PVCC1 = 3.3 V 0.3 V IOL = 1.6 mA IOL = 6 mA Vin = 0 V f = 1 MHz Ta = 25C f = 40 MHz Ta 50C 50C < Ta105C Ta > 105C VCC = 3.3 V f = 40 MHz -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- 50 40 50 -- -- 60 1.2 1 0.4 1.2 60 30 20 80 60 200 500 1000 90 5 30 V V pF pF pF mA mA A A A mA mA A Write operation Analog supply current During A/D conversion Awaiting A/D conversion AlCC -- -- -- Rev.2.0, 07/03, page 877 of 960 Table 26.4 DC Characteristics (cont) Conditions: VCC = PLLVCC = 3.3 V 0.3 V, PVCC1 = 5.0 V 0.5 V/3.3 V 0.3 V, PVCC2 = 5.0 V 0.5 V, AVCC = 5.0 V 0.5 V, AVref = 4.5 V to AVCC, VSS = PLLVSS = AVSS = 0 V, Ta = -40C to 125C. When PVCC1 = 3.3 V 0.3 V, VCC = PVCC1. When writing or erasing on-chip flash memory, Ta = -40C to 85C. Item During A/D Reference power supply conversions current Awaiting A/D conversion RAM standby voltage Notes: *1 Ta105C *2 Ta>105C Symbol Alref Min -- -- VRAM 2.7 Typ 1.3 1.1 -- Max 5 10 -- Unit mA A V VCC Measurement Conditions AVref = 5 V [Operating precautions] 1. When the A/D converter is not used (including during standby), do not leave the AVCC, AVref, and AVSS pins open. 2. The current consumption is measured when VIHmin = VCC - 0.3 V/PVCC - 0.3 V, VIL = 0.3 V, with all output pins unloaded. 3. The guaranteed operating range of power supply PVCC1 in the MCU expanded modes is only PVCC1 = 3.3 V 0.3 V. Do not use a voltage outside this range. 4. The guaranteed operating range of power supply PVCC1 in MCU single-chip mode is only PVCC1 = 5.0 V 0.5 V. Do not use a voltage outside this range. Rev.2.0, 07/03, page 878 of 960 Table 26.5 Permitted Output Current Values Conditions: VCC = PLLVCC = 3.3 V 0.3 V, PVCC1 = 5.0 V 0.5 V/3.3 V 0.3 V, PVCC2 = 5.0 V 0.5 V, AVCC = 5.0 V 0.5 V, AVref = 4.5V to AVCC, VSS = PLLVSS = AVSS = 0 V, Ta = -40C to 125C. When PVCC1 = 3.3 V 0.3 V, VCC = PVCC1. When writing or erasing on-chip flash memory, Ta = -40C to 85C. Item Output low-level permissible current (per pin) Output low-level permissible current (total) Output high-level permissible current (per pin) Output high-level permissible current (total) Symbol IOL IOL IOH IOL Min -- -- -- -- Typ -- -- -- -- Max 6 80 2 25 Unit mA mA mA mA [Operating precautions] To assure LSI reliability, do not exceed the output values listed in this table. Rev.2.0, 07/03, page 879 of 960 26.3 26.3.1 AC Characteristics Timing for swicthing the power supply on/off Table 26.6 Timing for swicthing the power supply on/off Conditions: VCC = PLLVCC = 3.3 V 0.3 V, PVCC1 = 5.0 V 0.5 V/3.3 V 0.3 V, PVCC2 = 5.0 V 0.5 V, AVCC = 5.0 V 0.5 V, AVref = 4.5 V to AVCC, VSS = PLLVSS = AVSS = 0 V, Ta = -40C to 125C. When PVCC1 = 3.3 V 0.3 V, VCC = PVCC1. When writing or erasing on-chip flash memory, Ta = -40C to 85C. Item Time taken to switch VCC on VCC hold-time when PVCC is swtched off Symbol tVCCS tVCCH Min 0 0 Max -- -- Unit ms ms Figures Figure 26.1 VCC PLLVCC VCC min tVCCS tVCCH VCC min PVCC1 PVCC2 PVCC min PVCC min Figure 26.1 Power-On/Off Timing Rev.2.0, 07/03, page 880 of 960 26.3.2 Clock Timing Table 26.7 shows the clock timing. Table 26.7 Clock Timing Conditions: VCC = PLLVCC = 3.3 V 0.3 V, PVCC1 = 5.0 V 0.5 V/3.3 V 0.3 V, PVCC2 = 5.0 V 0.5 V, AVCC = 5.0 V 0.5 V, AVref = 4.5 V to AVCC, VSS = PLLVSS = AVSS = 0 V, Ta = -40C to 125C. When PVCC1 = 3.3 V 0.3 V, VCC = PVCC1. When writing or erasing on-chip flash memory, Ta = -40C to 85C. Item Operating frequency Clock cycle time Clock low-level pulse width Clock high-level pulse width Clock rise time Clock fall time EXTAL clock input frequency EXTAL clock input cycle time EXTAL clock input low-level pulse width EXTAL clock input low-level pulse width EXTAL clock input rise time EXTAL clock input fall time Reset oscillation settling time Standby return clock settling time Symbol fop tcyc t t t t CL Min 20 25 4 4 -- -- 5 100 30 30 -- -- 30 30 Max 40 50 -- -- 8 8 10 200 -- -- 8 8 -- -- Unit MHz ns ns ns ns ns MHz ns ns ns ns ns ms ms Figures Figure 26.2 CH CR CF f t EX Figure 26.3 EXcyc t t t EXL EXH EXR t EXF tosc1 tosc2 Figure 26.4 [Operating precautions] The EXTAL, XTAL, and CK pins constitute a circuit requiring a power supply voltage of VCC = 3.3 V 0.3 V. Comply with the input and output voltages specified in the DC characteristics. Rev.2.0, 07/03, page 881 of 960 tcyc tCH tCL VOH 1/2VCC CK 1/2VCC VOH VOH VOL tCF VOL tCR Note: CK pin is VCC = 3.3 V 0.3 V power supply circuit. Figure 26.2 System Clock Timing tEXcyc tEXH VIH 1/2VCC VIH VIL tEXF VIL tEXL EXTAL VIH 1/2VCC tEXR Note: EXTAL pin is VCC = 3.3 V 0.3 V power supply circuit. Figure 26.3 EXTAL Clock Input Timing CK VCC PVCC1 PVCC2 VCC min tosc2 PVCC min VIH tosc1 tosc1 Figure 26.4 Oscillation Settling Time Rev.2.0, 07/03, page 882 of 960 26.3.3 Control Signal Timing Table 26.8 shows control signal timing. Table 26.8 Control Signal Timing Conditions: VCC = PLLVCC = 3.3 V 0.3 V, PVCC1 = 5.0 V 0.5 V/3.3 V 0.3 V, PVCC2 = 5.0 V 0.5 V, AVCC = 5.0 V 0.5 V, AVref = 4.5 V to AVCC, VSS = PLLVSS = AVSS = 0 V, Ta = -40C to 125C. When PVCC1 = 3.3 V 0.3 V, VCC = PVCC1. When writing or erasing on-chip flash memory, Ta = -40C to 85C. Item RES pulse width RES setup time MD2-MD0 setup time NMI setup time IRQ7-IRQ0 setup time* (edge detection) 1 1 Symbol tRESW tRESS tMDS tNMIS tIRQES tIRQLS tNMIH tIRQEH tIRQOD tBRQS tBACKD1 tBACKD2 tBZD Min 20 40 20 24 24 24 24 24 -- 24 -- -- -- Max -- -- -- -- -- -- -- -- 100 -- 30 30 30 Unit tcyc ns tcyc ns ns ns ns ns ns ns ns ns ns Figures Figure 26.5 Figure 26.6 IRQ7-IRQ0 setup time* (level detection) NMI hold time IRQ7-IRQ0 hold time IRQOUT output delay time Bus request setup time Bus acknowledge delay time 1 Bus acknowledge delay time 2 Bus three-state delay time Figure 26.7 Figure 26.8* 2 [Operating precautions] *1 The RES, NMI, and IRQ7-IRQ0 signals are asynchronous inputs, but when the setup times shown here are provided, the signals are considered to have been changed at clock fall. If the setup times are not provided, recognition is delayed until the next clock rise or fall. *2 The guaranteed operating range of power supply PVCC1 in the MCU expanded modes is only PVCC1 = 3.3 V 0.3 V. Do not use a voltage outside this range. Rev.2.0, 07/03, page 883 of 960 VOH CK tRESS tRESW VIL = 0.5 V tMDS tRESS VIH = VCC - 0.5 V VIH = VCC - 0.5 V VIL = 0.5 V VIH = VCC - 0.5 V MD2-MD0 VIL = 0.5 V Note: pin is controlled by VIL and VIH shown above. Figure 26.5 Reset Input Timing CK VOL VOL tNMIH VIH = VCC - 0.5 V NMI VIL = 0.5 V tIRQEH edge tNMIS VIH = VCC - 0.5 V VIL = 0.5 V tIRQES VIH VIL tIRQLS level VIL Note: NMI pin is controlled by VIL and VIH shown above. Figure 26.6 Interrupt Signal Input Timing Rev.2.0, 07/03, page 884 of 960 CK VOH tIRQOD VOH VOL tIRQOD Figure 26.7 Interrupt Signal Output Timing VOH CK tBRQS (input) tBACKD1 (output) tBZD , , , Hi-Z tBZD A21-A0, D15-D0 Hi-Z VOL VOL tBRQS VIH tBACKD2 VOH VOL VOH VOH Figure 26.8 Bus Right Release Timing Rev.2.0, 07/03, page 885 of 960 26.3.4 Bus Timing Table 26.9 shows bus timing. Table 26.9 Bus Timing Conditions: VCC = PLLVCC = 3.3 V 0.3 V, PVCC1 = 5.0 V 0.5 V/3.3 V 0.3 V, PVCC2 = 5.0 V 0.5 V, AVCC = 5.0 V 0.5 V, AVref = 4.5 V to AVCC, VSS = PLLVSS = AVSS = 0 V, Ta = -40C to 125C. When PVCC1 = 3.3 V 0.3 V, VCC = PVCC1. When writing or erasing on-chip flash memory, Ta = -40C to 85C. Item Address delay time CS delay time 1 CS delay time 2 Read strobe delay time 1 Read strobe delay time 2 Read data setup time Read data hold time Write strobe delay time 1 Write strobe delay time 2 Write data delay time Write data hold time WAIT setup time WAIT hold time Read data access time Access time from read strobe Write address setup time Write address hold time Symbol tAD tCSD1 tCSD2 tRSD1 tRSD2 tRDS tRDH tWSD1 tWSD2 tWDD tWDH tWTS tWTH tACC tOE tAS tWR Min -- -- -- -- -- 15 0 -- -- -- tcyc x m 15 0 tcyc x (n+1.5) - 39 tcyc x (n+1.0) - 39 0 5 Max 35 30 30 30 30 -- -- 30 30 30 -- -- -- -- -- -- -- Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns Figure 26.9, 26.10 Figure 26.11 Figures Figure 26.9, 26.10 n: Number of waits m = 1: CS assertion extension cycle m = 0: Normal cycle (CS assertion non-extension cycle) [Operating precautions] The guaranteed operating range of power supply PVCC1 in the MCU expanded modes is only PVCC1 = 3.3 V 0.3 V. Do not use a voltage outside this range. Rev.2.0, 07/03, page 886 of 960 T1 VOH CK tAD A21-A0 tCSD1 VOL T2 tCSD2 tRSD1 tOE tRSD2 (read) tACC D15-D0 (read) tWSD1 tAS tWDD D15-D0 (write) tWDH tWSD2 tWR tRDS tRDH (write) Note: tRDH: Specified from the negate timing of A21-A0, , or , whichever is first. Figure 26.9 Basic Cycle (No Waits) Rev.2.0, 07/03, page 887 of 960 T1 VOH CK tAD A21-A0 tCSD1 VOL TW T2 tCSD2 tRSD1 tOE tRSD2 (read) tACC D15-D0 (read) tWSD1 tAS tWDD D15-D0 (write) tWDH tWSD2 tWR tRDS tRDH (write) Note: tRDH: Specified from the negate timing of A21-A0, , or , whichever is first. Figure 26.10 Basic Cycle (One Software Wait) Rev.2.0, 07/03, page 888 of 960 T1 CK TW TW TWO T2 A21-A0 (read) D15-D0 (read) (write) D15-D0 (write) tWTS tWTH tWTS tWTH Note: tRDH: Specified from the negate timing of A21-A0, , or , whichever is first. Figure 26.11 Basic Cycle (Two Software Waits + Waits by WAIT Signal) Rev.2.0, 07/03, page 889 of 960 26.3.5 Advanced Timer Unit Timing and Advance Pulse Controller Timing Table 26.10 shows advanced timer unit timing and advanced pulse controller timing. Table 26.10 Advanced Timer Unit Timing and Advanced Pulse Controller Timing Conditions: VCC = PLLVCC = 3.3 V 0.3 V, PVCC1 = 5.0 V 0.5 V/3.3 V 0.3 V, PVCC2 = 5.0 V 0.5 V, AVCC = 5.0 V 0.5 V, AVref = 4.5 V to AVCC, VSS = PLLVSS = AVSS = 0 V, Ta = -40C to 125C. When PVCC1 = 3.3 V 0.3 V, VCC = PVCC1. When writing or erasing on-chip flash memory, Ta = -40C to 85C. Item Output compare output delay time Input capture input setup time PULS output delay time Timer clock input setup time Timer clock pulse width (single edge specified) Timer clock pulse width (both edges specified) Symbol tTOCD tTICS tPLSD tTCKS tTCKWH/L tTCKWH/L Min -- 24* 24 + tcyc - 24* 24 + tcyc 3.0 5.0 Max 100 -- 100 -- -- -- Unit ns ns ns ns tcyc tcyc Figure 26.13 Figures Figure 26.12 [Operating precautions] * The timer input signals and timer clock input signals are asynchronous, but judged to have been changed at clock rise with two-state intervals shown in figures 26.12 and 26.13. If the setup times shown here are not provided, recognition is delayed until the clock rise two states after that timing. Rev.2.0, 07/03, page 890 of 960 T1 VOH CK tTOCD Timer output VOH VOH Tn VOH * tTICS Input capture input tPLSD PULS output Figure 26.12 ATU Input/Output timing and APC Output timing T1 VOH CK * Tn VOH tTCKS VOH * VOH tTCKS TCLKA, TCLKB tTCKWL tTCKWH Figure 26.13 ATU Clock Input Timing Rev.2.0, 07/03, page 891 of 960 26.3.6 I/O Port Timing Table 26.11 shows I/O port timing. Table 26.11 I/O Port Timing Conditions: VCC = PLLVCC = 3.3 V 0.3 V, PVCC1 = 5.0 V 0.5 V/3.3 V 0.3 V, PVCC2 = 5.0 V 0.5 V, AVCC = 5.0 V 0.5 V, AVref = 4.5 V to AVCC, VSS = PLLVSS = AVSS = 0 V, Ta = -40C to 125C. When PVCC1 = 3.3 V 0.3 V, VCC = PVCC1. When writing or erasing on-chip flash memory, Ta = -40C to 85C. Item Port output data delay time Port input hold time Port input setup time Symbol tPWD tPRH tPRS Min -- 24* 24+tcyc 24* 24+tcyc Max 100 -- -- Unit ns ns ns Figures Figure 26.14 [Operating precautions] The port input signals are asynchronous, but judged to have been changed at CK clock rise with two-state intervals shown in figure 26.14. If the setup times shown here are not provided, recognition is delayed until the clock rise two states after that timing. * The guaranteed operating range of power supply PVCC1 in MCU single-chip mode is only PVCC1 = 5.0 V 0.5 V. Do not use a voltage outside this range. CK tPRS Port (read) tPWD Port (write) tPRH Figure 26.14 I/O Port Input/Output timing Rev.2.0, 07/03, page 892 of 960 26.3.7 Watchdog Timer Timing Table 26.12 shows watchdog timer timing. Table 26.12 Watchdog Timer Timing Conditions: VCC = PLLVCC = 3.3 V 0.3 V, PVCC1 = 5.0 V 0.5 V/3.3 V 0.3 V, PVCC2 = 5.0 V 0.5 V, AVCC = 5.0 V 0.5 V, AVref = 4.5 V to AVCC, VSS = PLLVSS = AVSS = 0 V, Ta = -40C to 125C. When PVCC1 = 3.3 V 0.3 V, VCC = PVCC1. When writing or erasing on-chip flash memory, Ta = -40C to 85C. Item WDTOVF delay time Symbol tWOVD Min -- Max 100 Unit ns Figures Figure 26.15 CK VOH tWOVD VOH tWOVD Figure 26.15 Watchdog Timer Timing Rev.2.0, 07/03, page 893 of 960 26.3.8 Serial Communication Interface Timing Table 26.13 shows serial communication interface timing. Table 26.13 Serial Communication Interface Timing Conditions: VCC = PLLVCC = 3.3 V 0.3 V, PVCC1 = 5.0 V 0.5 V/3.3 V 0.3 V, PVCC2 = 5.0 V 0.5 V, AVCC = 5.0 V 0.5 V, AVref = 4.5 V to AVCC, VSS = PLLVSS = AVSS = 0 V, Ta = -40C to 125C. When PVCC1 = 3.3 V 0.3 V, VCC = PVCC1. When writing or erasing on-chip flash memory, Ta = -40C to 85C. Item Clock cycle Clock cycle (clock sync) Clock pulse width Input clock rise time Input clock fall time Transmit data delay time Transmit data setup time Transmit data hold time Symbol tscyc tscyc tsckw tsckr tsckf tTxD tRxS tRxH Min 8 12 0.4 -- -- -- 100 100 Max -- -- 0.6 3.0 3.0 100 -- -- Unit tcyc tcyc tscyc tcyc tcyc ns ns ns Figure 26.17 Figures Figure 26.16 [Operating precautions] The inputs and outputs are asynchronous in start-stop synchronous mode, but as shown in figure 26.17, the receive data are judged to have been changed at CK clock rise (two-clock intervals). The transmit signals change with a reference of CK clock rise (two-clock intervals). tsckr VIH VIL VIL tscyc VIH VIH VIL tsckf tsckw VIH SCK0-SCK4 Figure 26.16 SCI Input/Output Timing Rev.2.0, 07/03, page 894 of 960 tscyc SCK0-SCK4 (input/output) tTxD TxD0-TxD4 (transmit data) tRxS RxD0-RxD4 (receive data) SCI input/output timing (clock synchronous mode) tRxH T1 VOH CK tTxD TxD0-TxD4 (transmit data) tRxS RxD0-RxD4 (receive data) tRxH VOH Tn SCI input/output timing (start-stop synchronous mode) Figure 26.17 SCI Input/Output Timing Rev.2.0, 07/03, page 895 of 960 26.3.9 HCAN Timing Table 26.14 shows HCAN timing. Table 26.14 HCAN Timing Conditions: VCC = PLLVCC = 3.3 V 0.3 V, PVCC1 = 5.0 V 0.5 V/3.3 V 0.3 V, PVCC2 = 5.0 V 0.5 V, AVCC = 5.0 V 0.5 V, AVref = 4.5 V to AVCC, VSS = PLLVSS = AVSS = 0 V, Ta = -40C to 125C. When PVCC1 = 3.3 V 0.3 V, VCC = PVCC1. When writing or erasing on-chip flash memory, Ta = -40C to 85C. Item Transmit data delay time Transmit data setup time Transmit data hold time Symbol tHTxD tHRxS tHRxH Min -- 100 100 Max 100 -- -- Unit ns ns ns Figures Figure 26.18 [Operating precautions] The HCAN input signals are asynchronous, but judged to have been changed at CK clock rise (two-clock intervals) shown in figure 26.18. The HCAN output signals are asynchronous, but they change with a reference of CK clock rise (two-clock intervals) shown in figure 26.18. VOH CK tHTxD HTxD0, HTxD1 (transmit data) tHRxS HRxD0, HRxD1 (receive data) tHRxH VOH Figure 26.18 HCAN Input/Output timing Rev.2.0, 07/03, page 896 of 960 26.3.10 A/D Converter Timing Table 26.15 shows A/D converter timing. Table 26.15 A/D Converter Timing Conditions: VCC = PLLVCC = 3.3 V 0.3 V, PVCC1 = 5.0 V 0.5 V/3.3 V 0.3 V, PVCC2 = 5.0 V 0.5 V, AVCC = 5.0 V 0.5 V, AVref = 4.5 V to AVCC, VSS = PLLVSS = AVSS = 0 V, Ta = -40C to 125C. When PVCC1 = 3.3 V 0.3 V, VCC = PVCC1. When writing or erasing on-chip flash memory, Ta = -40C to 85C. CSK = 0: fop = 20-40 MHz Item External trigger input start delay time A/D conversion time A/D conversion start delay time Input sampling time ADEND output delay time Symbol tTRGS tCONV tD tSPL tADENDD Min 50 518 20 -- -- Typ -- -- -- 128 -- Max -- 532 34 -- 100 CSK = 1: fop = 20 MHz Min 50 262 12 -- -- Typ -- -- -- 64 -- 100 Max -- 268 18 Unit ns tcyc tcyc tcyc ns Figure Figure 26.19 Figure 26.20 4-6 states VOH CK input tTRGS ADCR (ADST = 1 set) Figure 26.19 External Trigger Input Timing Rev.2.0, 07/03, page 897 of 960 tCONV tD Write cycle A/D synchronization time (6 states) (up to 28 states) CK tSPL Address Analog input sampling signal ADF VOH CK VOH tADENDD tADENDD ADEND Figure 26.20 Analog Conversion Timing Rev.2.0, 07/03, page 898 of 960 26.3.11 H-UDI Timing Table 26.16 shows H-UDI timing. Table 26.16 H-UDI Timing Conditions: VCC = PLLVCC = 3.3 V 0.3 V, PVCC1 = 5.0 V 0.5 V/3.3 V 0.3 V, PVCC2 = 5.0 V 0.5 V, AVCC = 5.0 V 0.5 V, AVref = 4.5 V to AVCC, VSS = PLLVSS = AVSS = 0 V, Ta = -40C to 125C. When PVCC1 = 3.3 V 0.3 V, VCC = PVCC1. When writing or erasing on-chip flash memory, Ta = -40C to 85C. Item TCK clock cycle TCK clock high-level width TCK clock low-level width TRST pulse width TRST setup time TMS setup time TMS hold time TDI setup time TDI hold time TDO delay time Symbol ttcyc tTCKH tTCKL tTRSW tTRSS tTMSS tTMSH tTDIS tTDIH tTDOD Min 4 0.4 0.4 20 30 30 10 30 10 -- Max -- 0.6 0.6 -- -- -- -- -- -- 30 Unit ttcyc ttcyc ttcyc tcyc ns ns ns ns ns ns Figure 26.23 Figure 26.22 Figures Figure 26.21 [Operating precautions] The H-UDI pins constitute a circuit requiring the voltage of VCC = 3.3 V 0.3 V. Comply with the input and output voltages specified in the DC characteristics, for operation. tTCKH VIH TCK VIL ttcyc VIL VIH tTCKL VIH Table 26.21 H-UDI Clock Timing Rev.2.0, 07/03, page 899 of 960 TCK tTRSS VIL tTRSS VIL VIL tTRSW VIL Table 26.22 H-UDI TRST Timing VIH TCK VIL tTMSS TMS tTDIS TDI tTDOD TDO tTDOD tTDIH tTMSH VIH Table 26.23 H-UDI Input/Output Timing Rev.2.0, 07/03, page 900 of 960 26.3.12 AUD Timing Table 26.17 shows AUD timing. Table 26.17 AUD Timing Conditions: VCC = PLLVCC = 3.3 V 0.3 V, PVCC1 = 5.0 V 0.5 V/3.3 V 0.3 V, PVCC2 = 5.0 V 0.5 V, AVCC = 5.0 V 0.5 V, AVref = 4.5 V to AVCC, VSS = PLLVSS = AVSS = 0 V, Ta = -40C to 125C. When PVCC1 = 3.3 V 0.3 V, VCC = PVCC1. When writing or erasing on-chip flash memory, Ta = -40C to 85C. Item AUDRST pulse width (Branch trace) AUDRST pulse width (RAM monitor) AUDMD setup time (Branch trace) AUDMD setup time (RAM monitor) Branch trace clock cycle Branch trace clock duty Branch trace data delay time Branch trace data hold time Branch trace SYNC delay time Branch trace SYNC hold time RAM monitor clock cycle RAM monitor clock low pulse width RAM monitor output data delay time RAM monitor output data hold time RAM monitor input data setup time RAM monitor input data hold time RAM monitor SYNC setup time RAM monitor SYNC hold time Symbol tAUDRSTW tAUDRSTW tAUDMDS tAUDMDS tBTCYC tBTCKW tBTDD tBTDH tBTSD tBTSH tRMCYC tRMCKW tRMDD tRMDHD tRMDS tRMDH tRMSS tRMSH Min 20 5 20 5 2 40 -- 0 -- 0 100 45 7 5 20 5 20 5 Max -- -- -- -- 2 60 40 -- 40 -- -- -- tRMCYC - 20 -- -- -- -- -- Unit tcyc tRMCYC tcyc tRMCYC tcyc % ns ns ns ns ns ns ns ns ns ns ns ns Figure 26.26 Figure 26.25 Figures Figure 26.24 Load conditions: AUDCK (branch trace): CL = 30 pF: otherwise CL = 100 pF AUDSYNC: CL = 100 pF AUDATA3 to AUDATA0: CL = 100 pF Rev.2.0, 07/03, page 901 of 960 tcyc CK (Branch trace) tRMCYC AUDCK (input) (RAM monitor) tAUDRSTW tAUDMDS AUDMD Figure 26.24 AUD Reset Timing tBTCKW AUDCK (output) tBTDD AUDATA3 to AUDATA0 (output) tBTDH tBTCYC tBTSD tBTSH (output) Figure 26.25 Branch Trace Timing Rev.2.0, 07/03, page 902 of 960 tRMCYC AUDCK (input) tRMDD AUDATA3 to AUDATA0 (output) AUDATA3 to AUDATA0 (input) tRMSS (input) tRMDHD tRMCKW tRMDS tRMDH tRMSH Figure 26.26 RAM Monitor Timing 26.3.13 UBC Trigger Timing Table 26.18 shows UBC trigger timing. Table 26.18 UBC Trigger Timing Conditions: VCC = PLLVCC = 3.3 V 0.3 V, PVCC1 = 5.0 V 0.5 V/3.3 V 0.3 V, PVCC2 = 5.0 V 0.5 V, AVCC = 5.0 V 0.5 V, AVref = 4.5 V to AVCC, VSS = PLLVSS = AVSS = 0 V, Ta = -40C to 125C. When PVCC1 = 3.3 V 0.3 V, VCC = PVCC1. When writing or erasing on-chip flash memory, Ta = -40C to 85C. Item UBCTRG delay time Symbol tUBCTGD Min -- Max 35 Unit ns Figures Figure 26.27 VOH CK tUBCTGD Figure 26.27 UBC Trigger Timing Rev.2.0, 07/03, page 903 of 960 26.3.14 Measuring Conditions for AC Characteristics Input reference levels Output reference level High level: VIH min. value, low level: VIL max. value High level: 2.0 V, Low level: 0.8 V IOL LSI output pin DUT output CL V VREF IOH CL is a total value that includes the measuring instrument capacitance. The following CL values are used: 30 pF: 50 pF: 100 pF: 30 pF: - , , , , AUDCK CK, A21-A0, D15-D0, , , , TDO AUDATA3-0, AUDSYNC All port pins other than the above, and peripheral module output pins. IOL and IOH are the condition for the IOL = 1.6 mA, IOH = 200 A. Figure 26.28 Output Test Circuit Rev.2.0, 07/03, page 904 of 960 26.4 A/D Converter Characteristics Table 26.19 shows A/D converter characteristics. Table 26.19 A/D Converter Characteristics Conditions: VCC = PLLVCC = 3.3 V 0.3 V, PVCC1 = 5.0 V 0.5 V/3.3 V 0.3 V, PVCC2 = 5.0 V 0.5 V, AVCC = 5.0 V 0.5 V, AVref = 4.5 V to AVCC, VSS = PLLVSS = AVSS = 0 V, Ta = -40C to 125C. When PVCC1 = 3.3 V 0.3 V, VCC = PVCC1. When writing or erasing on-chip flash memory, Ta = -40C to 85C. CSK = 0: fop = 10-20 MHz Item Resolution A/D conversion time Analog input capacitance Permitted analog signal source impedance Non-linear error Min 10 -- -- -- -- Typ 10 -- -- -- -- Max 10 13.3 20 3 1.5* 2.5* Offset error -- -- 1.5* 2.5* Full-scale error -- -- 1.5* 2.5* Quantization error Absolute error -- -- -- -- 0.5 2.0* 2.5* Note: *1 Ta105C *2 Ta>105C 1 1 CSK = 1: fop = 10 MHz Min 10 -- -- -- -- Typ 10 -- -- -- -- Max 10 13.4 20 3 1.5* 2.5* -- -- 1.5* 2.5* -- -- 1.5* 2.5* -- -- -- -- 0.5 2.0* 2.5* 1 1 Unit bit s pF k LSB 2 1 2 1 2 1 2 1 LSB LSB 2 2 LSB LSB 2 2 Rev.2.0, 07/03, page 905 of 960 26.5 Flash Memory Characteristics Table 26.20 shows the flash memory characteristics. Table 26.20 Flash Memory Characteristics Conditions: VCC = PLLVCC = 3.3 V 0.3 V, PVCC1 = 5.0 V 0.5 V/3.3 V 0.3 V, PVCC2 = 5.0 V 0.5 V, AVCC = 5.0 V 0.5 V, AVref = 4.5 V to AVCC, VSS = PLLVSS = AVSS = 0 V, Ta = -40C to 105C. When PVCC1 = 3.3 V 0.3 V, VCC = PVCC1. When writing or erasing on-chip flash memory, Ta = -40C to 85C. Item Programming time* * Erase time* * Note: 13 12 Symbol tP tE NWEC Min -- -- -- Typ 20 1 -- Max 200 10 100 Unit ms/128 bytes s/block Times Reprogramming count *1 Use the on-chip programming/erasing routine for programming/erasure. *2 When all 0 are programmed. *3 64 kbytes of block Rev.2.0, 07/03, page 906 of 960 26.6 26.6.1 Usage Note Notes on Connecting External Capacitor for Current Stabilization The SH7055SF includes an internal step-down curcuit to automatically reduce the microporocessor power supply voltage to an appropriate level. Between this internal steppeddown power supply (VCL pin) and the VSS pin, an capacitor (0.33 to 0.47 F) for stabilizing the internal voltage. Connection of the external capacitor is shown in figure 26.29. The external capacitor should be located near the pin. Do not apply any power supply voltage to the VCL pin. External power-supply stabilizing capacitor One 0.33 to 0.47 F capacitor VCL One 0.33 to 0.47 F capacitor VSS VCL VSS VCL One 0.33 to 0.47 F capacitor VSS Do not apply any power supply voltage to the VCL pin. Use multilayer ceramics capacitors (one 0.33 to 0.47 F capacitor for each VCL pin), which should be located near the pin. Figure 26.29 Connection of VCL Capacitor 26.6.2 Notes on Mode Pin Input When power is supplied and in hardware standby mode, mode setup time is determined by tMDS1. When power-on reset is performed only by the RES pin, mode setup time is differs according to the combination of input to the FWE and MD2 to MD0. When low is input to the RES pin with the pins FWE and MD2 to MD0 operated in mode specified in table 26.3, the mode setup time is determined by tMDS2. When combination which is not specified in table 26.3 is input, the mode setup time is determined by tMDS1. Rev.2.0, 07/03, page 907 of 960 Table 26.21 Mode Pin Input Timing Item Mode setup time 1 Mode setup time 2 Symbol tMDS1 tMDS2 Min 30 10 Typ Max Unit ms tcyc Remark Figure 26.30 Figure 26.30 Mode Pin Input Timing Rev.2.0, 07/03, page 908 of 960 Appendix A On-chip peripheral module Registers A.1 Address On-chip peripheral module register addresses and bit names are shown in the following table. 16-bit and 32-bit registers are shown in two and four rows of 8 bits, respectively. Table A.1 Address Register Abbr. Bit Names Bit 7 MCR7 -- BCR7 BCR15 MBCR7 Bit 6 -- -- BCR6 BCR14 MBCR6 Bit 5 MCR5 -- BCR5 BCR13 MBCR5 Bit 4 -- -- BCR4 BCR12 MBCR4 Bit 3 -- GSR3 BCR3 BCR11 MBCR3 Bit 2 MCR2 GSR2 BCR2 BCR10 MBCR2 Bit 1 MCR1 GSR1 BCR1 BCR9 MBCR1 Bit 0 MCR0 GSR0 BCR0 BCR8 -- MBCR8 -- TXPR8 -- TXCR8 -- TXACK8 -- ABACK8 RXPR0 RXPR8 RFPR0 RFPR8 IRR0 IRR8 MBIMR0 MBIMR8 -- IMR8 Module HCAN (channel 0) Address H'FFFFE400 MCR H'FFFFE401 GSR H'FFFFE402 BCR H'FFFFE403 H'FFFFE404 MBCR H'FFFFE405 H'FFFFE406 TXPR H'FFFFE407 H'FFFFE408 TXCR H'FFFFE409 H'FFFFE40A TXACK H'FFFFE40B H'FFFFE40C ABACK H'FFFFE40D H'FFFFE40E RXPR H'FFFFE40F H'FFFFE410 RFPR H'FFFFE411 H'FFFFE412 IRR H'FFFFE413 H'FFFFE414 MBIMR H'FFFFE415 H'FFFFE416 IMR H'FFFFE417 H'FFFFE418 REC H'FFFFE419 TEC H'FFFFE41A UMSR H'FFFFE41B MBCR15 MBCR14 MBCR13 MBCR12 MBCR11 MBCR10 MBCR9 TXPR7 TXPR15 TXCR7 TXCR15 TXACK7 TXPR6 TXPR14 TXCR6 TXCR14 TXACK6 TXPR5 TXPR13 TXCR5 TCR13 TXACK5 TXPR4 TXPR12 TXCR4 TXCR12 TXACK4 TXPR3 TXPR11 TXCR3 TXCR11 TXACK3 TXPR2 TXPR10 TXCR2 TSCR10 TXACK2 TXPR1 TXPR9 TXCR1 TXCR9 TXACK1 TXACK15 TXACK14 TXACK13 TXACK12 TXACK11 TXACK10 TXACK9 ABACK7 ABACK6 ABACK5 ABACK4 ABACK3 ABACK2 ABACK1 ABACK15 ABACK14 ABACK13 ABACK12 ABACK11 ABACK10 ABACK9 RXPR7 RXPR15 RFPR7 RFPR15 IRR7 -- MBIMR7 RXPR6 RXPR14 RFPR6 RFPR14 IRR6 -- MBIMR6 RXPR5 RXPR13 RFPR5 RFPR13 IRR5 -- MBIMR5 RXPR4 RXPR12 RFPR4 RFPR12 IRR4 IRR12 MBIMR4 RXPR3 RXPR11 RFPR3 RFPR11 IRR3 -- MBIMR3 RXPR2 RXPR10 RFPR2 RFPR10 IRR2 -- MBIMR2 RXPR1 RXPR9 RFPR1 RFPR9 IRR1 IRR9 MBIMR1 MBIMR15 MBIMR14 MBIMR13 MBIMR12 MBIMR11 MBIMR10 MBIMR9 IMR7 -- IMR6 -- IMR5 -- IMR4 IMR12 IMR3 -- IMR2 -- IMR1 IMR9 UMSR7 UMSR6 UMSR5 UMSR4 UMSR3 UMSR2 UMSR1 UMSR0 UMSR8 UMSR15 UMSR14 UMSR13 UMSR12 UMSR11 UMSR10 UMSR9 Rev.2.0, 07/03, page 909 of 960 Table A.1 Address (cont) Register Abbr. Bit Names Bit 7 LAFML7 Bit 6 LAFML6 Bit 5 LAFML5 Bit 4 LAFML4 Bit 3 LAFML3 Bit 2 LAFML2 Bit 1 LAFML1 Bit 0 LAFML0 LAFML8 LAFMH0 LAFMH8 DLC0 Module HCAN (channel 0) Address H'FFFFE41C LAFML H'FFFFE41D H'FFFFE41E LAFMH H'FFFFE41F H'FFFFE420 MC0[1] H'FFFFE421 MC0[2] H'FFFFE422 MC0[3] H'FFFFE423 MC0[4] H'FFFFE424 MC0[5] H'FFFFE425 MC0[6] H'FFFFE426 MC0[7] H'FFFFE427 MC0[8] H'FFFFE428 MC1[1] H'FFFFE429 MC1[2] H'FFFFE42A MC1[3] H'FFFFE42B MC1[4] H'FFFFE42C MC1[5] H'FFFFE42D MC1[6] H'FFFFE42E MC1[7] H'FFFFE42F MC1[8] H'FFFFE430 MC2[1] H'FFFFE431 MC2[2] H'FFFFE432 MC2[3] H'FFFFE433 MC2[4] H'FFFFE434 MC2[5] H'FFFFE435 MC2[6] H'FFFFE436 MC2[7] H'FFFFE437 MC2[8] H'FFFFE438 MC3[1] H'FFFFE439 MC3[2] H'FFFFE43A MC3[3] H'FFFFE43B MC3[4] H'FFFFE43C MC3[5] H'FFFFE43D MC3[6] H'FFFFE43E MC3[7] H'FFFFE43F MC3[8] LAFML15 LAFML14 LAFML13 LAFML12 LAFML11 LAFML10 LAFML9 LAFMH7 LAFMH6 LAFMH5 -- -- -- LAFMH1 LAFMH15 LAFMH14 LAFMH13 LAFMH12 LAFMH11 LAFMH10 LAFMH9 DLC3 DLC2 DLC1 STD_ID2 STD_ID1 STD_ID0 RTR IDE EXD_ID17 EXD_ID16 STD_ID10 STD_ID9 STD_ID8 STD_ID7 STD_ID6 STD_ID5 STD_ID4 STD_ID3 EXD_ID7 EXD_ID6 EXD_ID5 EXD_ID4 EXD_ID3 EXD_ID2 EXD_ID1 EXD_ID0 EXD_ID15 EXD_ID14 EXD_ID13 EXD_ID12 EXD_ID11 EXD_ID10 EXD_ID9 EXD_ID8 DLC3 DLC2 DLC1 DLC0 STD_ID2 STD_ID1 STD_ID0 RTR IDE EXD_ID17 EXD_ID16 STD_ID10 STD_ID9 STD_ID8 STD_ID7 STD_ID6 STD_ID5 STD_ID4 STD_ID3 EXD_ID7 EXD_ID6 EXD_ID5 EXD_ID4 EXD_ID3 EXD_ID2 EXD_ID1 EXD_ID0 EXD_ID15 EXD_ID14 EXD_ID13 EXD_ID12 EXD_ID11 EXD_ID10 EXD_ID9 EXD_ID8 DLC3 DLC2 DLC1 DLC0 STD_ID2 STD_ID1 STD_ID0 RTR IDE EXD_ID17 EXD_ID16 STD_ID10 STD_ID9 STD_ID8 STD_ID7 STD_ID6 STD_ID5 STD_ID4 STD_ID3 EXD_ID7 EXD_ID6 EXD_ID5 EXD_ID4 EXD_ID3 EXD_ID2 EXD_ID1 EXD_ID0 EXD_ID15 EXD_ID14 EXD_ID13 EXD_ID12 EXD_ID11 EXD_ID10 EXD_ID9 EXD_ID8 DLC3 DLC2 DLC1 DLC0 STD_ID2 STD_ID1 STD_ID0 RTR IDE EXD_ID17 EXD_ID16 STD_ID10 STD_ID9 STD_ID8 STD_ID7 STD_ID6 STD_ID5 STD_ID4 STD_ID3 EXD_ID7 EXD_ID6 EXD_ID5 EXD_ID4 EXD_ID3 EXD_ID2 EXD_ID1 EXD_ID0 EXD_ID15 EXD_ID14 EXD_ID13 EXD_ID12 EXD_ID11 EXD_ID10 EXD_ID9 EXD_ID8 Rev.2.0, 07/03, page 910 of 960 Table A.1 Address (cont) Register Abbr. Bit Names Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 DLC3 Bit 2 DLC2 Bit 1 DLC1 Bit 0 DLC0 Module HCAN (channel 0) Address H'FFFFE440 MC4[1] H'FFFFE441 MC4[2] H'FFFFE442 MC4[3] H'FFFFE443 MC4[4] H'FFFFE444 MC4[5] H'FFFFE445 MC4[6] H'FFFFE446 MC4[7] H'FFFFE447 MC4[8] H'FFFFE448 MC5[1] H'FFFFE449 MC5[2] H'FFFFE44A MC5[3] H'FFFFE44B MC5[4] H'FFFFE44C MC5[5] H'FFFFE44D MC5[6] H'FFFFE44E MC5[7] H'FFFFE44F MC5[8] H'FFFFE450 MC6[1] H'FFFFE451 MC6[2] H'FFFFE452 MC6[3] H'FFFFE453 MC6[4] H'FFFFE454 MC6[5] H'FFFFE455 MC6[6] H'FFFFE456 MC6[7] H'FFFFE457 MC6[8] H'FFFFE458 MC7[1] H'FFFFE459 MC7[2] H'FFFFE45A MC7[3] H'FFFFE45B MC7[4] H'FFFFE45C MC7[5] H'FFFFE45D MC7[6] H'FFFFE45E MC7[7] H'FFFFE45F MC7[8] H'FFFFE460 MC8[1] H'FFFFE461 MC8[2] H'FFFFE462 MC8[3] H'FFFFE463 MC8[4] STD_ID2 STD_ID1 STD_ID0 RTR STD_ID2 STD_ID1 STD_ID0 RTR STD_ID2 STD_ID1 STD_ID0 RTR STD_ID2 STD_ID1 STD_ID0 RTR IDE EXD_ID17 EXD_ID16 STD_ID10 STD_ID9 STD_ID8 STD_ID7 STD_ID6 STD_ID5 STD_ID4 STD_ID3 EXD_ID7 EXD_ID6 EXD_ID5 EXD_ID4 EXD_ID3 EXD_ID2 EXD_ID1 EXD_ID0 EXD_ID15 EXD_ID14 EXD_ID13 EXD_ID12 EXD_ID11 EXD_ID10 EXD_ID9 EXD_ID8 DLC3 DLC2 DLC1 DLC0 IDE EXD_ID17 EXD_ID16 STD_ID10 STD_ID9 STD_ID8 STD_ID7 STD_ID6 STD_ID5 STD_ID4 STD_ID3 EXD_ID7 EXD_ID6 EXD_ID5 EXD_ID4 EXD_ID3 EXD_ID2 EXD_ID1 EXD_ID0 EXD_ID15 EXD_ID14 EXD_ID13 EXD_ID12 EXD_ID11 EXD_ID10 EXD_ID9 EXD_ID8 DLC3 DLC2 DLC1 DLC0 IDE EXD_ID17 EXD_ID16 STD_ID10 STD_ID9 STD_ID8 STD_ID7 STD_ID6 STD_ID5 STD_ID4 STD_ID3 EXD_ID7 EXD_ID6 EXD_ID5 EXD_ID4 EXD_ID3 EXD_ID2 EXD_ID1 EXD_ID0 EXD_ID15 EXD_ID14 EXD_ID13 EXD_ID12 EXD_ID11 EXD_ID10 EXD_ID9 EXD_ID8 DLC3 DLC2 DLC1 DLC0 IDE EXD_ID17 EXD_ID16 STD_ID10 STD_ID9 STD_ID8 STD_ID7 STD_ID6 STD_ID5 STD_ID4 STD_ID3 EXD_ID7 EXD_ID6 EXD_ID5 EXD_ID4 EXD_ID3 EXD_ID2 EXD_ID1 EXD_ID0 EXD_ID15 EXD_ID14 EXD_ID13 EXD_ID12 EXD_ID11 EXD_ID10 EXD_ID9 EXD_ID8 DLC3 DLC2 DLC1 DLC0 Rev.2.0, 07/03, page 911 of 960 Table A.1 Address (cont) Register Abbr. Bit Names Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 IDE Bit 2 Bit 1 Bit 0 Module Address H'FFFFE464 MC8[5] H'FFFFE465 MC8[6] H'FFFFE466 MC8[7] H'FFFFE467 MC8[8] H'FFFFE468 MC9[1] H'FFFFE469 MC9[2] H'FFFFE46A MC9[3] H'FFFFE46B MC9[4] H'FFFFE46C MC9[5] H'FFFFE46D MC9[6] H'FFFFE46E MC9[7] H'FFFFE46F MC9[8] H'FFFFE470 MC10[1] H'FFFFE471 MC10[2] H'FFFFE472 MC10[3] H'FFFFE473 MC10[4] H'FFFFE474 MC10[5] H'FFFFE475 MC10[6] H'FFFFE476 MC10[7] H'FFFFE477 MC10[8] H'FFFFE478 MC11[1] H'FFFFE479 MC11[2] H'FFFFE47A MC11[3] H'FFFFE47B MC11[4] H'FFFFE47C MC11[5] H'FFFFE47D MC11[6] H'FFFFE47E MC11[7] H'FFFFE47F MC11[8] H'FFFFE480 MC12[1] H'FFFFE481 MC12[2] H'FFFFE482 MC12[3] H'FFFFE483 MC12[4] H'FFFFE484 MC12[5] H'FFFFE485 MC12[6] H'FFFFE486 MC12[7] H'FFFFE487 MC12[8] STD_ID2 STD_ID1 STD_ID0 RTR STD_ID10 STD_ID9 STD_ID8 STD_ID7 STD_ID6 STD_ID5 STD_ID4 STD_ID3 EXD_ID17 EXD_ID16 HCAN (channel 0) EXD_ID7 EXD_ID6 EXD_ID5 EXD_ID4 EXD_ID3 EXD_ID2 EXD_ID1 EXD_ID0 EXD_ID15 EXD_ID14 EXD_ID13 EXD_ID12 EXD_ID11 EXD_ID10 EXD_ID9 EXD_ID8 DLC3 DLC2 DLC1 DLC0 STD_ID2 STD_ID1 STD_ID0 RTR IDE EXD_ID17 EXD_ID16 STD_ID10 STD_ID9 STD_ID8 STD_ID7 STD_ID6 STD_ID5 STD_ID4 STD_ID3 EXD_ID7 EXD_ID6 EXD_ID5 EXD_ID4 EXD_ID3 EXD_ID2 EXD_ID1 EXD_ID0 EXD_ID15 EXD_ID14 EXD_ID13 EXD_ID12 EXD_ID11 EXD_ID10 EXD_ID9 EXD_ID8 DLC3 DLC2 DLC1 DLC0 STD_ID2 STD_ID1 STD_ID0 RTR IDE EXD_ID17 EXD_ID16 STD_ID10 STD_ID9 STD_ID8 STD_ID7 STD_ID6 STD_ID5 STD_ID4 STD_ID3 EXD_ID7 EXD_ID6 EXD_ID5 EXD_ID4 EXD_ID3 EXD_ID2 EXD_ID1 EXD_ID0 EXD_ID15 EXD_ID14 EXD_ID13 EXD_ID12 EXD_ID11 EXD_ID10 EXD_ID9 EXD_ID8 DLC3 DLC2 DLC1 DLC0 STD_ID2 STD_ID1 STD_ID0 RTR IDE EXD_ID17 EXD_ID16 STD_ID10 STD_ID9 STD_ID8 STD_ID7 STD_ID6 STD_ID5 STD_ID4 STD_ID3 EXD_ID7 EXD_ID6 EXD_ID5 EXD_ID4 EXD_ID3 EXD_ID2 EXD_ID1 EXD_ID0 EXD_ID15 EXD_ID14 EXD_ID13 EXD_ID12 EXD_ID11 EXD_ID10 EXD_ID9 EXD_ID8 DLC3 DLC2 DLC1 DLC0 STD_ID2 STD_ID1 STD_ID0 RTR IDE EXD_ID17 EXD_ID16 STD_ID10 STD_ID9 STD_ID8 STD_ID7 STD_ID6 STD_ID5 STD_ID4 STD_ID3 EXD_ID7 EXD_ID6 EXD_ID5 EXD_ID4 EXD_ID3 EXD_ID2 EXD_ID1 EXD_ID0 EXD_ID15 EXD_ID14 EXD_ID13 EXD_ID12 EXD_ID11 EXD_ID10 EXD_ID9 EXD_ID8 Rev.2.0, 07/03, page 912 of 960 Table A.1 Address (cont) Register Abbr. Bit Names Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 DLC3 Bit 2 DLC2 Bit 1 DLC1 Bit 0 DLC0 Module HCAN (channel 0) Address H'FFFFE488 MC13[1] H'FFFFE489 MC13[2] H'FFFFE48A MC13[3] H'FFFFE48B MC13[4] H'FFFFE48C MC13[5] H'FFFFE48D MC13[6] H'FFFFE48E MC13[7] H'FFFFE48F MC13[8] H'FFFFE490 MC14[1] H'FFFFE491 MC14[2] H'FFFFE492 MC14[3] H'FFFFE493 MC14[4] H'FFFFE494 MC14[5] H'FFFFE495 MC14[6] H'FFFFE496 MC14[7] H'FFFFE497 MC14[8] H'FFFFE498 MC15[1] H'FFFFE499 MC15[2] H'FFFFE49A MC15[3] H'FFFFE49B MC15[4] H'FFFFE49C MC15[5] H'FFFFE49D MC15[6] H'FFFFE49E MC15[7] H'FFFFE49F MC15[8] H'FFFFE4A0 -- to H'FFFFE4AF H'FFFFE4B0 MD0[1] H'FFFFE4B1 MD0[2] H'FFFFE4B2 MD0[3] H'FFFFE4B3 MD0[4] H'FFFFE4B4 MD0[5] H'FFFFE4B5 MD0[6] H'FFFFE4B6 MD0[7] H'FFFFE4B7 MD0[8] STD_ID2 STD_ID1 STD_ID0 RTR STD_ID2 STD_ID1 STD_ID0 RTR STD_ID2 STD_ID1 STD_ID0 RTR IDE EXD_ID17 EXD_ID16 STD_ID10 STD_ID9 STD_ID8 STD_ID7 STD_ID6 STD_ID5 STD_ID4 STD_ID3 EXD_ID7 EXD_ID6 EXD_ID5 EXD_ID4 EXD_ID3 EXD_ID2 EXD_ID1 EXD_ID0 EXD_ID15 EXD_ID14 EXD_ID13 EXD_ID12 EXD_ID11 EXD_ID10 EXD_ID9 EXD_ID8 DLC3 DLC2 DLC1 DLC0 IDE EXD_ID17 EXD_ID16 STD_ID10 STD_ID9 STD_ID8 STD_ID7 STD_ID6 STD_ID5 STD_ID4 STD_ID3 EXD_ID7 EXD_ID6 EXD_ID5 EXD_ID4 EXD_ID3 EXD_ID2 EXD_ID1 EXD_ID0 EXD_ID15 EXD_ID14 EXD_ID13 EXD_ID12 EXD_ID11 EXD_ID10 EXD_ID9 EXD_ID8 DLC3 DLC2 DLC1 DLC0 IDE EXD_ID17 EXD_ID16 STD_ID10 STD_ID9 STD_ID8 STD_ID7 STD_ID6 STD_ID5 STD_ID4 STD_ID3 EXD_ID7 EXD_ID6 EXD_ID5 EXD_ID4 EXD_ID3 EXD_ID2 EXD_ID1 EXD_ID0 EXD_ID15 EXD_ID14 EXD_ID13 EXD_ID12 EXD_ID11 EXD_ID10 EXD_ID9 EXD_ID8 -- -- -- -- -- -- -- -- MSG_DATA_1 MSG_DATA_2 MSG_DATA_3 MSG_DATA_4 MSG_DATA_5 MSG_DATA_6 MSG_DATA_7 MSG_DATA_8 Rev.2.0, 07/03, page 913 of 960 Table A.1 Address (cont) Register Abbr. Bit Names Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Module HCAN (channel 0) Address H'FFFFE4B8 MD1[1] H'FFFFE4B9 MD1[2] H'FFFFE4BA MD1[3] H'FFFFE4BB MD1[4] H'FFFFE4BC MD1[5] H'FFFFE4BD MD1[6] H'FFFFE4BE MD1[7] H'FFFFE4BF MD1[8] H'FFFFE4C0 MD2[1] H'FFFFE4C1 MD2[2] H'FFFFE4C2 MD2[3] H'FFFFE4C3 MD2[4] H'FFFFE4C4 MD2[5] H'FFFFE4C5 MD2[6] H'FFFFE4C6 MD2[7] H'FFFFE4C7 MD2[8] H'FFFFE4C8 MD3[1] H'FFFFE4C9 MD3[2] H'FFFFE4CA MD3[3] H'FFFFE4CB MD3[4] H'FFFFE4CC MD3[5] H'FFFFE4CD MD3[6] H'FFFFE4CE MD3[7] H'FFFFE4CF MD3[8] H'FFFFE4D0 MD4[1] H'FFFFE4D1 MD4[2] H'FFFFE4D2 MD4[3] H'FFFFE4D3 MD4[4] H'FFFFE4D4 MD4[5] H'FFFFE4D5 MD4[6] H'FFFFE4D6 MD4[7] H'FFFFE4D7 MD4[8] H'FFFFE4D8 MD5[1] H'FFFFE4D9 MD5[2] H'FFFFE4DA MD5[3] MSG_DATA_1 MSG_DATA_2 MSG_DATA_3 MSG_DATA_4 MSG_DATA_5 MSG_DATA_6 MSG_DATA_7 MSG_DATA_8 MSG_DATA_1 MSG_DATA_2 MSG_DATA_3 MSG_DATA_4 MSG_DATA_5 MSG_DATA_6 MSG_DATA_7 MSG_DATA_8 MSG_DATA_1 MSG_DATA_2 MSG_DATA_3 MSG_DATA_4 MSG_DATA_5 MSG_DATA_6 MSG_DATA_7 MSG_DATA_8 MSG_DATA_1 MSG_DATA_2 MSG_DATA_3 MSG_DATA_4 MSG_DATA_5 MSG_DATA_6 MSG_DATA_7 MSG_DATA_8 MSG_DATA_1 MSG_DATA_2 MSG_DATA_3 Rev.2.0, 07/03, page 914 of 960 Table A.1 Address (cont) Register Abbr. Bit Names Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Module HCAN (channel 0) Address H'FFFFE4DB MD5[4] H'FFFFE4DC MD5[5] H'FFFFE4DD MD5[6] H'FFFFE4DE MD5[7] H'FFFFE4DF MD5[8] H'FFFFE4E0 MD6[1] H'FFFFE4E1 MD6[2] H'FFFFE4E2 MD6[3] H'FFFFE4E3 MD6[4] H'FFFFE4E4 MD6[5] H'FFFFE4E5 MD6[6] H'FFFFE4E6 MD6[7] H'FFFFE4E7 MD6[8] H'FFFFE4E8 MD7[1] H'FFFFE4E9 MD7[2] H'FFFFE4EA MD7[3] H'FFFFE4EB MD7[4] H'FFFFE4EC MD7[5] H'FFFFE4ED MD7[6] H'FFFFE4EE MD7[7] H'FFFFE4EF MD7[8] H'FFFFE4F0 MD8[1] H'FFFFE4F1 MD8[2] H'FFFFE4F2 MD8[3] H'FFFFE4F3 MD8[4] H'FFFFE4F4 MD8[5] H'FFFFE4F5 MD8[6] H'FFFFE4F6 MD8[7] H'FFFFE4F7 MD8[8] H'FFFFE4F8 MD9[1] H'FFFFE4F9 MD9[2] H'FFFFE4FA MD9[3] H'FFFFE4FB MD9[4] H'FFFFE4FC MD9[5] H'FFFFE4FD MD9[6] MSG_DATA_4 MSG_DATA_5 MSG_DATA_6 MSG_DATA_7 MSG_DATA_8 MSG_DATA_1 MSG_DATA_2 MSG_DATA_3 MSG_DATA_4 MSG_DATA_5 MSG_DATA_6 MSG_DATA_7 MSG_DATA_8 MSG_DATA_1 MSG_DATA_2 MSG_DATA_3 MSG_DATA_4 MSG_DATA_5 MSG_DATA_6 MSG_DATA_7 MSG_DATA_8 MSG_DATA_1 MSG_DATA_2 MSG_DATA_3 MSG_DATA_4 MSG_DATA_5 MSG_DATA_6 MSG_DATA_7 MSG_DATA_8 MSG_DATA_1 MSG_DATA_2 MSG_DATA_3 MSG_DATA_4 MSG_DATA_5 MSG_DATA_6 Rev.2.0, 07/03, page 915 of 960 Table A.1 Address (cont) Register Abbr. Bit Names Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Module HCAN (channel 0) Address H'FFFFE4FE MD9[7] H'FFFFE4FF MD9[8] H'FFFFE500 MD10[1] H'FFFFE501 MD10[2] H'FFFFE502 MD10[3] H'FFFFE503 MD10[4] H'FFFFE504 MD10[5] H'FFFFE505 MD10[6] H'FFFFE506 MD10[7] H'FFFFE507 MD10[8] H'FFFFE508 MD11[1] H'FFFFE509 MD11[2] H'FFFFE50A MD11[3] H'FFFFE50B MD11[4] H'FFFFE50C MD11[5] H'FFFFE50D MD11[6] H'FFFFE50E MD11[7] H'FFFFE50F MD11[8] H'FFFFE510 MD12[1] H'FFFFE511 MD12[2] H'FFFFE512 MD12[3] H'FFFFE513 MD12[4] H'FFFFE514 MD12[5] H'FFFFE515 MD12[6] H'FFFFE516 MD12[7] H'FFFFE517 MD12[8] H'FFFFE518 MD13[1] H'FFFFE519 MD13[2] H'FFFFE51A MD13[3] H'FFFFE51B MD13[4] H'FFFFE51C MD13[5] H'FFFFE51D MD13[6] H'FFFFE51E MD13[7] H'FFFFE51F MD13[8] MSG_DATA_7 MSG_DATA_8 MSG_DATA_1 MSG_DATA_2 MSG_DATA_3 MSG_DATA_4 MSG_DATA_5 MSG_DATA_6 MSG_DATA_7 MSG_DATA_8 MSG_DATA_1 MSG_DATA_2 MSG_DATA_3 MSG_DATA_4 MSG_DATA_5 MSG_DATA_6 MSG_DATA_7 MSG_DATA_8 MSG_DATA_1 MSG_DATA_2 MSG_DATA_3 MSG_DATA_4 MSG_DATA_5 MSG_DATA_6 MSG_DATA_7 MSG_DATA_8 MSG_DATA_1 MSG_DATA_2 MSG_DATA_3 MSG_DATA_4 MSG_DATA_5 MSG_DATA_6 MSG_DATA_7 MSG_DATA_8 Rev.2.0, 07/03, page 916 of 960 Table A.1 Address (cont) Register Abbr. Bit Names Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Module HCAN (channel 0) Address H'FFFFE520 MD14[1] H'FFFFE521 MD14[2] H'FFFFE522 MD14[3] H'FFFFE523 MD14[4] H'FFFFE524 MD14[5] H'FFFFE525 MD14[6] H'FFFFE526 MD14[7] H'FFFFE527 MD14[8] H'FFFFE528 MD15[1] H'FFFFE529 MD15[2] H'FFFFE52A MD15[3] H'FFFFE52B MD15[4] H'FFFFE52C MD15[5] H'FFFFE52D MD15[6] H'FFFFE52E MD15[7] H'FFFFE52F MD15[8] H'FFFFE530 -- to H'FFFFE5FF H'FFFFE600 MCR H'FFFFE601 GSR H'FFFFE602 BCR H'FFFFE603 H'FFFFE604 MBCR H'FFFFE605 H'FFFFE606 TXPR H'FFFFE607 H'FFFFE608 TXCR H'FFFFE609 H'FFFFE60A TXACK H'FFFFE60B H'FFFFE60C ABACK H'FFFFE60D H'FFFFE60E RXPR H'FFFFE60F MSG_DATA_1 MSG_DATA_2 MSG_DATA_3 MSG_DATA_4 MSG_DATA_5 MSG_DATA_6 MSG_DATA_7 MSG_DATA_8 MSG_DATA_1 MSG_DATA_2 MSG_DATA_3 MSG_DATA_4 MSG_DATA_5 MSG_DATA_6 MSG_DATA_7 MSG_DATA_8 -- -- -- -- -- -- -- -- -- MCR7 -- BCR7 BCR15 MBCR7 -- -- BCR6 BCR14 MBCR6 MCR5 -- BCR5 BCR13 MBCR5 -- -- BCR4 BCR12 MBCR4 -- GSR3 BCR3 BCR11 MBCR3 MCR2 GSR2 BCR2 BCR10 MBCR2 MCR1 GSR1 BCR1 BCR9 MBCR1 MCR0 GSR0 BCR0 BCR8 -- MBCR8 -- TXPR8 -- TXCR8 -- TXACK8 -- ABACK8 RXPR0 RXPR8 HCAN (channel 1) MBCR15 MBCR14 MBCR13 MBCR12 MBCR11 MBCR10 MBCR9 TXPR7 TXPR15 TXCR7 TXCR15 TXACK7 TXPR6 TXPR14 TXCR6 TXCR14 TXACK6 TXPR5 TXPR13 TXCR5 TCR13 TXACK5 TXPR4 TXPR12 TXCR4 TXCR12 TXACK4 TXPR3 TXPR11 TXCR3 TXCR11 TXACK3 TXPR2 TXPR10 TXCR2 TSCR10 TXACK2 TXPR1 TXPR9 TXCR1 TXCR9 TXACK1 TXACK15 TXACK14 TXACK13 TXACK12 TXACK11 TXACK10 TXACK9 ABACK7 ABACK6 ABACK5 ABACK4 ABACK3 ABACK2 ABACK1 ABACK15 ABACK14 ABACK13 ABACK12 ABACK11 ABACK10 ABACK9 RXPR7 RXPR15 RXPR6 RXPR14 RXPR5 RXPR13 RXPR4 RXPR12 RXPR3 RXPR11 RXPR2 RXPR10 RXPR1 RXPR9 Rev.2.0, 07/03, page 917 of 960 Table A.1 Address (cont) Register Abbr. Bit Names Bit 7 RFPR7 RFPR15 IRR7 -- MBIMR7 Bit 6 RFPR6 RFPR14 IRR6 -- MBIMR6 Bit 5 RFPR5 RFPR13 IRR5 -- MBIMR5 Bit 4 RFPR4 RFPR12 IRR4 IRR12 MBIMR4 Bit 3 RFPR3 RFPR11 IRR3 -- MBIMR3 Bit 2 RFPR2 RFPR10 IRR2 -- MBIMR2 Bit 1 RFPR1 RFPR9 IRR1 IRR9 MBIMR1 Bit 0 RFPR0 RFPR8 IRR0 IRR8 MBIMR0 MBIMR8 -- IMR8 Module HCAN (channel 1) Address H'FFFFE610 RFPR H'FFFFE611 H'FFFFE612 IRR H'FFFFE613 H'FFFFE614 MBIMR H'FFFFE615 H'FFFFE616 IMR H'FFFFE617 H'FFFFE618 REC H'FFFFE619 TEC H'FFFFE61A UMSR H'FFFFE61B H'FFFFE61C LAFML H'FFFFE61D H'FFFFE61E LAFMH H'FFFFE61F H'FFFFE620 MC0[1] H'FFFFE621 MC0[2] H'FFFFE622 MC0[3] H'FFFFE623 MC0[4] H'FFFFE624 MC0[5] H'FFFFE625 MC0[6] H'FFFFE626 MC0[7] H'FFFFE627 MC0[8] H'FFFFE628 MC1[1] H'FFFFE629 MC1[2] H'FFFFE62A MC1[3] H'FFFFE62B MC1[4] H'FFFFE62C MC1[5] H'FFFFE62D MC1[6] H'FFFFE62E MC1[7] H'FFFFE62F MC1[8] H'FFFFE630 MC2[1] H'FFFFE631 MC2[2] H'FFFFE632 MC2[3] MBIMR15 MBIMR14 MBIMR13 MBIMR12 MBIMR11 MBIMR10 MBIMR9 IMR7 -- IMR6 -- IMR5 -- IMR4 IMR12 IMR3 -- IMR2 -- IMR1 IMR9 UMSR7 UMSR6 UMSR5 UMSR4 UMSR3 UMSR2 UMSR1 UMSR0 UMSR8 LAFML0 LAFML8 LAFMH0 LAFMH8 DLC0 UMSR15 UMSR14 UMSR13 UMSR12 UMSR11 UMSR10 UMSR9 LAFML7 LAFML6 LAFML5 LAFML4 LAFML3 LAFML2 LAFML1 LAFML15 LAFML14 LAFML13 LAFML12 LAFML11 LAFML10 LAFML9 LAFMH7 LAFMH6 LAFMH5 -- -- -- LAFMH1 LAFMH15 LAFMH14 LAFMH13 LAFMH12 LAFMH11 LAFMH10 LAFMH9 DLC3 DLC2 DLC1 STD_ID2 STD_ID1 STD_ID0 RTR IDE EXD_ID17 EXD_ID16 STD_ID10 STD_ID9 STD_ID8 STD_ID7 STD_ID6 STD_ID5 STD_ID4 STD_ID3 EXD_ID7 EXD_ID6 EXD_ID5 EXD_ID4 EXD_ID3 EXD_ID2 EXD_ID1 EXD_ID0 EXD_ID15 EXD_ID14 EXD_ID13 EXD_ID12 EXD_ID11 EXD_ID10 EXD_ID9 EXD_ID8 DLC3 DLC2 DLC1 DLC0 STD_ID2 STD_ID1 STD_ID0 RTR IDE EXD_ID17 EXD_ID16 STD_ID10 STD_ID9 STD_ID8 STD_ID7 STD_ID6 STD_ID5 STD_ID4 STD_ID3 EXD_ID7 EXD_ID6 EXD_ID5 EXD_ID4 EXD_ID3 EXD_ID2 EXD_ID1 EXD_ID0 EXD_ID15 EXD_ID14 EXD_ID13 EXD_ID12 EXD_ID11 EXD_ID10 EXD_ID9 EXD_ID8 DLC3 DLC2 DLC1 DLC0 Rev.2.0, 07/03, page 918 of 960 Table A.1 Address (cont) Register Abbr. Bit Names Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Module HCAN (channel 1) Address H'FFFFE633 MC2[4] H'FFFFE634 MC2[5] H'FFFFE635 MC2[6] H'FFFFE636 MC2[7] H'FFFFE637 MC2[8] H'FFFFE638 MC3[1] H'FFFFE639 MC3[2] H'FFFFE63A MC3[3] H'FFFFE63B MC3[4] H'FFFFE63C MC3[5] H'FFFFE63D MC3[6] H'FFFFE63E MC3[7] H'FFFFE63F MC3[8] H'FFFFE640 MC4[1] H'FFFFE641 MC4[2] H'FFFFE642 MC4[3] H'FFFFE643 MC4[4] H'FFFFE644 MC4[5] H'FFFFE645 MC4[6] H'FFFFE646 MC4[7] H'FFFFE647 MC4[8] H'FFFFE648 MC5[1] H'FFFFE649 MC5[2] H'FFFFE64A MC5[3] H'FFFFE64B MC5[4] H'FFFFE64C MC5[5] H'FFFFE64D MC5[6] H'FFFFE64E MC5[7] H'FFFFE64F MC5[8] H'FFFFE650 MC6[1] H'FFFFE651 MC6[2] H'FFFFE652 MC6[3] H'FFFFE653 MC6[4] H'FFFFE654 MC6[5] H'FFFFE655 MC6[6] STD_ID2 STD_ID1 STD_ID0 RTR IDE EXD_ID17 EXD_ID16 STD_ID2 STD_ID1 STD_ID0 RTR IDE EXD_ID17 EXD_ID16 STD_ID2 STD_ID1 STD_ID0 RTR IDE EXD_ID17 EXD_ID16 STD_ID2 STD_ID1 STD_ID0 RTR IDE EXD_ID17 EXD_ID16 STD_ID2 STD_ID1 STD_ID0 RTR IDE EXD_ID17 EXD_ID16 STD_ID10 STD_ID9 STD_ID8 STD_ID7 STD_ID6 STD_ID5 STD_ID4 STD_ID3 EXD_ID7 EXD_ID6 EXD_ID5 EXD_ID4 EXD_ID3 EXD_ID2 EXD_ID1 EXD_ID0 EXD_ID15 EXD_ID14 EXD_ID13 EXD_ID12 EXD_ID11 EXD_ID10 EXD_ID9 EXD_ID8 DLC3 DLC2 DLC1 DLC0 STD_ID10 STD_ID9 STD_ID8 STD_ID7 STD_ID6 STD_ID5 STD_ID4 STD_ID3 EXD_ID7 EXD_ID6 EXD_ID5 EXD_ID4 EXD_ID3 EXD_ID2 EXD_ID1 EXD_ID0 EXD_ID15 EXD_ID14 EXD_ID13 EXD_ID12 EXD_ID11 EXD_ID10 EXD_ID9 EXD_ID8 DLC3 DLC2 DLC1 DLC0 STD_ID10 STD_ID9 STD_ID8 STD_ID7 STD_ID6 STD_ID5 STD_ID4 STD_ID3 EXD_ID7 EXD_ID6 EXD_ID5 EXD_ID4 EXD_ID3 EXD_ID2 EXD_ID1 EXD_ID0 EXD_ID15 EXD_ID14 EXD_ID13 EXD_ID12 EXD_ID11 EXD_ID10 EXD_ID9 EXD_ID8 DLC3 DLC2 DLC1 DLC0 STD_ID10 STD_ID9 STD_ID8 STD_ID7 STD_ID6 STD_ID5 STD_ID4 STD_ID3 EXD_ID7 EXD_ID6 EXD_ID5 EXD_ID4 EXD_ID3 EXD_ID2 EXD_ID1 EXD_ID0 EXD_ID15 EXD_ID14 EXD_ID13 EXD_ID12 EXD_ID11 EXD_ID10 EXD_ID9 EXD_ID8 DLC3 DLC2 DLC1 DLC0 STD_ID10 STD_ID9 STD_ID8 STD_ID7 STD_ID6 STD_ID5 STD_ID4 STD_ID3 Rev.2.0, 07/03, page 919 of 960 Table A.1 Address (cont) Register Abbr. Bit Names Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Module Address H'FFFFE656 MC6[7] H'FFFFE657 MC6[8] H'FFFFE658 MC7[1] H'FFFFE659 MC7[2] H'FFFFE65A MC7[3] H'FFFFE65B MC7[4] H'FFFFE65C MC7[5] H'FFFFE65D MC7[6] H'FFFFE65E MC7[7] H'FFFFE65F MC7[8] H'FFFFE660 MC8[1] H'FFFFE661 MC8[2] H'FFFFE662 MC8[3] H'FFFFE663 MC8[4] H'FFFFE664 MC8[5] H'FFFFE665 MC8[6] H'FFFFE666 MC8[7] H'FFFFE667 MC8[8] H'FFFFE668 MC9[1] H'FFFFE669 MC9[2] H'FFFFE66A MC9[3] H'FFFFE66B MC9[4] H'FFFFE66C MC9[5] H'FFFFE66D MC9[6] H'FFFFE66E MC9[7] H'FFFFE66F MC9[8] H'FFFFE670 MC10[1] H'FFFFE671 MC10[2] H'FFFFE672 MC10[3] H'FFFFE673 MC10[4] H'FFFFE674 MC10[5] H'FFFFE675 MC10[6] H'FFFFE676 MC10[7] H'FFFFE677 MC10[8] EXD_ID7 EXD_ID6 EXD_ID5 EXD_ID4 EXD_ID3 EXD_ID2 EXD_ID1 EXD_ID0 HCAN (channel 1) EXD_ID15 EXD_ID14 EXD_ID13 EXD_ID12 EXD_ID11 EXD_ID10 EXD_ID9 EXD_ID8 DLC3 DLC2 DLC1 DLC0 STD_ID2 STD_ID1 STD_ID0 RTR IDE EXD_ID17 EXD_ID16 STD_ID10 STD_ID9 STD_ID8 STD_ID7 STD_ID6 STD_ID5 STD_ID4 STD_ID3 EXD_ID7 EXD_ID6 EXD_ID5 EXD_ID4 EXD_ID3 EXD_ID2 EXD_ID1 EXD_ID0 EXD_ID15 EXD_ID14 EXD_ID13 EXD_ID12 EXD_ID11 EXD_ID10 EXD_ID9 EXD_ID8 DLC3 DLC2 DLC1 DLC0 STD_ID2 STD_ID1 STD_ID0 RTR IDE EXD_ID17 EXD_ID16 STD_ID10 STD_ID9 STD_ID8 STD_ID7 STD_ID6 STD_ID5 STD_ID4 STD_ID3 EXD_ID7 EXD_ID6 EXD_ID5 EXD_ID4 EXD_ID3 EXD_ID2 EXD_ID1 EXD_ID0 EXD_ID15 EXD_ID14 EXD_ID13 EXD_ID12 EXD_ID11 EXD_ID10 EXD_ID9 EXD_ID8 DLC3 DLC2 DLC1 DLC0 STD_ID2 STD_ID1 STD_ID0 RTR IDE EXD_ID17 EXD_ID16 STD_ID10 STD_ID9 STD_ID8 STD_ID7 STD_ID6 STD_ID5 STD_ID4 STD_ID3 EXD_ID7 EXD_ID6 EXD_ID5 EXD_ID4 EXD_ID3 EXD_ID2 EXD_ID1 EXD_ID0 EXD_ID15 EXD_ID14 EXD_ID13 EXD_ID12 EXD_ID11 EXD_ID10 EXD_ID9 EXD_ID8 DLC3 DLC2 DLC1 DLC0 STD_ID2 STD_ID1 STD_ID0 RTR IDE EXD_ID17 EXD_ID16 STD_ID10 STD_ID9 STD_ID8 STD_ID7 STD_ID6 STD_ID5 STD_ID4 STD_ID3 EXD_ID7 EXD_ID6 EXD_ID5 EXD_ID4 EXD_ID3 EXD_ID2 EXD_ID1 EXD_ID0 EXD_ID15 EXD_ID14 EXD_ID13 EXD_ID12 EXD_ID11 EXD_ID10 EXD_ID9 EXD_ID8 Rev.2.0, 07/03, page 920 of 960 Table A.1 Address (cont) Register Abbr. Bit Names Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 DLC3 Bit 2 DLC2 Bit 1 DLC1 Bit 0 DLC0 Module HCAN (channel 1) Address H'FFFFE678 MC11[1] H'FFFFE679 MC11[2] H'FFFFE67A MC11[3] H'FFFFE67B MC11[4] H'FFFFE67C MC11[5] H'FFFFE67D MC11[6] H'FFFFE67E MC11[7] H'FFFFE67F MC11[8] H'FFFFE680 MC12[1] H'FFFFE681 MC12[2] H'FFFFE682 MC12[3] H'FFFFE683 MC12[4] H'FFFFE684 MC12[5] H'FFFFE685 MC12[6] H'FFFFE686 MC12[7] H'FFFFE687 MC12[8] H'FFFFE688 MC13[1] H'FFFFE689 MC13[2] H'FFFFE68A MC13[3] H'FFFFE68B MC13[4] H'FFFFE68C MC13[5] H'FFFFE68D MC13[6] H'FFFFE68E MC13[7] H'FFFFE68F MC13[8] H'FFFFE690 MC14[1] H'FFFFE691 MC14[2] H'FFFFE692 MC14[3] H'FFFFE693 MC14[4] H'FFFFE694 MC14[5] H'FFFFE695 MC14[6] H'FFFFE696 MC14[7] H'FFFFE697 MC14[8] H'FFFFE698 MC15[1] H'FFFFE699 MC15[2] H'FFFFE69A MC15[3] STD_ID2 STD_ID1 STD_ID0 RTR STD_ID2 STD_ID1 STD_ID0 RTR STD_ID2 STD_ID1 STD_ID0 RTR STD_ID2 STD_ID1 STD_ID0 RTR IDE EXD_ID17 EXD_ID16 STD_ID10 STD_ID9 STD_ID8 STD_ID7 STD_ID6 STD_ID5 STD_ID4 STD_ID3 EXD_ID7 EXD_ID6 EXD_ID5 EXD_ID4 EXD_ID3 EXD_ID2 EXD_ID1 EXD_ID0 EXD_ID15 EXD_ID14 EXD_ID13 EXD_ID12 EXD_ID11 EXD_ID10 EXD_ID9 EXD_ID8 DLC3 DLC2 DLC1 DLC0 IDE EXD_ID17 EXD_ID16 STD_ID10 STD_ID9 STD_ID8 STD_ID7 STD_ID6 STD_ID5 STD_ID4 STD_ID3 EXD_ID7 EXD_ID6 EXD_ID5 EXD_ID4 EXD_ID3 EXD_ID2 EXD_ID1 EXD_ID0 EXD_ID15 EXD_ID14 EXD_ID13 EXD_ID12 EXD_ID11 EXD_ID10 EXD_ID9 EXD_ID8 DLC3 DLC2 DLC1 DLC0 IDE EXD_ID17 EXD_ID16 STD_ID10 STD_ID9 STD_ID8 STD_ID7 STD_ID6 STD_ID5 STD_ID4 STD_ID3 EXD_ID7 EXD_ID6 EXD_ID5 EXD_ID4 EXD_ID3 EXD_ID2 EXD_ID1 EXD_ID0 EXD_ID15 EXD_ID14 EXD_ID13 EXD_ID12 EXD_ID11 EXD_ID10 EXD_ID9 EXD_ID8 DLC3 DLC2 DLC1 DLC0 IDE EXD_ID17 EXD_ID16 STD_ID10 STD_ID9 STD_ID8 STD_ID7 STD_ID6 STD_ID5 STD_ID4 STD_ID3 EXD_ID7 EXD_ID6 EXD_ID5 EXD_ID4 EXD_ID3 EXD_ID2 EXD_ID1 EXD_ID0 EXD_ID15 EXD_ID14 EXD_ID13 EXD_ID12 EXD_ID11 EXD_ID10 EXD_ID9 EXD_ID8 DLC3 DLC2 DLC1 DLC0 Rev.2.0, 07/03, page 921 of 960 Table A.1 Address (cont) Register Abbr. Bit Names Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Module HCAN (channel 1) Address H'FFFFE69B MC15[4] H'FFFFE69C MC15[5] H'FFFFE69D MC15[6] H'FFFFE69E MC15[7] H'FFFFE69F MC15[8] H'FFFFE6A0 -- to H'FFFFE6AF H'FFFFE6B0 MD0[1] H'FFFFE6B1 MD0[2] H'FFFFE6B2 MD0[3] H'FFFFE6B3 MD0[4] H'FFFFE6B4 MD0[5] H'FFFFE6B5 MD0[6] H'FFFFE6B6 MD0[7] H'FFFFE6B7 MD0[8] H'FFFFE6B8 MD1[1] H'FFFFE6B9 MD1[2] H'FFFFE6BA MD1[3] H'FFFFE6BB MD1[4] H'FFFFE6BC MD1[5] H'FFFFE6BD MD1[6] H'FFFFE6BE MD1[7] H'FFFFE6BF MD1[8] H'FFFFE6C0 MD2[1] H'FFFFE6C1 MD2[2] H'FFFFE6C2 MD2[3] H'FFFFE6C3 MD2[4] H'FFFFE6C4 MD2[5] H'FFFFE6C5 MD2[6] H'FFFFE6C6 MD2[7] H'FFFFE6C7 MD2[8] H'FFFFE6C8 MD3[1] H'FFFFE6C9 MD3[2] H'FFFFE6CA MD3[3] H'FFFFE6CB MD3[4] STD_ID2 STD_ID1 STD_ID0 RTR IDE EXD_ID17 EXD_ID16 STD_ID10 STD_ID9 STD_ID8 STD_ID7 STD_ID6 STD_ID5 STD_ID4 STD_ID3 EXD_ID7 EXD_ID6 EXD_ID5 EXD_ID4 EXD_ID3 EXD_ID2 EXD_ID1 EXD_ID0 EXD_ID15 EXD_ID14 EXD_ID13 EXD_ID12 EXD_ID11 EXD_ID10 EXD_ID9 EXD_ID8 -- -- -- -- -- -- -- -- MSG_DATA_1 MSG_DATA_2 MSG_DATA_3 MSG_DATA_4 MSG_DATA_5 MSG_DATA_6 MSG_DATA_7 MSG_DATA_8 MSG_DATA_1 MSG_DATA_2 MSG_DATA_3 MSG_DATA_4 MSG_DATA_5 MSG_DATA_6 MSG_DATA_7 MSG_DATA_8 MSG_DATA_1 MSG_DATA_2 MSG_DATA_3 MSG_DATA_4 MSG_DATA_5 MSG_DATA_6 MSG_DATA_7 MSG_DATA_8 MSG_DATA_1 MSG_DATA_2 MSG_DATA_3 MSG_DATA_4 Rev.2.0, 07/03, page 922 of 960 Table A.1 Address (cont) Register Abbr. Bit Names Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Module HCAN (channel 1) Address H'FFFFE6CC MD3[5] H'FFFFE6CD MD3[6] H'FFFFE6CE MD3[7] H'FFFFE6CF MD3[8] H'FFFFE6D0 MD4[1] H'FFFFE6D1 MD4[2] H'FFFFE6D2 MD4[3] H'FFFFE6D3 MD4[4] H'FFFFE6D4 MD4[5] H'FFFFE6D5 MD4[6] H'FFFFE6D6 MD4[7] H'FFFFE6D7 MD4[8] H'FFFFE6D8 MD5[1] H'FFFFE6D9 MD5[2] H'FFFFE6DA MD5[3] H'FFFFE6DB MD5[4] H'FFFFE6DC MD5[5] H'FFFFE6DD MD5[6] H'FFFFE6DE MD5[7] H'FFFFE6DF MD5[8] H'FFFFE6E0 MD6[1] H'FFFFE6E1 MD6[2] H'FFFFE6E2 MD6[3] H'FFFFE6E3 MD6[4] H'FFFFE6E4 MD6[5] H'FFFFE6E5 MD6[6] H'FFFFE6E6 MD6[7] H'FFFFE6E7 MD6[8] H'FFFFE6E8 MD7[1] H'FFFFE6E9 MD7[2] H'FFFFE6EA MD7[3] H'FFFFE6EB MD7[4] H'FFFFE6EC MD7[5] H'FFFFE6ED MD7[6] H'FFFFE6EE MD7[7] MSG_DATA_5 MSG_DATA_6 MSG_DATA_7 MSG_DATA_8 MSG_DATA_1 MSG_DATA_2 MSG_DATA_3 MSG_DATA_4 MSG_DATA_5 MSG_DATA_6 MSG_DATA_7 MSG_DATA_8 MSG_DATA_1 MSG_DATA_2 MSG_DATA_3 MSG_DATA_4 MSG_DATA_5 MSG_DATA_6 MSG_DATA_7 MSG_DATA_8 MSG_DATA_1 MSG_DATA_2 MSG_DATA_3 MSG_DATA_4 MSG_DATA_5 MSG_DATA_6 MSG_DATA_7 MSG_DATA_8 MSG_DATA_1 MSG_DATA_2 MSG_DATA_3 MSG_DATA_4 MSG_DATA_5 MSG_DATA_6 MSG_DATA_7 Rev.2.0, 07/03, page 923 of 960 Table A.1 Address (cont) Register Abbr. Bit Names Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Module HCAN (channel 1) Address H'FFFFE6EF MD7[8] H'FFFFE6F0 MD8[1] H'FFFFE6F1 MD8[2] H'FFFFE6F2 MD8[3] H'FFFFE6F3 MD8[4] H'FFFFE6F4 MD8[5] H'FFFFE6F5 MD8[6] H'FFFFE6F6 MD8[7] H'FFFFE6F7 MD8[8] H'FFFFE6F8 MD9[1] H'FFFFE6F9 MD9[2] H'FFFFE6FA MD9[3] H'FFFFE6FB MD9[4] H'FFFFE6FC MD9[5] H'FFFFE6FD MD9[6] H'FFFFE6FE MD9[7] H'FFFFE6FF MD9[8] H'FFFFE700 MD10[1] H'FFFFE701 MD10[2] H'FFFFE702 MD10[3] H'FFFFE703 MD10[4] H'FFFFE704 MD10[5] H'FFFFE705 MD10[6] H'FFFFE706 MD10[7] H'FFFFE707 MD10[8] H'FFFFE708 MD11[1] H'FFFFE709 MD11[2] H'FFFFE70A MD11[3] H'FFFFE70B MD11[4] H'FFFFE70C MD11[5] H'FFFFE70D MD11[6] H'FFFFE70E MD11[7] H'FFFFE70F MD11[8] H'FFFFE710 MD12[1] H'FFFFE711 MD12[2] MSG_DATA_8 MSG_DATA_1 MSG_DATA_2 MSG_DATA_3 MSG_DATA_4 MSG_DATA_5 MSG_DATA_6 MSG_DATA_7 MSG_DATA_8 MSG_DATA_1 MSG_DATA_2 MSG_DATA_3 MSG_DATA_4 MSG_DATA_5 MSG_DATA_6 MSG_DATA_7 MSG_DATA_8 MSG_DATA_1 MSG_DATA_2 MSG_DATA_3 MSG_DATA_4 MSG_DATA_5 MSG_DATA_6 MSG_DATA_7 MSG_DATA_8 MSG_DATA_1 MSG_DATA_2 MSG_DATA_3 MSG_DATA_4 MSG_DATA_5 MSG_DATA_6 MSG_DATA_7 MSG_DATA_8 MSG_DATA_1 MSG_DATA_2 Rev.2.0, 07/03, page 924 of 960 Table A.1 Address (cont) Register Abbr. Bit Names Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Module HCAN (channel 1) Address H'FFFFE712 MD12[3] H'FFFFE713 MD12[4] H'FFFFE714 MD12[5] H'FFFFE715 MD12[6] H'FFFFE716 MD12[7] H'FFFFE717 MD12[8] H'FFFFE718 MD13[1] H'FFFFE719 MD13[2] H'FFFFE71A MD13[3] H'FFFFE71B MD13[4] H'FFFFE71C MD13[5] H'FFFFE71D MD13[6] H'FFFFE71E MD13[7] H'FFFFE71F MD13[8] H'FFFFE720 MD14[1] H'FFFFE721 MD14[2] H'FFFFE722 MD14[3] H'FFFFE723 MD14[4] H'FFFFE724 MD14[5] H'FFFFE725 MD14[6] H'FFFFE726 MD14[7] H'FFFFE727 MD14[8] H'FFFFE728 MD15[1] H'FFFFE729 MD15[2] H'FFFFE72A MD15[3] H'FFFFE72B MD15[4] H'FFFFE72C MD15[5] H'FFFFE72D MD15[6] H'FFFFE72E MD15[7] H'FFFFE72F MD15[8] H'FFFFE730 -- to H'FFFFE7FF MSG_DATA_3 MSG_DATA_4 MSG_DATA_5 MSG_DATA_6 MSG_DATA_7 MSG_DATA_8 MSG_DATA_1 MSG_DATA_2 MSG_DATA_3 MSG_DATA_4 MSG_DATA_5 MSG_DATA_6 MSG_DATA_7 MSG_DATA_8 MSG_DATA_1 MSG_DATA_2 MSG_DATA_3 MSG_DATA_4 MSG_DATA_5 MSG_DATA_6 MSG_DATA_7 MSG_DATA_8 MSG_DATA_1 MSG_DATA_2 MSG_DATA_3 MSG_DATA_4 MSG_DATA_5 MSG_DATA_6 MSG_DATA_7 MSG_DATA_8 -- -- -- -- -- -- -- -- -- Rev.2.0, 07/03, page 925 of 960 Table A.1 Address (cont) Register Abbr. Bit Names Bit 7 FWE -- -- Bit 6 -- -- -- Bit 5 -- -- -- Bit 4 FLER -- -- Bit 3 -- -- -- Bit 2 -- -- -- Bit 1 -- -- -- Bit 0 SCO PPVS EPVB Module FLASH Address H'FFFFE800 FCCS H'FFFFE801 FPCS H'FFFFE802 FECS H'FFFFE803 -- H'FFFFE804 FKEY H'FFFFE805 FMATS H'FFFFE806 FTDAR H'FFFFE807 -- to H'FFFFEBFF H'FFFFEC00 UBARH H'FFFFEC01 H'FFFFEC02 UBARL H'FFFFEC03 System area. Do not access this area. K7 MS7 TDER K6 MS6 TDA6 K5 MS5 TDA5 K4 MS4 TDA4 K3 MS3 TDA3 K2 MS2 TDA2 K1 MS1 TDA1 K0 MS0 TDA0 System area. Do not access this area. UBA31 UBA23 UBA15 UBA7 UBA30 UBA22 UBA14 UBA6 UBM30 UBM22 UBM14 UBM6 -- CP0 -- -- -- UBA29 UBA21 UBA13 UBA5 UBM29 UBM21 UBM13 UBM5 -- ID1 -- -- -- UBA28 UBA20 UBA12 UBA4 UBM28 UBM20 UBM12 UBM4 -- ID0 -- -- -- UBA27 UBA19 UBA11 UBA3 UBM27 UBM19 UBM11 UBM3 -- RW1 -- -- -- UBA26 UBA18 UBA10 UBA2 UBM26 UBM18 UBM10 UBM2 -- RW0 -- CKS1 -- UBA25 UBA17 UBA9 UBA1 UBM25 UBM17 UBM9 UBM1 -- SZ1 -- CKS0 -- UBA24 UBA16 UBA8 UBA0 UBM24 UBM16 UBM8 UBM0 -- SZ0 -- UBID -- UBC H'FFFFEC04 UBAMRH UBM31 H'FFFFEC05 H'FFFFEC06 UBAMRL H'FFFFEC07 H'FFFFEC08 UBBR H'FFFFEC09 H'FFFFEC0A UBCR H'FFFFEC0B H'FFFFEC0C -- to H'FFFFEC0F H'FFFFEC10 TCSR * H'FFFFEC11 TCNT * H'FFFFEC12 -- -- UBM23 UBM15 UBM7 -- CP1 -- -- -- -- OVF WT/IT TME -- -- CKS2 CKS1 CKS0 WDT -- RSTE HIZ -- -- RSTS -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- Powerdown state -- H'FFFFEC13 RSTCSR * WOVF H'FFFFEC14 SBYCR H'FFFFEC15 -- to H'FFFFEC1F SSBY -- Note: * This is the read address. The write address is H'FFFEC10 for TCSR and TCNT, and H'FFFEC12 for RSTCSR. For details, see section 13.2.4, Register Access. Rev.2.0, 07/03, page 926 of 960 Table A.1 Address (cont) Register Abbr. Bit Names Bit 7 -- -- IW31 CW3 W33 W13 -- -- -- Bit 6 -- -- IW30 CW2 W32 W12 -- -- -- Bit 5 -- -- IW21 CW1 W31 W11 -- -- -- Bit 4 -- -- IW20 CW0 W30 W10 -- -- -- Bit 3 -- A3SZ IW11 SW3 W23 W03 -- RAMS -- Bit 2 -- A2SZ IW10 SW2 W22 W02 -- RAM2 -- Bit 1 -- A1SZ IW01 SW1 W21 W01 -- RAM1 -- Bit 0 -- A0SZ IW00 SW0 W20 W00 -- RAM0 -- -- Module BSC Address H'FFFFEC20 BCR1 H'FFFFEC21 H'FFFFEC22 BCR2 H'FFFFEC23 H'FFFFEC24 WCR H'FFFFEC25 H'FFFFEC26 RAMER H'FFFFEC27 H'FFFFEC28 -- to H'FFFFECAF H'FFFFECB0 DMAOR H'FFFFECB1 H'FFFFECB2 -- to H'FFFFECBF H'FFFFECC0 SAR0 H'FFFFECC1 H'FFFFECC2 H'FFFFECC3 H'FFFFECC4 DAR0 H'FFFFECC5 H'FFFFECC6 H'FFFFECC7 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- AE -- -- NMIF -- -- DME -- DMAC (all channels) -- DMAC (channel 0) H'FFFFECC8 DMATCR0 -- H'FFFFECC9 H'FFFFECCA H'FFFFECCB H'FFFFECCC CHCR0 H'FFFFECCD H'FFFFECCE H'FFFFECCF -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- SM1 TS1 -- RS4 SM0 TS0 -- RS3 -- TM -- RS2 -- IE -- RS1 DM1 TE -- RS0 DM0 DE Rev.2.0, 07/03, page 927 of 960 Table A.1 Address (cont) Register Abbr. Bit Names Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Module DMAC (channel 1) Address H'FFFFECD0 SAR1 H'FFFFECD1 H'FFFFECD2 H'FFFFECD3 H'FFFFECD4 DAR1 H'FFFFECD5 H'FFFFECD6 H'FFFFECD7 H'FFFFECD8 DMATCR1 -- H'FFFFECD9 H'FFFFECDA H'FFFFECDB H'FFFFECDC CHCR1 H'FFFFECDD H'FFFFECDE H'FFFFECDF H'FFFFECE0 SAR2 H'FFFFECE1 H'FFFFECE2 H'FFFFECE3 H'FFFFECE4 DAR2 H'FFFFECE5 H'FFFFECE6 H'FFFFECE7 H'FFFFECE8 DMATCR2 -- H'FFFFECE9 H'FFFFECEA H'FFFFECEB H'FFFFECEC CHCR2 H'FFFFECED H'FFFFECEE H'FFFFECEF -- -- -- -- -- -- -- -- -- -- SM1 TS1 -- RS4 SM0 TS0 -- RS3 -- TM -- RS2 -- IE -- RS1 DM1 TE RO RS0 DM0 DE -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- SM1 TS1 -- RS4 SM0 TS0 -- RS3 -- TM -- RS2 -- IE -- RS1 DM1 TE -- RS0 DM0 DE -- -- -- -- -- -- -- DMAC (channel 2) Rev.2.0, 07/03, page 928 of 960 Table A.1 Address (cont) Register Abbr. Bit Names Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Module DMAC (channel 3) Address H'FFFFECF0 SAR3 H'FFFFECF1 H'FFFFECF2 H'FFFFECF3 H'FFFFECF4 DAR3 H'FFFFECF5 H'FFFFECF6 H'FFFFECF7 H'FFFFECF8 DMATCR3 -- H'FFFFECF9 H'FFFFECFA H'FFFFECFB H'FFFFECFC CHCR3 H'FFFFECFD H'FFFFECFE H'FFFFECFF H'FFFFED00 IPRA H'FFFFED01 H'FFFFED02 IPRB H'FFFFED03 H'FFFFED04 IPRC H'FFFFED05 H'FFFFED06 IPRD H'FFFFED07 H'FFFFED08 IPRE H'FFFFED09 H'FFFFED0A IPRF H'FFFFED0B H'FFFFED0C IPRG H'FFFFED0D H'FFFFED0E IPRH H'FFFFED0F H'FFFFED10 IPRI H'FFFFED11 H'FFFFED12 IPRJ H'FFFFED13 -- -- -- -- -- -- -- -- -- -- SM1 TS1 DI RS4 SM0 TS0 -- RS3 -- TM -- RS2 -- IE -- RS1 DM1 TE -- RS0 DM0 DE -- -- -- -- -- -- -- INTC Rev.2.0, 07/03, page 929 of 960 Table A.1 Address (cont) Register Abbr. Bit Names Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Module INTC Address H'FFFFED14 IPRK H'FFFFED15 H'FFFFED16 IPRL H'FFFFED17 H'FFFFED18 ICR H'FFFFED19 H'FFFFED1A ISR H'FFFFED1B H'FFFFED1C -- to H'FFFFEFFF H'FFFFF000 SMR0 H'FFFFF001 BRR0 H'FFFFF002 SCR0 H'FFFFF003 TDR0 H'FFFFF004 SSR0 H'FFFFF005 RDR0 H'FFFFF006 SDCR0 H'FFFFF007 -- H'FFFFF008 SMR1 H'FFFFF009 BRR1 H'FFFFF00A SCR1 H'FFFFF00B TDR1 H'FFFFF00C SSR1 H'FFFFF00D RDR1 H'FFFFF00E SDCR1 H'FFFFF00F -- H'FFFFF010 SMR2 H'FFFFF011 BRR2 H'FFFFF012 SCR2 H'FFFFF013 TDR2 H'FFFFF014 SSR2 H'FFFFF015 RDR2 H'FFFFF016 SDCR2 H'FFFFF017 -- -- -- -- -- -- -- -- -- DIR -- -- -- -- -- -- -- TDRE RDRF ORER FER PER TEND MPB MPBT TIE RIE TE RE MPIE TEIE CKE1 CKE0 -- -- C/A -- -- CHR -- -- PE -- -- O/E DIR -- STOP -- -- MP -- -- CKS1 -- -- CKS0 TDRE RDRF ORER FER PER TEND MPB MPBT TIE RIE TE RE MPIE TEIE CKE1 CKE0 -- -- C/A -- -- CHR -- -- PE -- -- O/E DIR -- STOP -- -- MP -- -- CKS1 -- -- CKS0 TDRE RDRF ORER FER PER TEND MPB MPBT TIE RIE TE RE MPIE TEIE CKE1 CKE0 NMIL IRQ0S -- IRQ0F -- -- IRQ1S -- IRQ1F -- -- IRQ2S -- IRQ2F -- -- IRQ3S -- IRQ3F -- -- IRQ4S -- IRQ4F -- -- IRQ5S -- IRQ5F -- -- IRQ6S -- IRQ6F -- NMIE IRQ7S -- IRQ7F -- -- C/A CHR PE O/E STOP MP CKS1 CKS0 SCI (channel 0) SCI (channel 1) SCI (channel 2) Rev.2.0, 07/03, page 930 of 960 Table A.1 Address (cont) Register Abbr. Bit Names Bit 7 C/A Bit 6 CHR Bit 5 PE Bit 4 O/E Bit 3 STOP Bit 2 MP Bit 1 CKS1 Bit 0 CKS0 Module SCI (channel 3) Address H'FFFFF018 SMR3 H'FFFFF019 BRR3 H'FFFFF01A SCR3 H'FFFFF01B TDR3 H'FFFFF01C SSR3 H'FFFFF01D RDR3 H'FFFFF01E SDCR3 H'FFFFF01F -- H'FFFFF020 SMR4 H'FFFFF021 BRR4 H'FFFFF022 SCR4 H'FFFFF023 TDR4 H'FFFFF024 SSR4 H'FFFFF025 RDR4 H'FFFFF026 SDCR4 H'FFFFF027 -- to H'FFFFF3FF H'FFFFF400 TSTR2 H'FFFFF401 TSTR1 H'FFFFF402 TSTR3 H'FFFFF403 -- H'FFFFF404 PSCR1 H'FFFFF405 -- H'FFFFF406 PSCR2 H'FFFFF407 -- H'FFFFF408 PSCR3 H'FFFFF409 -- H'FFFFF40A PSCR4 H'FFFFF40B -- H'FFFFF40C -- to H'FFFFF41F H'FFFFF420 ICR0DH H'FFFFF421 H'FFFFF422 ICR0DL H'FFFFF423 TIE RIE TE RE MPIE TEIE CKE1 CKE0 TDRE RDRF ORER FER PER TEND MPB MPBT -- -- C/A -- -- CHR -- -- PE -- -- O/E DIR -- STOP -- -- MP -- -- CKS1 -- -- CKS0 SCI (channel 4) TIE RIE TE RE MPIE TEIE CKE1 CKE0 TDRE RDRF ORER FER PER TEND MPB MPBT -- -- -- -- -- -- -- -- DIR -- -- -- -- -- -- -- -- STR7D STR10 -- -- -- -- STR7C STR5 -- -- -- -- STR7B STR4 -- -- -- -- STR7A STR3 -- -- PSC1E -- PSC2E STR6D STR6C STR6B STR1A -- -- PSC1B -- PSC2B -- PSC3B -- PSC4B -- -- STR6A STR0 STR11 -- PSC1A -- PSC2A -- PSC3A -- PSC4A -- -- STR1B,2B STR2A -- -- PSC1D -- PSC2D -- PSC3D -- PSC4D -- -- -- -- PSC1C -- PSC2C -- PSC3C -- PSC4C -- -- ATU-II (all channels) -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- PSC3E -- PSC4E -- -- -- ATU-II (channel 0) Rev.2.0, 07/03, page 931 of 960 Table A.1 Address (cont) Register Abbr. Bit Names Bit 7 ITVA9 -- ITVA13A -- ITVA13B -- IO0D1 -- -- IIF2B -- -- Bit 6 ITVA8 -- ITVA12A -- ITVA12B -- IO0D0 -- -- IIF2A -- -- Bit 5 ITVA7 -- ITVA11A -- ITVA11B -- IO0C1 -- -- IIF1 -- -- Bit 4 ITVA6 -- ITVA10A -- ITVA10B -- IO0C0 -- -- OVF0 -- OVE0 Bit 3 ITVE9 -- ITVE13A -- ITVE13B -- IO0B1 -- -- ICF0D -- ICE0D Bit 2 ITVE8 -- ITVE12A -- ITVE12B -- IO0B0 -- -- ICF0C -- ICE0C Bit 1 ITVE7 -- ITVE11A -- ITVE11B -- IO0A1 -- -- ICF0B -- ICE0B Bit 0 TIVE6 -- ITVE10A -- ITVE10B -- IO0A0 -- -- ICF0A -- ICE0A ATU-II (channel 0) Module ATU-II (channel 1) ATU-II (channel 2) Address H'FFFFF424 ITVRR1 H'FFFFF425 -- H'FFFFF426 ITVRR2A H'FFFFF427 -- H'FFFFF428 ITVRR2B H'FFFFF429 -- H'FFFFF42A TIOR0 H'FFFFF42B -- H'FFFFF42C TSR0 H'FFFFF42D H'FFFFF42E TIER0 H'FFFFF42F H'FFFFF430 TCNT0H H'FFFFF431 H'FFFFF432 TCNT0L H'FFFFF433 H'FFFFF434 ICR0AH H'FFFFF435 H'FFFFF436 ICR0AL H'FFFFF437 H'FFFFF438 ICR0BH H'FFFFF439 H'FFFFF43A ICR0BL H'FFFFF43B H'FFFFF43C ICR0CH H'FFFFF43D H'FFFFF43E ICR0CL H'FFFFF43F Rev.2.0, 07/03, page 932 of 960 Table A.1 Address (cont) Register Abbr. Bit Names Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Module ATU-II (channel 1) Address H'FFFFF440 TCNT1A H'FFFFF441 H'FFFFF442 TCNT1B H'FFFFF443 H'FFFFF444 GR1A H'FFFFF445 H'FFFFF446 GR1B H'FFFFF447 H'FFFFF448 GR1C H'FFFFF449 H'FFFFF44A GR1D H'FFFFF44B H'FFFFF44C GR1E H'FFFFF44D H'FFFFF44E GR1F H'FFFFF44F H'FFFFF450 GR1G H'FFFFF451 H'FFFFF452 GR1H H'FFFFF453 H'FFFFF454 OCR1 H'FFFFF455 H'FFFFF456 OSBR1 H'FFFFF457 H'FFFFF458 TIOR1B H'FFFFF459 TIOR1A H'FFFFF45A TIOR1D H'FFFFF45B TIOR1C H'FFFFF45C TCR1B H'FFFFF45D TCR1A H'FFFFF45E TSR1A H'FFFFF45F H'FFFFF460 TSR1B H'FFFFF461 -- -- -- -- -- -- -- IMF1H -- -- IO1D2 IO1B2 IO1H2 IO1F2 -- -- -- IMF1G -- -- IO1D1 IO1B1 IO1H1 IO1F1 IO1D0 IO1B0 IO1H0 IO1F0 -- -- -- -- IO1C2 IO1A2 IO1G2 IO1E2 IO1C1 IO1A1 IO1G1 IO1E1 IO1C0 IO1A0 IO1G0 IO1E0 CKEGB1 CKEGB0 CKSELB3 CKSELB2 CKSELB1 CKSELB0 CKEGA1 CKEGA0 CKSELA3 CKSELA2 CKSELA1 CKSELA0 -- IMF1F -- -- -- IMF1E -- -- -- IMF1D -- -- -- IMF1C -- -- -- IMF1B -- -- OVF1A IMF1A OVF1B CMF1 Rev.2.0, 07/03, page 933 of 960 Table A.1 Address (cont) Register Abbr. Bit Names Bit 7 -- IME1H -- -- Bit 6 -- IME1G -- -- -- -- Bit 5 -- IME1F -- -- -- -- Bit 4 -- IME1E -- -- -- -- Bit 3 -- IME1D -- -- -- -- Bit 2 -- IME1C -- -- -- -- Bit 1 -- IME1B -- -- -- -- Bit 0 OVE1A IME1A OVE1B CME1 -- -- -- Module ATU-II (channel 1) Address H'FFFFF462 TIER1A H'FFFFF463 H'FFFFF464 TIER1B H'FFFFF465 H'FFFFF466 TRGMDR TRGMD H'FFFFF467 -- to H'FFFFF47F H'FFFFF480 TSR3 H'FFFFF481 H'FFFFF482 TIER3 H'FFFFF483 H'FFFFF484 TMDR H'FFFFF485 -- to H'FFFFF49F H'FFFFF4A0 TCNT3 H'FFFFF4A1 H'FFFFF4A2 TGR3A H'FFFFF4A3 H'FFFFF4A4 GR3B H'FFFFF4A5 H'FFFFF4A6 GR3C H'FFFFF4A7 H'FFFFF4A8 GR3D H'FFFFF4A9 H'FFFFF4AA TIOR3B H'FFFFF4AB TIOR3A H'FFFFF4AC TCR3 H'FFFFF4AD -- to H'FFFFF4BF CCI3D CCI3B -- -- -- -- IMF4C -- IME4C -- -- OVF5 IMF4B OVE5 IME4B -- -- IMF5D IMF4A IME5D IME4A -- -- IMF5C OVF3 IME5C OVE3 -- -- IMF5B IMF3D IME5B IME3D -- -- IMF5A IMF3C IME5A IME3C T5PWM -- OVF4 IMF3B OVE4 IME3B T4PWM -- IMF4D IMF3A IME4D IME3A T3PWM -- ATU-II (channels 3 to 5) -- ATU-II (channel 3) IO3D2 IO3B2 -- -- IO3D1 IO3B1 CKEG1 -- IO3D0 IO3B0 CKEG0 -- CCI3C CCI3A CKSEL3 -- IO3C2 IO3A2 CKSEL2 -- IO3C1 IO3A1 CKSEL1 -- IO3C0 IO3A0 CKSEL0 -- -- Rev.2.0, 07/03, page 934 of 960 Table A.1 Address (cont) Register Abbr. Bit Names Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Module ATU-II (channel 4) Address H'FFFFF4C0 TCNT4 H'FFFFF4C1 H'FFFFF4C2 GR4A H'FFFFF4C3 H'FFFFF4C4 GR4B H'FFFFF4C5 H'FFFFF4C6 GR4C H'FFFFF4C7 H'FFFFF4C8 GR4D H'FFFFF4C9 H'FFFFF4CA TIOR4B H'FFFFF4CB TIOR4A H'FFFFF4CC TCR4 H'FFFFF4CD -- to H'FFFFF4DF H'FFFFF4E0 TCNT5 H'FFFFF4E1 H'FFFFF4E2 GR5A H'FFFFF4E3 H'FFFFF4E4 GR5B H'FFFFF4E5 H'FFFFF4E6 GR5C H'FFFFF4E7 H'FFFFF4E8 GR5D H'FFFFF4E9 H'FFFFF4EA TIOR5B H'FFFFF4EB TIOR5A H'FFFFF4EC TCR5 H'FFFFF4ED -- to H'FFFFF4EF CCI5D CCI5B -- -- IO5D2 IO5B2 -- -- IO5D1 IO5B1 CKEG1 -- IO5D0 IO5B0 CKEG0 -- CCI5C CCI5A CKSEL3 -- IO5C2 IO5A2 CKSEL2 -- IO5C1 IO5A1 CKSEL1 -- IO5C0 IO5A0 CKSEL0 -- CCI4D CCI4B -- -- IO4D2 IO4B2 -- -- IO4D1 IO4B1 CKEG1 -- IO4D0 IO4B0 CKEG0 -- CCI4C CCI4A CKSEL3 -- IO4C2 IO4A2 CKSEL2 -- IO4C1 IO4A1 CKSEL1 -- IO4C0 IO4A0 CKSEL0 -- -- ATU-II (channel 5) -- Rev.2.0, 07/03, page 935 of 960 Table A.1 Address (cont) Register Abbr. Bit Names Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Module ATU-II (channel 6) Address H'FFFFF500 TCNT6A H'FFFFF501 H'FFFFF502 TCNT6B H'FFFFF503 H'FFFFF504 TCNT6C H'FFFFF505 H'FFFFF506 TCNT6D H'FFFFF507 H'FFFFF508 CYLR6A H'FFFFF509 H'FFFFF50A CYLR6B H'FFFFF50B H'FFFFF50C CYLR6C H'FFFFF50D H'FFFFF50E CYLR6D H'FFFFF50F H'FFFFF510 BFR6A H'FFFFF511 H'FFFFF512 BFR6B H'FFFFF513 H'FFFFF514 BFR6C H'FFFFF515 H'FFFFF516 BFR6D H'FFFFF517 H'FFFFF518 DTR6A H'FFFFF519 H'FFFFF51A DTR6B H'FFFFF51B H'FFFFF51C DTR6C H'FFFFF51D Rev.2.0, 07/03, page 936 of 960 Table A.1 Address (cont) Register Abbr. Bit Names Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Module ATU-II (channel 6) -- -- -- UD6D -- -- DTSELD -- CKSELD2 CKSELD1 CKSELD0 -- CKSELB2 CKSELB1 CKSELB0 -- -- UD6C -- -- DTSELC -- -- UD6B -- -- DTSELB -- -- UD6A -- -- DTSELA -- -- CMF6D -- CME6D CKSELC2 CKSELC1 CKSELC0 CKSELA2 CKSELA1 CKSELA0 -- CMF6C -- CME6C -- CMF6B -- CME6B -- CMF6A -- CME6A Address H'FFFFF51E DTR6D H'FFFFF51F H'FFFFF520 TCR6B H'FFFFF521 TCR6A H'FFFFF522 TSR6 H'FFFFF523 H'FFFFF524 TIER6 H'FFFFF525 H'FFFFF526 PMDR6 H'FFFFF527 -- to H'FFFFF57F H'FFFFF580 TCNT7A H'FFFFF581 H'FFFFF582 TCNT7B H'FFFFF583 H'FFFFF584 TCNT7C H'FFFFF585 H'FFFFF586 TCNT7D H'FFFFF587 H'FFFFF588 CYLR7A H'FFFFF589 H'FFFFF58A CYLR7B H'FFFFF58B H'FFFFF58C CYLR7C H'FFFFF58D H'FFFFF58E CYLR7D H'FFFFF58F H'FFFFF590 BFR7A H'FFFFF591 H'FFFFF592 BFR7B H'FFFFF593 H'FFFFF594 BFR7C H'FFFFF595 H'FFFFF596 BFR7D H'FFFFF597 CNTSELD CNTSELC CNTSELB CNTSELA -- -- -- -- -- ATU-II (channel 7) Rev.2.0, 07/03, page 937 of 960 Table A.1 Address (cont) Register Abbr. Bit Names Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Module ATU-II (channel 7) Address H'FFFFF598 DTR7A H'FFFFF599 H'FFFFF59A DTR7B H'FFFFF59B H'FFFFF59C DTR7C H'FFFFF59D H'FFFFF59E DTR7D H'FFFFF59F H'FFFFF5A0 TCR7B H'FFFFF5A1 TCR7A H'FFFFF5A2 TSR7 H'FFFFF5A3 H'FFFFF5A4 TIER7 H'FFFFF5A5 H'FFFFF5A6 -- to H'FFFFF5BF H'FFFFF5C0 TCNT11 H'FFFFF5C1 H'FFFFF5C2 GR11A H'FFFFF5C3 H'FFFFF5C4 GR11B H'FFFFF5C5 H'FFFFF5C6 TIOR11 H'FFFFF5C7 -- H'FFFFF5C8 TCR11 H'FFFFF5C9 -- H'FFFFF5CA TSR11 H'FFFFF5CB H'FFFFF5CC TIER11 H'FFFFF5CD H'FFFFF5CE -- to H'FFFFF5FF H'FFFFF600 TCNT2A H'FFFFF601 -- -- -- -- -- -- -- -- -- IO11B2 -- -- -- -- -- -- -- -- IO11B1 -- CKEG1 -- -- -- -- -- -- IO11B0 -- CKEG0 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- IO11A2 -- IO11A1 -- IO11A0 -- -- -- -- -- -- -- -- CKSELD2 CKSELD1 CKSELD0 -- CKSELB2 CKSELB1 CKSELB0 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- CMF7D -- CME7D -- CKSELC2 CKSELC1 CKSELC0 CKSELA2 CKSELA1 CKSELA0 -- CMF7C -- CME7C -- -- C ATU-II (channel 11) CKSELA2 CKSELA1 CKSELA0 -- -- -- -- -- -- -- -- IMF11B -- IME11B -- -- OVF11 IMF11A OVE11 IME11A -- -- ATU-II (channel 2) Rev.2.0, 07/03, page 938 of 960 Table A.1 Address (cont) Register Abbr. Bit Names Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Module ATU-II (channel 2) Address H'FFFFF602 TCNT2B H'FFFFF603 H'FFFFF604 GR2A H'FFFFF605 H'FFFFF606 GR2B H'FFFFF607 H'FFFFF608 GR2C H'FFFFF609 H'FFFFF60A GR2D H'FFFFF60B H'FFFFF60C GR2E H'FFFFF60D H'FFFFF60E GR2F H'FFFFF60F H'FFFFF610 GR2G H'FFFFF611 H'FFFFF612 GR2H H'FFFFF613 H'FFFFF614 OCR2A H'FFFFF615 H'FFFFF616 OCR2B H'FFFFF617 H'FFFFF618 OCR2C H'FFFFF619 H'FFFFF61A OCR2D H'FFFFF61B H'FFFFF61C OCR2E H'FFFFF61D H'FFFFF61E OCR2F H'FFFFF61F H'FFFFF620 OCR2G H'FFFFF621 H'FFFFF622 OCR2H H'FFFFF623 H'FFFFF624 OSBR2 H'FFFFF625 Rev.2.0, 07/03, page 939 of 960 Table A.1 Address (cont) Register Abbr. Bit Names Bit 7 -- -- -- -- -- -- -- IMF2H -- CMF2H -- IME2H -- CME2H -- Bit 6 IO2D2 IO2B2 IO2H2 IO2F2 -- -- -- IMF2G -- CMF2G -- IME2G -- CME2G -- Bit 5 IO2D1 IO2B1 IO2H1 IO2F1 Bit 4 IO2D0 IO2B0 IO2H0 IO2F0 Bit 3 -- -- -- -- Bit 2 IO2C2 IO2A2 IO2G2 IO2E2 Bit 1 IO2C1 IO2A1 IO2G1 IO2E1 Bit 0 IO2C0 IO2A0 IO2G0 IO2E0 Module ATU-II (channel 2) Address H'FFFFF626 TIOR2B H'FFFFF627 TIOR2A H'FFFFF628 TIOR2D H'FFFFF629 TIOR2C H'FFFFF62A TCR2B H'FFFFF62B TCR2A H'FFFFF62C TSR2A H'FFFFF62D H'FFFFF62E TSR2B H'FFFFF62F H'FFFFF630 TIER2A H'FFFFF631 H'FFFFF632 TIER2B H'FFFFF633 H'FFFFF634 -- to H'FFFFF63F H'FFFFF640 DCNT8A H'FFFFF641 H'FFFFF642 DNCT8B H'FFFFF643 H'FFFFF644 DNCT8C H'FFFFF645 H'FFFFF646 DCNT8D H'FFFFF647 H'FFFFF648 DCNT8E H'FFFFF649 H'FFFFF64A DCNT8F H'FFFFF64B H'FFFFF64C DCNT8G H'FFFFF64D H'FFFFF64E DCNT8H H'FFFFF64F H'FFFFF650 DCNT8I H'FFFFF651 CKEGB1 CKEGB0 CKSELB3 CKSELB2 CKSELB1 CKSELB0 CKEGA1 CKEGA0 CKSELA3 CKSELA2 CKSELA1 CKSELA0 -- IMF2F -- CMF2F -- IME2F -- CME2F -- -- IMF2E -- CMF2E -- IME2E -- CME2E -- -- IMF2D -- CMF2D -- IME2D -- CME2D -- -- IMF2C -- CMF2C -- IME2C -- CME2C -- -- IMF2B -- CMF2B -- IME2B -- CME2B -- OVF2A IMF2A OVF2B CMF2A OVE1A IME2A OVE2B CME2A -- -- ATU-II (channel 8) Rev.2.0, 07/03, page 940 of 960 Table A.1 Address (cont) Register Abbr. Bit Names Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Module ATU-II (channel 8) Address H'FFFFF652 DCNT8J H'FFFFF653 H'FFFFF654 DCNT8K H'FFFFF655 H'FFFFF656 DCNT8L H'FFFFF657 H'FFFFF658 DCNT8M H'FFFFF659 H'FFFFF65A DCNT8N H'FFFFF65B H'FFFFF65C DCNT8O H'FFFFF65D H'FFFFF65E DCNT8P H'FFFFF65F H'FFFFF660 RLDR8 H'FFFFF661 H'FFFFF662 TCNR H'FFFFF663 H'FFFFF664 OTR H'FFFFF665 H'FFFFF666 DSTR H'FFFFF667 H'FFFFF668 TCR8 H'FFFFF669 -- H'FFFFF66A TSR8 H'FFFFF66B H'FFFFF66C TIER8 H'FFFFF66D H'FFFFF66E RLDENR H'FFFFF66F -- to H'FFFFF67F H'FFFFF680 ECNT9A H'FFFFF681 -- H'FFFFF682 ECNT9B H'FFFFF683 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- CN8P CN8H OTEP OTEH DST8P DST8H -- -- OSF8P OSF8H OSE8P OSE8H RLDEN -- CN8O CN8G OTEO OTEG DST8O DST8G CN8N CN8F OTEN OTEF DST8N DST8F CN8M CN8E OTEM OTEE DST8M DST8E CN8L CN8D OTEL OTED DST8L DST8D CN8K CN8C OTEK OTEC DST8K DST8C CN8J CN8B OTEJ OTEB DST8J DST8B CN8I CN8A OTEI OTEA DST8I DST8A CKSELB2 CKSELB1 CKSELB0 -- -- OSF8O OSF8G OSE8O OSE8G -- -- -- OSF8N OSF8F OSE8N OSE8F -- -- -- OSF8M OSF8E OSE8M OSE8E -- -- -- OSF8L OSF8D OSE8L OSE8D -- -- CKSELA2 CKSELA1 CKSELA0 -- OSF8K OSF8C OSE8K OSE8C -- -- -- OSF8J OSF8B OSE8J OSE8B -- -- -- OSF8I OSF8A OSE8I OSE8A -- -- -- ATU-II (channel 9) Rev.2.0, 07/03, page 941 of 960 Table A.1 Address (cont) Register Abbr. Bit Names Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Module ATU-II (channel 9) Address H'FFFFF684 ECNT9C H'FFFFF685 -- H'FFFFF686 ECNT9D H'FFFFF687 -- H'FFFFF688 ECNT9E H'FFFFF689 -- H'FFFFF68A ECNT9F H'FFFFF68B -- H'FFFFF68C GR9A H'FFFFF68D -- H'FFFFF68E GR9B H'FFFFF68F -- H'FFFFF690 GR9C H'FFFFF691 -- H'FFFFF692 GR9D H'FFFFF693 -- H'FFFFF694 GR9E H'FFFFF695 -- H'FFFFF696 GR9F H'FFFFF697 -- H'FFFFF698 TCR9A H'FFFFF699 -- H'FFFFF69A TCR9B H'FFFFF69B -- H'FFFFF69C TCR9C H'FFFFF69D -- H'FFFFF69E TSR9 H'FFFFF69F H'FFFFF6A0 TIER9 H'FFFFF6A1 H'FFFFF6A2 -- to H'FFFFF6BF H'FFFFF6C0 TCNT10AH H'FFFFF6C1 H'FFFFF6C2 TCNT10AL H'FFFFF6C3 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- TRG3BEN EGSELB1 EGSELB0 -- -- -- -- -- TRG3AEN EGSELA1 EGSELA0 -- -- -- TRG3DEN EGSELD1 EGSELD0 -- -- -- -- -- -- -- -- -- -- -- -- TRG3CEN EGSELC1 EGSELC0 -- -- -- -- CMF9C -- CME9C -- -- -- EGSELF1 EGSELF0 -- -- -- CMF9F -- CME9F -- -- -- CMF9E -- CME9E -- -- -- CMF9D -- CME9D -- EGSELE1 EGSELE0 -- -- CMF9B -- CME9B -- -- -- CMF9A -- CME9A -- -- ATU-II (channel 10) Rev.2.0, 07/03, page 942 of 960 Table A.1 Address (cont) Register Abbr. Bit Names Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Module ATU-II (channel 10) Address H'FFFFF6C4 TCNT10B H'FFFFF6C5 -- H'FFFFF6C6 TCNT10C H'FFFFF6C7 H'FFFFF6C8 TCNT10D H'FFFFF6C9 -- H'FFFFF6CA TCNT10E H'FFFFF6CB H'FFFFF6CC TCNT10F H'FFFFF6CD H'FFFFF6CE TCNT10G H'FFFFF6CF H'FFFFF6D0 ICR10AH H'FFFFF6D1 H'FFFFF6D2 ICR10AL H'FFFFF6D3 H'FFFFF6D4 OCR10AH H'FFFFF6D5 H'FFFFF6D6 OCR10AL H'FFFFF6D7 H'FFFFF6D8 OCR10B H'FFFFF6D9 -- H'FFFFF6DA RLD10C H'FFFFF6DB H'FFFFF6DC GR10G H'FFFFF6DD H'FFFFF6DE TCNT10H H'FFFFF6DF -- H'FFFFF6E0 NCR10 H'FFFFF6E1 -- H'FFFFF6E2 TIOR10 H'FFFFF6E3 -- H'FFFFF6E4 TCR10 H'FFFFF6E5 -- H'FFFFF6E6 TCCLR10 H'FFFFF6E7 -- RLDEN -- -- CCS -- -- PIM1 -- -- PIM0 -- -- -- -- -- IO10G2 -- -- IO10G1 -- CKEG1 -- -- IO10G0 -- CKEG0 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- TRG2BEN TRG1BEN TRG2AEN TRG1AEN TRG0DEN NCE -- -- -- -- -- -- Rev.2.0, 07/03, page 943 of 960 Table A.1 Address (cont) Register Abbr. Bit Names Bit 7 -- -- -- -- -- Bit 6 -- -- -- -- -- Bit 5 -- -- -- -- -- Bit 4 -- -- -- IREG -- Bit 3 -- Bit 2 -- Bit 1 -- ICF10A -- ICE10A -- Bit 0 -- CMF10A -- CME10A -- -- Module ATU-II (channel 10) Address H'FFFFF6E8 TSR10 H'FFFFF6E9 H'FFFFF6EA TIER10 H'FFFFF6EB H'FFFFF6EC -- to H'FFFFF6FF H'FFFFF700 POPCR H'FFFFF701 H'FFFFF702 -- to H'FFFFF707 H'FFFFF708 SYSCR H'FFFFF709 -- H'FFFFF70A -- CMF10G CMF10B -- -- CME10G CME10B -- -- PULS7 ROE PULS7 SOE -- PULS6 ROE PULS6 SOE -- PULS5 ROE PULS5 SOE -- PULS4 ROE PULS4 SOE -- PULS3 ROE PULS3 SOE -- PULS2 ROE PULS2 SOE -- PULS1 ROE PULS1 SOE -- PULS0 ROE PULS0 SOE -- APC -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- AUDSRST RAME -- -- -- -- Powerdown state H'FFFFF70B MSTCR * -- H'FFFFF70C -- to H'FFFFF70F H'FFFFF710 CMSTR H'FFFFF711 H'FFFFF712 CMCSR0 H'FFFFF713 H'FFFFF714 CMCNT0 H'FFFFF715 H'FFFFF716 CMCOR0 H'FFFFF717 H'FFFFF718 CMCSR1 H'FFFFF719 H'FFFFF71A CMCNT1 H'FFFFF71B H'FFFFF71C CMCOR1 H'FFFFF71D H'FFFFF71E -- H'FFFFF71F -- -- -- -- CMF -- MSTOP3 MSTOP2 MSTOP1 MSTOP0 -- -- -- -- -- -- -- -- CMF -- -- -- CMIE -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- STR1 -- CKS1 -- STR0 -- CKS0 CMT -- CMIE -- -- -- -- -- -- -- -- -- CKS1 -- CKS0 -- -- -- -- -- -- -- -- -- -- -- -- -- -- Note: * This is the read address. The write address is H'FFFFF70A. For details, see section 24.2.4, Register Access. Rev.2.0, 07/03, page 944 of 960 Table A.1 Address (cont) Register Abbr. Bit Names Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 PA8IOR PA0IOR PA12MD PA8MD PA4MD PA0MD PA8DR PA0DR PH8IOR PH0IOR PH8MD PH0MD PH8DR PH0DR -- -- PB8IOR PB0IOR Port B A/D Port H Module Port A Address H'FFFFF720 PAIOR H'FFFFF721 H'FFFFF722 PACRH H'FFFFF723 H'FFFFF724 PACRL H'FFFFF725 H'FFFFF726 PADR H'FFFFF727 H'FFFFF728 PHIOR H'FFFFF729 H'FFFFF72A PHCR H'FFFFF72B H'FFFFF72C PHDR H'FFFFF72D PA15IOR PA14IOR PA13IOR PA12IOR PA11IOR PA10IOR PA9IOR PA7IOR -- -- -- -- PA15DR PA7DR PA6IOR PA15MD PA11MD PA7MD PA3MD PA14DR PA6DR PA5IOR -- -- -- -- PA13DR PA5DR PA4IOR PA14MD PA10MD PA6MD PA2MD PA12DR PA4DR PA3IOR -- -- -- -- PA11DR PA3DR PA2IOR PA13MD PA9MD PA5MD PA1MD PA10DR PA2DR PA1IOR -- -- -- -- PA9DR PA1DR PH15IOR PH14IOR PH13IOR PH12IOR PH11IOR PH10IOR PH9IOR PH7IOR PH6IOR PH5IOR PH4IOR PH3IOR PH2IOR PH1IOR PH15MD PH14MD PH13MD PH12MD PH11MD PH10MD PH9MD PH7MD PH15DR PH7DR PH6MD PH14DR PH6DR -- -- PH5MD PH13DR PH5DR -- -- PH4MD PH12DR PH4DR -- -- PH3MD PH11DR PH3DR -- -- PH2MD PH10DR PH2DR -- -- PH1MD PH9DR PH1DR -- -- H'FFFFF72E ADTRGR1 EXTRG H'FFFFF72F ADTRGR2 EXTRG H'FFFFF730 PBIOR H'FFFFF731 H'FFFFF732 PBCRH H'FFFFF733 H'FFFFF734 PBCRL H'FFFFF735 H'FFFFF736 PBIR H'FFFFF737 H'FFFFF738 PBDR H'FFFFF739 H'FFFFF73A PCIOR H'FFFFF73B H'FFFFF73C PCCR H'FFFFF73D H'FFFFF73E PCDR H'FFFFF73F H'FFFFF740 PDIOR H'FFFFF741 PB15IOR PB14IOR PB13IOR PB12IOR PB11IOR PB10IOR PB9IOR PB7IOR PB6IOR PB5IOR PB4IOR PB3IOR PB2IOR PB13MD PB9MD0 PB5MD0 PB1MD PB10IR PB2IR PB10DR PB2DR -- PC2IOR -- PC1MC -- PC2DR PB1IOR PB15MD1 PB15MD0 PB14MD1 PB14MD0 -- PB11MD1 PB11MD0 PB10MD1 PB10MD0 PB9MD1 PB7MD1 -- PB15IR PB7IR PB15DR PB7DR -- -- -- -- -- -- -- PD7IOR PB7MD0 PB3MD PB14IR PB6IR PB14DR PB6DR -- -- -- PC3MD -- -- -- PD6IOR PB6MD1 -- PB13IR PB5IR PB13DR PB5DR -- -- -- -- -- -- PB6MD0 PB2MD -- PB4IR PB12DR PB4DR -- PC4IOR -- PC2MC -- PC4DR PB5MD1 -- PB11IR PB3IR PB11DR PB3DR -- PC3IOR -- -- -- PC3DR PB12MD1 PB12MD0 PB8MD1 PB4MD1 -- PB9IR PB1IR PB9DR PB1DR -- PC1IOR -- -- -- PC1DR PB8MD0 PB4MD0 PB0MD PB8IR PB0IR PB8DR PB0DR -- PC0IOR PC4MC PC0MD -- PC0DR PD8IOR PD0IOR Port D Port C PD13IOR PD12IOR PD11IOR PD10IOR PD9IOR PD5IOR PD4IOR PD3IOR PD2IOR PD1IOR Rev.2.0, 07/03, page 945 of 960 Table A.1 Address (cont) Register Abbr. Bit Names Bit 7 -- -- -- -- -- PD7DR Bit 6 -- Bit 5 -- Bit 4 -- Bit 3 Bit 2 Bit 1 Bit 0 Module Address H'FFFFF742 PDCRH H'FFFFF743 H'FFFFF744 PDCRL H'FFFFF745 H'FFFFF746 PDDR H'FFFFF747 H'FFFFF748 PFIOR H'FFFFF749 H'FFFFF74A PFCRH H'FFFFF74B H'FFFFF74C PFCRL H'FFFFF74D H'FFFFF74E PFDR H'FFFFF74F H'FFFFF750 PEIOR H'FFFFF751 H'FFFFF752 PECR H'FFFFF753 H'FFFFF754 PEDR H'FFFFF755 H'FFFFF756 PLIOR H'FFFFF757 H'FFFFF758 PLCRH H'FFFFF759 H'FFFFF75A PLCRL H'FFFFF75B H'FFFFF75C PLIR H'FFFFF75D H'FFFFF75E PLDR H'FFFFF75F H'FFFFF760 PGIOR H'FFFFF761 H'FFFFF762 PGCR H'FFFFF763 H'FFFFF764 PGDR H'FFFFF765 PD13MD1 PD13MD0 -- PD9MD PD5MD PD1MD PD10DR PD2DR -- -- -- PD9DR PD1DR PD12MD Port D PD8MD PD4MD PD0MD PD8DR PD0DR PF8IOR PF0IOR PF12MD PF8MD PF4MD PF0MD PF8DR PF0DR PE8IOR PE0IOR PE8MD PE0MD PE8DR PE0DR PL8IOR PL0IOR PL12MD PL8MD PL4MD PL0MD0 PL8IR -- PL8DR PL0DR -- PG0IOR -- Port G Port L Port E Port F PD11MD -- PD7MD PD3MD -- PD6DR -- -- PD13DR PD5DR PD10MD -- PD6MD PD2MD PD12DR PD4DR -- -- PD11DR PD3DR PF15IOR PF14IOR PF13IOR PF12IOR PF11IOR PF10IOR PF9IOR PF7IOR CKHIZ -- -- -- PF15DR PF7DR PF6IOR PF15MD PF11MD PF7MD PF3MD PF14DR PF6DR PF5IOR -- -- -- -- PF13DR PF5DR PF4IOR PF14MD PF10MD PF6MD PF2MD PF12DR PF4DR PF3IOR -- -- PF5MD1 -- PF11DR PF3DR PF2IOR PF13MD PF9MD PF5MD0 PF1MD PF10DR PF2DR PF1IOR -- -- -- -- PF9DR PF1DR PE15IOR PE14IOR PE13IOR PE12IOR PE11IOR PE10IOR PE9IOR PE7IOR PE15MD PE7MD PE15DR PE7DR -- PL7IOR -- PE6IOR PE14MD PE6MD PE14DR PE6DR -- PL6IOR -- PE5IOR PE13MD PE5MD PE13DR PE5DR PE4IOR PE12MD PE4MD PE12DR PE4DR PE3IOR PE11MD PE3MD PE11DR PE3DR PE2IOR PE10MD PE2MD PE10DR PE2DR PE1IOR PE9MD PE1MD PE9DR PE1DR PL13IOR PL12IOR PL11IOR PL10IOR PL9IOR PL5IOR -- PL4IOR -- PL3IOR PL2IOR PL1IOR PL13MD1 PL13MD0 -- PL9MD0 PL5MD PL1MD0 -- -- PL10DR PL2DR -- PG2IOR -- PG1MD -- PG2DR -- -- -- PL9IR -- PL9DR PL1DR -- PG1IOR -- PL11MD1 PL11MD0 PL10MD1 PL10MD0 PL9MD1 -- -- -- PL7IR -- PL7DR -- -- -- PL7MD PL3MD -- -- -- PL6DR -- -- -- -- PL2MD1 -- -- PL13DR PL5DR -- -- -- PL6MD PL2MD0 -- -- PL12DR PL4DR -- -- -- -- PL1MD1 -- -- PL11DR PL3DR -- PG3IOR -- PG3MD1 PG3MD0 PG2MD1 PG2MD0 -- -- -- -- -- -- -- -- -- -- PG3DR PG0MD1 PG0MD0 -- PG1DR -- PG0DR Rev.2.0, 07/03, page 946 of 960 Table A.1 Address (cont) Register Abbr. Bit Names Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 PJ8IOR PJ0IOR PJ12MD PJ8MD PJ4MD PJ0MD PJ8DR PJ0DR -- -- PK8IOR PK0IOR PK12MD PK8MD PK4MD PK0MD PK8IR PK0IR PK8DR PK0DR -- -- Port K A/D Module Port J Address H'FFFFF766 PJIOR H'FFFFF767 H'FFFFF768 PJCRH H'FFFFF769 H'FFFFF76A PJCRL H'FFFFF76B H'FFFFF76C PJDR H'FFFFF76D H'FFFFF76E ADTRG0 H'FFFFF76F -- H'FFFFF770 PKIOR H'FFFFF771 H'FFFFF772 PKCRH H'FFFFF773 H'FFFFF774 PKCRL H'FFFFF775 H'FFFFF776 PKIR H'FFFFF777 H'FFFFF778 PKDR H'FFFFF779 H'FFFFF77A -- to H'FFFFF77F H'FFFFF780 PAPR H'FFFFF781 H'FFFFF782 PBPR H'FFFFF783 H'FFFFF784 PDPR H'FFFFF785 H'FFFFF786 PJPR H'FFFFF787 H'FFFFF788 PLPR H'FFFFF789 PJ15IOR PJ14IOR PJ13IOR PJ12IOR PJ11IOR PJ10IOR PJ9IOR PJ7IOR -- -- -- -- PJ15DR PJ7DR EXTRG -- PJ6IOR PJ15MD PJ11MD PJ7MD PJ3MD PJ14DR PJ6DR -- -- PJ5IOR -- -- -- -- PJ13DR PJ5DR -- -- PJ4IOR PJ14MD PJ10MD PJ6MD PJ2MD PJ12DR PJ4DR -- -- PJ3IOR -- -- -- -- PJ11DR PJ3DR -- -- PJ2IOR PJ13MD PJ9MD PJ5MD PJ1MD PJ10DR PJ2DR -- -- PJ1IOR -- -- -- -- PJ9DR PJ1DR -- -- PK15IOR PK14IOR PK13IOR PK12IOR PK11IOR PK10IOR PK9IOR PK7IOR -- -- -- -- PK15IR PK7IR PK15DR PK7DR -- PK6IOR PK15MD PK11MD PK7MD PK3MD PK14IR PK6IR PK14DR PK6DR -- PK5IOR -- -- -- -- PK13IR PK5IR PK13DR PK5DR -- PK4IOR PK14MD PK10MD PK6MD PK2MD PK12IR PK4IR PK12DR PK4DR -- PK3IOR -- -- -- -- PK11IR PK3IR PK11DR PK3DR -- PK2IOR PK13MD PK9MD PK5MD PK1MD PK10IR PK2IR PK10DR PK2DR -- PK1IOR -- -- -- -- PK9IR PK1IR PK9DR PK1DR -- PA15DR PA7DR PB15DR PB7DR -- PD7PR PJ15PR PJ7PR -- PL7PR PA14DR PA6DR PB14DR PB6DR -- PD6PR PJ14PR PJ6PR -- PL6PR PA13DR PA5DR PB13DR PB5DR PD13PR PD5PR PJ13PR PJ5PR PL13PR PL5PR PA12DR PA4DR PB12DR PB4DR PD12PR PD4PR PJ12PR PJ4PR PL12PR PL4PR PA11DR PA3DR PB11DR PB3DR PD11PR PD3PR PJ11PR PJ3PR PL11PR PL3PR PA10DR PA2DR PB10DR PB2DR PD10PR PD2PR PJ10PR PJ2PR PL10PR PL2PR PA9DR PA1DR PB9DR PB1DR PD9PR PD1PR PJ9PR PJ1PR PL9PR PL1PR PA8DR PA0DR PB8DR PB0DR PD8PR PD0PR PJ8PR PJ0PR PL8PR PL0PR Port A Port B Port D Port J Port L Rev.2.0, 07/03, page 947 of 960 Table A.1 Address (cont) Register Abbr. Bit Names Bit 7 -- Bit 6 -- Bit 5 -- Bit 4 -- Bit 3 -- Bit 2 -- Bit 1 -- Bit 0 -- Module -- Address H'FFFFF78A -- to H'FFFFF7BF H'FFFFF7C0 SDIR H'FFFFF7C1 H'FFFFF7C2 SDSR H'FFFFF7C3 H'FFFFF7C4 SDDRH H'FFFFF7C5 H'FFFFF7C6 SDDRL H'FFFFF7C7 H'FFFFF7C8 -- to H'FFFFF7FF H'FFFFF800 ADDR0H H'FFFFF801 ADDR0L H'FFFFF802 ADDR1H H'FFFFF803 ADDR1L H'FFFFF804 ADDR2H H'FFFFF805 ADDR2L H'FFFFF806 ADDR3H H'FFFFF807 ADDR3L H'FFFFF808 ADDR4H H'FFFFF809 ADDR4L H'FFFFF80A ADDR5H H'FFFFF80B ADDR5L H'FFFFF80C ADDR6H H'FFFFF80D ADDR6L H'FFFFF80E ADDR7H H'FFFFF80F ADDR7L TS3 -- -- -- TS2 -- -- -- TS1 -- -- -- TS0 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- SDTRF H-UDI -- -- -- -- -- -- -- -- -- AD9 AD1 AD9 AD1 AD9 AD1 AD9 AD1 AD9 AD1 AD9 AD1 AD9 AD1 AD9 AD1 AD8 AD0 AD8 AD0 AD8 AD0 AD8 AD0 AD8 AD0 AD8 AD0 AD8 AD0 AD8 AD0 AD7 -- AD7 -- AD7 -- AD7 -- AD7 -- AD7 -- AD7 -- AD7 -- AD6 -- AD6 -- AD6 -- AD6 -- AD6 -- AD6 -- AD6 -- AD6 -- AD5 -- AD5 -- AD5 -- AD5 -- AD5 -- AD5 -- AD5 -- AD5 -- AD4 -- AD4 -- AD4 -- AD4 -- AD4 -- AD4 -- AD4 -- AD4 -- AD3 -- AD3 -- AD3 -- AD3 -- AD3 -- AD3 -- AD3 -- AD3 -- AD2 -- AD2 -- AD2 -- AD2 -- AD2 -- AD2 -- AD2 -- AD2 -- A/D Rev.2.0, 07/03, page 948 of 960 Table A.1 Address (cont) Register Abbr. Bit Names Bit 7 AD9 AD1 AD9 AD1 Bit 6 AD8 AD0 AD8 AD0 AD8 AD0 AD8 AD0 ADIE CKS -- Bit 5 AD7 -- AD7 -- AD7 -- AD7 -- ADM1 ADST -- Bit 4 AD6 -- AD6 -- AD6 -- AD6 -- ADM0 ADCS -- Bit 3 AD5 -- AD5 -- AD5 -- AD5 -- CH3 -- -- Bit 2 AD4 -- AD4 -- AD4 -- AD4 -- CH2 -- -- Bit 1 AD3 -- AD3 -- AD3 -- AD3 -- CH1 -- -- Bit 0 AD2 -- AD2 -- AD2 -- AD2 -- CH0 -- -- Module A/D Address H'FFFFF810 ADDR8H H'FFFFF811 ADDR8L H'FFFFF812 ADDR9H H'FFFFF813 ADDR9L H'FFFFF814 ADDR10H AD9 H'FFFFF815 ADDR10L AD1 H'FFFFF816 ADDR11H AD9 H'FFFFF817 ADDR11L AD1 H'FFFFF818 ADCSR0 H'FFFFF819 ADCR0 H'FFFFF81A -- to H'FFFFF81F ADF TRGE -- H'FFFFF820 ADDR12H AD9 H'FFFFF821 ADDR12L AD1 H'FFFFF822 ADDR13H AD9 H'FFFFF823 ADDR13L AD1 H'FFFFF824 ADDR14H AD9 H'FFFFF825 ADDR14L AD1 H'FFFFF826 ADDR15H AD9 H'FFFFF827 ADDR15L AD1 H'FFFFF828 ADDR16H AD9 H'FFFFF829 ADDR16L AD1 H'FFFFF82A ADDR17H AD9 H'FFFFF82B ADDR17L AD1 H'FFFFF82C ADDR18H AD9 H'FFFFF82D ADDR18L AD1 H'FFFFF82E ADDR19H AD9 H'FFFFF82F ADDR19L AD1 H'FFFFF830 ADDR20H AD9 H'FFFFF831 ADDR20L AD1 H'FFFFF832 ADDR21H AD9 H'FFFFF833 ADDR21L AD1 H'FFFFF834 ADDR22H AD9 H'FFFFF835 ADDR22L AD1 H'FFFFF836 ADDR23H AD9 AD8 AD0 AD8 AD0 AD8 AD0 AD8 AD0 AD8 AD0 AD8 AD0 AD8 AD0 AD8 AD0 AD8 AD0 AD8 AD0 AD8 AD0 AD8 AD7 -- AD7 -- AD7 -- AD7 -- AD7 -- AD7 -- AD7 -- AD7 -- AD7 -- AD7 -- AD7 -- AD7 AD6 -- AD6 -- AD6 -- AD6 -- AD6 -- AD6 -- AD6 -- AD6 -- AD6 -- AD6 -- AD6 -- AD6 AD5 -- AD5 -- AD5 -- AD5 -- AD5 -- AD5 -- AD5 -- AD5 -- AD5 -- AD5 -- AD5 -- AD5 AD4 -- AD4 -- AD4 -- AD4 -- AD4 -- AD4 -- AD4 -- AD4 -- AD4 -- AD4 -- AD4 -- AD4 AD3 -- AD3 -- AD3 -- AD3 -- AD3 -- AD3 -- AD3 -- AD3 -- AD3 -- AD3 -- AD3 -- AD3 AD2 -- AD2 -- AD2 -- AD2 -- AD2 -- AD2 -- AD2 -- AD2 -- AD2 -- AD2 -- AD2 -- AD2 Rev.2.0, 07/03, page 949 of 960 Table A.1 Address (cont) Register Abbr. Bit Names Bit 7 Bit 6 AD0 ADIE CKS AD8 AD0 AD8 AD0 AD8 AD0 AD8 AD0 AD8 AD0 AD8 AD0 AD8 AD0 AD8 AD0 -- Bit 5 -- ADM1 ADST AD7 -- AD7 -- AD7 -- AD7 -- AD7 -- AD7 -- AD7 -- AD7 -- -- Bit 4 -- ADM0 ADCS AD6 -- AD6 -- AD6 -- AD6 -- AD6 -- AD6 -- AD6 -- AD6 -- -- Bit 3 -- CH3 -- AD5 -- AD5 -- AD5 -- AD5 -- AD5 -- AD5 -- AD5 -- AD5 -- -- Bit 2 -- CH2 -- AD4 -- AD4 -- AD4 -- AD4 -- AD4 -- AD4 -- AD4 -- AD4 -- -- Bit 1 -- CH1 -- AD3 -- AD3 -- AD3 -- AD3 -- AD3 -- AD3 -- AD3 -- AD3 -- -- Bit 0 -- CH0 -- AD2 -- AD2 -- AD2 -- AD2 -- AD2 -- AD2 -- AD2 -- AD2 -- -- Module A/D Address H'FFFFF837 ADDR23L AD1 H'FFFFF838 ADCSR1 H'FFFFF839 ADCR1 ADF TRGE H'FFFFF840 ADDR24H AD9 H'FFFFF841 ADDR24L AD1 H'FFFFF842 ADDR25H AD9 H'FFFFF843 ADDR25L AD1 H'FFFFF844 ADDR26H AD9 H'FFFFF845 ADDR26L AD1 H'FFFFF846 ADDR27H AD9 H'FFFFF847 ADDR27L AD1 H'FFFFF848 ADDR28H AD9 H'FFFFF849 ADDR28L AD1 H'FFFFF84A ADDR29H AD9 H'FFFFF84B ADDR29L AD1 H'FFFFF84C ADDR30H AD9 H'FFFFF84D ADDR30L AD1 H'FFFFF84E ADDR31H AD9 H'FFFFF84F ADDR31L AD1 H'FFFFF850 -- to H'FFFFF857 H'FFFFF858 ADCSR2 H'FFFFF859 ADCR2 H'FFFFF85A -- to H'FFFFF85F H'FFFFF83A -- to H'FFFFF83F -- ADF TRGE -- ADIE CKS -- ADM1 ADST -- ADM0 ADCS -- -- -- -- CH2 -- -- CH1 -- -- CH0 -- -- -- -- -- -- -- -- -- -- Rev.2.0, 07/03, page 950 of 960 A.2 Register States in Reset and Power-Down States Register States in Reset and Power-Down States Reset State Power-Down State Hardware Standby Initialized Software Standby Held Sleep Held Table A.2 Type CPU Name R0 to R15 SR GBR VBR MACH, MACL PR PC Power-On Initialized FPU FR0 to FR15 FPUL FPSCR Initialized Initialized Held Held Interrupt controller (INTC) IPRA to IPRL IOR ISR Initialized Initialized Held Held User break controller (UBC) UBARH, UBARL UBAMRH, UBAMRL UBBR UBCR Initialized Initialized Held Held Bus state controller (BSC) Direct memory access controller (DMAC) BCR1, BCR2 WCR SAR0 to SAR3 DAR0 to DAR3 DMATCR0 to DMATCR3 CHCR0 to CHCR3 DMAOR Initialized Initialized Held Held Initialized Initialized Initialized Held Advanced timer unit-II (ATU-II) BFR6A-D, BFR7A-D CYLR6A-D, CYLR7A-D DCNT8A-P DSTR Initialized Initialized Initialized Held Rev.2.0, 07/03, page 951 of 960 Table A.2 Register States in Reset and Power-Down States (cont) Reset State Power-Down State Hardware Standby Initialized Software Standby Initialized Sleep Held Type Advanced timer unit-II (ATU-II) Name DTR6A-D, DTR7A-D ECNT9A-F GR1A-H, GR2A-H GR3A-D, GR4A-D GR5A-D, GR9A-F GR10G, GR11A, 11B ICR0A-D, ICR10A ITVRR1, ITVRR2A, 2B NCR10 OCR1, OCR2A-H OCR10AH, 10AL OCR10B OSBR1, OSBR2 OTR PMDR PSCR1-4 PSTR RLD10C RLDENR RLDR8 TCCLR10 TCNR TCNT0H, L, TCNT1A 1B, TCNT2A, 2B TCNT3-5, TCNT6A-D TCNT7A-D TCNT10AH, 10AL TCNT10B-H, TCNT11 TCR1A, 1B TCR2A, 2B, TCR3-5 TCR6A, 6B, TCR7A 7B, TCR8, TCR9A-C TCR10, TCR11 Power-On Initialized Rev.2.0, 07/03, page 952 of 960 Table A.2 Register States in Reset and Power-Down States (cont) Reset State Power-Down State Hardware Standby Initialized Software Standby Initialized Sleep Held Type Advanced timer unit-II (ATU-II) Name TIER0, TIER1A, 1B TIER2A, 2B, TIER3 TIER6-11 TIOR0, TIOR1A-D TIOR2A-D, TIOR3A 3B, TIOR4A, 4B TIOR5A, 5B TIOR10,11 TMDR TNCT10E TRGMDR TSR0, TSR1A, 1B TSR2A, 2B, TSR3 TSR6-11 TSTR1-3 Power-On Initialized Advanced pulse controller (APC) Watchdog timer (WDT) POPCR TCNT TCSR RSTCSR Initialized Initialized Initialized Initialized Held Initialized Held Held Serial communication interface (SCI) SMR0 to SMR4 BRR0 to BRR4 SCR0 to SCR4 TDR0 to TDR4 SSR0 to SSR4 RDR0 to RDR4 SDCR0 to SDCR4 Initialized Initialized Held Held Intialized Held Initialized Initialized Initialized Held A/D converter ADDR0 (H/L) to ADDR31 (H/L) ADSCR0, ADCSR1 ADCSR2 ADCR0, ADCR1 ADCR2 Rev.2.0, 07/03, page 953 of 960 Table A.2 Register States in Reset and Power-Down States (cont) Reset State Power-Down State Hardware Standby Initialized Initialized Software Standby Initialized Initialized Sleep Held Held Type A/D converter Compare match timer (CMT) Name ADTRGR0, ADTRGR1 ADTRGR2 CMSTR CMCSR0, CMCSR1 CMCNT0, CMCNT1 CMCOR0, CMCOR1 Power-On Initialized Initialized Initialized Initialized Initialized Held Pin function controller (PFC) PAIOR, PBIOR PCIOR, PDIOR PEIOR, PFIOR PGIOR, PHIOR PJIOR, PKIOR, PLIOR PACRH, PACRL PBCRH, PBCRL PBIR, PCCR, PDCRH PDCRL, PECR PFCRH, PFCRL PGCR, PHCR, PJCRH PJCRL PKCRH PKCRL PKIR, PLCRH PLCRL,PLIR Initialized Initialized Held Held I/O ports PADR, PBDR, PCDR PDDR, PEDR, PFDR PGDE, PHDR, PJDR PKDR, PLDR PAPR, PBPR, PDPR, PJPR, PLPR Initialized Initialized Held Held Pin value Initialized Held Initialized Held Held Initialized/ Held* Initialized Pin value Held Flash ROM RAMER FCCS FPCS FECS FKEY FMATS FTDAR Held Initialized Rev.2.0, 07/03, page 954 of 960 Table A.2 Register States in Reset and Power-Down States (cont) Reset State Power-Down State Hardware Standby Initialized Software Standby Held Sleep Held Type Power-down state related Name SBYCR SYSCR MSTCR Power-On Initialized Controller area network (HCAN) MCR GSR BCR MBCR TXPR TXCR TXACK ABACK RXPR RFPR IRR MBIMR IMR REC TEC UMSR LAFML LAFMH Initialized Initialized Initialized Held MC0 [1:8] to MC15 [1:8] Underfined MD0 [1:8] to MD15 [1:8] High-performance SDIR user debug SDSR interface (H-UDI) SDDRH, SDDRL Held Underfined Underfined Held Held Held Note: * Bit 7 (FLER) is held, and bit 0 (SCO) is initialized. Rev.2.0, 07/03, page 955 of 960 Appendix B Pin States Tables B.1, B.2, and B.3 show the SH7055SF pin states. Table B.1 Pin States Pin State Reset State Power-On ROMless Expanded SingleH-UDI Expanded Mode Mode with Chip Hardware Software Module Mode Standby Standby Standby 8 Bits 16 Bits ROM O O I I I I I I I I O -- -- I -- -- O Z -- I H H H -- -- -- -- -- -- Z -- -- -- -- -- -- -- Z L Z I Z I I I I I Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z H*1 L I I I I I I I I O* Z Z I Z O* Z Z Z Z Z Z Z Z Z Z K*1 K*1 K* 1 1 1 Power-Down State Type Clock Pin Name CK*2 XTAL EXTAL PLLCAP AUD Module Standby O O I I I I I I I I O I O I I O O I/O I/O I O O O O I I I/O I/O I/O BusReleased State O O I I I I I I I I O I L I I O Z Z Z I Z Z Z Z I I I/O I/O I/O O O I I I I I I I I O I O I I O O I/O I/O I O O O O I I I/O I/O I/O System RES control FWE HSTBY MD0 MD1 MD2 WDTOVF BREQ BACK Interrupt NMI IRQ0 to IRQ7 IRQOUT Address A0 to A21 bus Data bus D0 to D7 D8 to D15 Bus control WAIT WRH, WRL RD CS0 CS1 to CS3 Port ATU-II POD TI0A to TI0D TIO1A to TIO1H TIO2A to TIO2H TIO3A to TIO3D Rev.2.0, 07/03, page 956 of 960 Table B.1 Pin States (cont) Pin State Reset State Power-On ROMless Expanded SingleH-UDI Expanded Mode Mode with Chip Hardware Software Module Mode Standby Standby Standby 8 Bits 16 Bits ROM -- -- -- -- -- -- -- -- -- -- -- -- Z -- -- I Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z I Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z -- Z Z Z Z Z Z K*1 K*1 O*1 O*1 O*1 Z Z K*1 Z K*1 O*1 Z Z Z O*1 I O*1 O*1 Z O*1 K*1 K*1 K*1 K*1 K*1 K*1 K* 1 Power-Down State Type ATU-II Pin Name TIO4A to TIO4D TIO5A to TIO5D TO6A to TO6D TO7A to TO7D TO8A to TO8P TI9A to TI9F TI10 TIO11A, TIO11B TCLKA, TCLKB AUD Module Standby I/O I/O O O O I I I/O I I/O O I I I O I O O I Z I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O BusReleased State I/O I/O O O O I I I/O I I/O O I I I O I O O I O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O O O O I I I/O I I/O O I I I O I O O I O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O SCI SCK0 to SCK4 TxD0 to TxD4 RxD0 to RxD4 A/D AN0 to AN31 converter ADTRG0, ADTRG1 ADEND AVref APC HCAN PULS0 to PULS7 -- HTxD0, HTxD1 HRxD0, HRxD1 UBCTRG PA0 to PA15 PB0 to PB15 PC0 to PC4 PD0 to PD13 PE0 to PE15 PF0 to PF5 PF6 to PF10 PH11 to PF15 PG0 to PG3 PH0 to PH7 PH8 to PH15 PJ0 to PJ15 PK0 to PK15 PL0 to PL13 -- -- -- Z Z Z Z -- -- -- Z Z -- Z Z Z Z UBC I/O port K*1 K*1 K*1 K*1 K*1 K*1 K*1 Rev.2.0, 07/03, page 957 of 960 Table B.2 Pin States Pin State Reset State Power-On ROMless Expanded SingleH-UDI Expanded Mode Mode with Chip Hardware Software Module Mode Standby Standby Standby 8 Bits 16 Bits ROM I I I O I Z Z Z Z Z I I I O I Z Z Z Z Z AUD Module Standby I I I O I BusReleased No State Connection I I I O I Pulled up internally Pulled up internally Pulled up internally O/Z Pulled up internally Power-Down State Type Pin Name H-UDI TMS TRST TDI TDO TCK Table B.3 Pin States Pin State Hardware Standby AUD Module Standby Z Z Z AUD Reset (AUDRST = L) AUDRST L input I When AUDMD = H: I When AUDMD = L: K (pulled up internally) When AUDMD = H: I When AUDMD = L: K (pulled up internally) When AUDMD = H: I When AUDMD = L: K (pulled up internally) Software Standby AUDSRST = 1/ Normal Operation H input I When AUDMD = H: I/O When AUDMD = L: O When AUDMD = H: I When AUDMD = L: O When AUDMD = H: I When AUDMD = L: O Type AUD Pin Name AUDRST AUDMD AUDATA0 to AUDATA3 AUDCK No Connection Pulled down internally Pulled up internally Pulled up internally Z Pulled up internally AUDSYNC Z Pulled up internally -- I O H L Z K : : : : : : : Not initial value Input Output High-level output Low-level output High impedance Input pins become high-impedance, output pins retain their state. Notes: *1 When the port impedance bit (HIZ) in the standby control register (SBYCR) is set to 1, output pins become high-impedance. *2 When the CKHIZ bit in PFCRH is set to 1, becomes high-impedance unconditionally. Rev.2.0, 07/03, page 958 of 960 Appendix C Product Lineup Table C.1 SH7055S F-ZTAT Product Lineup Model Name F-ZTAT HD64F7055S Mark Model Name 64F7055F40 Package 256-pin (FP-256H) Product Type SH7055SF Rev.2.0, 07/03, page 959 of 960 Appendix D Package Dimensions Figure D.1 shows the FP-256H package dimensions of the SH7055SF. 42.6 0.3 40 204 205 129 128 As of January, 2002 Unit: mm 30.6 0.3 28 256 1 *0.22 0.05 0.20 0.04 0.10 M 1.25 76 77 3.56 Max 0.5 *0.17 0.05 0.15 0.04 1.3 1.25 0 -8 0.5 0.2 0.08 0.15 0.10 3.20 *Dimension including the plating thickness Base material dimension Package Code JEDEC JEITA Mass (reference value) FP-256H -- Conforms 7.5 g Figure D.1 Package Dimensions (FP-256H) Rev.2.0, 07/03, page 960 of 960 SH-2E SH7055S F-ZTAT TM Hardware Manual Publication Date: 1st Edition, May, 2002 Rev.2.00, July 17, 2003 Published by: Sales Strategic Planning Div. Renesas Technology Corp. Edited by: Technical Documentation & Information Department Renesas Kodaira Semiconductor Co., Ltd. 2002, 2003 Renesas Technology Corp. All rights reserved. Printed in Japan. Sales Strategic Planning Div. Nippon Bldg., 2-6-2, Ohte-machi, Chiyoda-ku, Tokyo 100-0004, Japan RENESAS SALES OFFICES Refer to "http://www.renesas.com/en/network" for the latest and detailed information. Renesas Technology America, Inc. 450 Holger Way, San Jose, CA 95134-1368, U.S.A Tel: <1> (408) 382-7500, Fax: <1> (408) 382-7501 Renesas Technology Europe Limited Dukes Meadow, Millboard Road, Bourne End, Buckinghamshire, SL8 5FH, U.K. Tel: <44> (1628) 585-100, Fax: <44> (1628) 585-900 Renesas Technology (Shanghai) Co., Ltd. Unit 204, 205, AZIACenter, No.1233 Lujiazui Ring Rd, Pudong District, Shanghai, China 200120 Tel: <86> (21) 5877-1818, Fax: <86> (21) 6887-7898 Renesas Technology Hong Kong Ltd. 7th Floor, North Tower, World Finance Centre, Harbour City, 1 Canton Road, Tsimshatsui, Kowloon, Hong Kong Tel: <852> 2265-6688, Fax: <852> 2730-6071 Renesas Technology Taiwan Co., Ltd. 10th Floor, No.99, Fushing North Road, Taipei, Taiwan Tel: <886> (2) 2715-2888, Fax: <886> (2) 2713-2999 Renesas Technology Singapore Pte. Ltd. 1 Harbour Front Avenue, #06-10, Keppel Bay Tower, Singapore 098632 Tel: <65> 6213-0200, Fax: <65> 6278-8001 Renesas Technology Korea Co., Ltd. Kukje Center Bldg. 18th Fl., 191, 2-ka, Hangang-ro, Yongsan-ku, Seoul 140-702, Korea Tel: <82> (2) 796-3115, Fax: <82> (2) 796-2145 http://www.renesas.com Renesas Technology Malaysia Sdn. Bhd Unit 906, Block B, Menara Amcorp, Amcorp Trade Centre, No.18, Jalan Persiaran Barat, 46050 Petaling Jaya, Selangor Darul Ehsan, Malaysia Tel: <603> 7955-9390, Fax: <603> 7955-9510 Colophon 6.0 SH-2E SH7055S F-ZTAT Hardware Manual TM 2-6-2, Ote-machi, Chiyoda-ku, Tokyo, 100-0004, Japan REJ09B0045-0200H |
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